1 /* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Suspend support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqdomain.h> 24 #include <linux/of_address.h> 25 #include <linux/err.h> 26 #include <linux/regulator/machine.h> 27 #include <linux/soc/samsung/exynos-pmu.h> 28 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 30 #include <asm/cacheflush.h> 31 #include <asm/hardware/cache-l2x0.h> 32 #include <asm/firmware.h> 33 #include <asm/mcpm.h> 34 #include <asm/smp_scu.h> 35 #include <asm/suspend.h> 36 37 #include <mach/map.h> 38 39 #include <plat/pm-common.h> 40 41 #include "common.h" 42 43 #define REG_TABLE_END (-1U) 44 45 #define EXYNOS5420_CPU_STATE 0x28 46 47 /** 48 * struct exynos_wkup_irq - PMU IRQ to mask mapping 49 * @hwirq: Hardware IRQ signal of the PMU 50 * @mask: Mask in PMU wake-up mask register 51 */ 52 struct exynos_wkup_irq { 53 unsigned int hwirq; 54 u32 mask; 55 }; 56 57 struct exynos_pm_data { 58 const struct exynos_wkup_irq *wkup_irq; 59 unsigned int wake_disable_mask; 60 61 void (*pm_prepare)(void); 62 void (*pm_resume_prepare)(void); 63 void (*pm_resume)(void); 64 int (*pm_suspend)(void); 65 int (*cpu_suspend)(unsigned long); 66 }; 67 68 static const struct exynos_pm_data *pm_data; 69 70 static int exynos5420_cpu_state; 71 static unsigned int exynos_pmu_spare3; 72 73 /* 74 * GIC wake-up support 75 */ 76 77 static u32 exynos_irqwake_intmask = 0xffffffff; 78 79 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 80 { 73, BIT(1) }, /* RTC alarm */ 81 { 74, BIT(2) }, /* RTC tick */ 82 { /* sentinel */ }, 83 }; 84 85 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 86 { 44, BIT(1) }, /* RTC alarm */ 87 { 45, BIT(2) }, /* RTC tick */ 88 { /* sentinel */ }, 89 }; 90 91 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 92 { 43, BIT(1) }, /* RTC alarm */ 93 { 44, BIT(2) }, /* RTC tick */ 94 { /* sentinel */ }, 95 }; 96 97 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 98 { 99 const struct exynos_wkup_irq *wkup_irq; 100 101 if (!pm_data->wkup_irq) 102 return -ENOENT; 103 wkup_irq = pm_data->wkup_irq; 104 105 while (wkup_irq->mask) { 106 if (wkup_irq->hwirq == data->hwirq) { 107 if (!state) 108 exynos_irqwake_intmask |= wkup_irq->mask; 109 else 110 exynos_irqwake_intmask &= ~wkup_irq->mask; 111 return 0; 112 } 113 ++wkup_irq; 114 } 115 116 return -ENOENT; 117 } 118 119 static struct irq_chip exynos_pmu_chip = { 120 .name = "PMU", 121 .irq_eoi = irq_chip_eoi_parent, 122 .irq_mask = irq_chip_mask_parent, 123 .irq_unmask = irq_chip_unmask_parent, 124 .irq_retrigger = irq_chip_retrigger_hierarchy, 125 .irq_set_wake = exynos_irq_set_wake, 126 #ifdef CONFIG_SMP 127 .irq_set_affinity = irq_chip_set_affinity_parent, 128 #endif 129 }; 130 131 static int exynos_pmu_domain_translate(struct irq_domain *d, 132 struct irq_fwspec *fwspec, 133 unsigned long *hwirq, 134 unsigned int *type) 135 { 136 if (is_of_node(fwspec->fwnode)) { 137 if (fwspec->param_count != 3) 138 return -EINVAL; 139 140 /* No PPI should point to this domain */ 141 if (fwspec->param[0] != 0) 142 return -EINVAL; 143 144 *hwirq = fwspec->param[1]; 145 *type = fwspec->param[2]; 146 return 0; 147 } 148 149 return -EINVAL; 150 } 151 152 static int exynos_pmu_domain_alloc(struct irq_domain *domain, 153 unsigned int virq, 154 unsigned int nr_irqs, void *data) 155 { 156 struct irq_fwspec *fwspec = data; 157 struct irq_fwspec parent_fwspec; 158 irq_hw_number_t hwirq; 159 int i; 160 161 if (fwspec->param_count != 3) 162 return -EINVAL; /* Not GIC compliant */ 163 if (fwspec->param[0] != 0) 164 return -EINVAL; /* No PPI should point to this domain */ 165 166 hwirq = fwspec->param[1]; 167 168 for (i = 0; i < nr_irqs; i++) 169 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 170 &exynos_pmu_chip, NULL); 171 172 parent_fwspec = *fwspec; 173 parent_fwspec.fwnode = domain->parent->fwnode; 174 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 175 &parent_fwspec); 176 } 177 178 static const struct irq_domain_ops exynos_pmu_domain_ops = { 179 .translate = exynos_pmu_domain_translate, 180 .alloc = exynos_pmu_domain_alloc, 181 .free = irq_domain_free_irqs_common, 182 }; 183 184 static int __init exynos_pmu_irq_init(struct device_node *node, 185 struct device_node *parent) 186 { 187 struct irq_domain *parent_domain, *domain; 188 189 if (!parent) { 190 pr_err("%s: no parent, giving up\n", node->full_name); 191 return -ENODEV; 192 } 193 194 parent_domain = irq_find_host(parent); 195 if (!parent_domain) { 196 pr_err("%s: unable to obtain parent domain\n", node->full_name); 197 return -ENXIO; 198 } 199 200 pmu_base_addr = of_iomap(node, 0); 201 202 if (!pmu_base_addr) { 203 pr_err("%s: failed to find exynos pmu register\n", 204 node->full_name); 205 return -ENOMEM; 206 } 207 208 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, 209 node, &exynos_pmu_domain_ops, 210 NULL); 211 if (!domain) { 212 iounmap(pmu_base_addr); 213 return -ENOMEM; 214 } 215 216 /* 217 * Clear the OF_POPULATED flag set in of_irq_init so that 218 * later the Exynos PMU platform device won't be skipped. 219 */ 220 of_node_clear_flag(node, OF_POPULATED); 221 222 return 0; 223 } 224 225 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init) 226 227 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); 228 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); 229 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); 230 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); 231 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); 232 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); 233 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); 234 235 static int exynos_cpu_do_idle(void) 236 { 237 /* issue the standby signal into the pm unit. */ 238 cpu_do_idle(); 239 240 pr_info("Failed to suspend the system\n"); 241 return 1; /* Aborting suspend */ 242 } 243 static void exynos_flush_cache_all(void) 244 { 245 flush_cache_all(); 246 outer_flush_all(); 247 } 248 249 static int exynos_cpu_suspend(unsigned long arg) 250 { 251 exynos_flush_cache_all(); 252 return exynos_cpu_do_idle(); 253 } 254 255 static int exynos3250_cpu_suspend(unsigned long arg) 256 { 257 flush_cache_all(); 258 return exynos_cpu_do_idle(); 259 } 260 261 static int exynos5420_cpu_suspend(unsigned long arg) 262 { 263 /* MCPM works with HW CPU identifiers */ 264 unsigned int mpidr = read_cpuid_mpidr(); 265 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 266 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 267 268 writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); 269 270 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { 271 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); 272 mcpm_cpu_suspend(); 273 } 274 275 pr_info("Failed to suspend the system\n"); 276 277 /* return value != 0 means failure */ 278 return 1; 279 } 280 281 static void exynos_pm_set_wakeup_mask(void) 282 { 283 /* Set wake-up mask registers */ 284 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 285 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 286 } 287 288 static void exynos_pm_enter_sleep_mode(void) 289 { 290 /* Set value of power down register for sleep mode */ 291 exynos_sys_powerdown_conf(SYS_SLEEP); 292 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1); 293 } 294 295 static void exynos_pm_prepare(void) 296 { 297 exynos_set_delayed_reset_assertion(false); 298 299 /* Set wake-up mask registers */ 300 exynos_pm_set_wakeup_mask(); 301 302 exynos_pm_enter_sleep_mode(); 303 304 /* ensure at least INFORM0 has the resume address */ 305 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 306 } 307 308 static void exynos3250_pm_prepare(void) 309 { 310 unsigned int tmp; 311 312 /* Set wake-up mask registers */ 313 exynos_pm_set_wakeup_mask(); 314 315 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); 316 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 317 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); 318 319 exynos_pm_enter_sleep_mode(); 320 321 /* ensure at least INFORM0 has the resume address */ 322 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 323 } 324 325 static void exynos5420_pm_prepare(void) 326 { 327 unsigned int tmp; 328 329 /* Set wake-up mask registers */ 330 exynos_pm_set_wakeup_mask(); 331 332 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); 333 /* 334 * The cpu state needs to be saved and restored so that the 335 * secondary CPUs will enter low power start. Though the U-Boot 336 * is setting the cpu state with low power flag, the kernel 337 * needs to restore it back in case, the primary cpu fails to 338 * suspend for any reason. 339 */ 340 exynos5420_cpu_state = readl_relaxed(sysram_base_addr + 341 EXYNOS5420_CPU_STATE); 342 343 exynos_pm_enter_sleep_mode(); 344 345 /* ensure at least INFORM0 has the resume address */ 346 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 347 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); 348 349 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); 350 tmp &= ~EXYNOS5_USE_RETENTION; 351 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); 352 353 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 354 tmp |= EXYNOS5420_UFS; 355 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 356 357 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); 358 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; 359 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); 360 361 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 362 tmp |= EXYNOS5420_EMULATION; 363 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 364 365 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 366 tmp |= EXYNOS5420_EMULATION; 367 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 368 } 369 370 371 static int exynos_pm_suspend(void) 372 { 373 exynos_pm_central_suspend(); 374 375 /* Setting SEQ_OPTION register */ 376 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 377 S5P_CENTRAL_SEQ_OPTION); 378 379 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 380 exynos_cpu_save_register(); 381 382 return 0; 383 } 384 385 static int exynos5420_pm_suspend(void) 386 { 387 u32 this_cluster; 388 389 exynos_pm_central_suspend(); 390 391 /* Setting SEQ_OPTION register */ 392 393 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 394 if (!this_cluster) 395 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, 396 S5P_CENTRAL_SEQ_OPTION); 397 else 398 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, 399 S5P_CENTRAL_SEQ_OPTION); 400 return 0; 401 } 402 403 static void exynos_pm_resume(void) 404 { 405 u32 cpuid = read_cpuid_part(); 406 407 if (exynos_pm_central_resume()) 408 goto early_wakeup; 409 410 if (cpuid == ARM_CPU_PART_CORTEX_A9) 411 scu_enable(S5P_VA_SCU); 412 413 if (call_firmware_op(resume) == -ENOSYS 414 && cpuid == ARM_CPU_PART_CORTEX_A9) 415 exynos_cpu_restore_register(); 416 417 early_wakeup: 418 419 /* Clear SLEEP mode set in INFORM1 */ 420 pmu_raw_writel(0x0, S5P_INFORM1); 421 exynos_set_delayed_reset_assertion(true); 422 } 423 424 static void exynos3250_pm_resume(void) 425 { 426 u32 cpuid = read_cpuid_part(); 427 428 if (exynos_pm_central_resume()) 429 goto early_wakeup; 430 431 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); 432 433 if (call_firmware_op(resume) == -ENOSYS 434 && cpuid == ARM_CPU_PART_CORTEX_A9) 435 exynos_cpu_restore_register(); 436 437 early_wakeup: 438 439 /* Clear SLEEP mode set in INFORM1 */ 440 pmu_raw_writel(0x0, S5P_INFORM1); 441 } 442 443 static void exynos5420_prepare_pm_resume(void) 444 { 445 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 446 WARN_ON(mcpm_cpu_powered_up()); 447 } 448 449 static void exynos5420_pm_resume(void) 450 { 451 unsigned long tmp; 452 453 /* Restore the CPU0 low power state register */ 454 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); 455 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, 456 EXYNOS5_ARM_CORE0_SYS_PWR_REG); 457 458 /* Restore the sysram cpu state register */ 459 writel_relaxed(exynos5420_cpu_state, 460 sysram_base_addr + EXYNOS5420_CPU_STATE); 461 462 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, 463 S5P_CENTRAL_SEQ_OPTION); 464 465 if (exynos_pm_central_resume()) 466 goto early_wakeup; 467 468 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); 469 470 early_wakeup: 471 472 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 473 tmp &= ~EXYNOS5420_UFS; 474 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 475 476 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 477 tmp &= ~EXYNOS5420_EMULATION; 478 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 479 480 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 481 tmp &= ~EXYNOS5420_EMULATION; 482 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 483 484 /* Clear SLEEP mode set in INFORM1 */ 485 pmu_raw_writel(0x0, S5P_INFORM1); 486 } 487 488 /* 489 * Suspend Ops 490 */ 491 492 static int exynos_suspend_enter(suspend_state_t state) 493 { 494 int ret; 495 496 s3c_pm_debug_init(); 497 498 S3C_PMDBG("%s: suspending the system...\n", __func__); 499 500 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 501 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 502 503 if (exynos_irqwake_intmask == -1U 504 && exynos_get_eint_wake_mask() == -1U) { 505 pr_err("%s: No wake-up sources!\n", __func__); 506 pr_err("%s: Aborting sleep\n", __func__); 507 return -EINVAL; 508 } 509 510 s3c_pm_save_uarts(); 511 if (pm_data->pm_prepare) 512 pm_data->pm_prepare(); 513 flush_cache_all(); 514 s3c_pm_check_store(); 515 516 ret = call_firmware_op(suspend); 517 if (ret == -ENOSYS) 518 ret = cpu_suspend(0, pm_data->cpu_suspend); 519 if (ret) 520 return ret; 521 522 if (pm_data->pm_resume_prepare) 523 pm_data->pm_resume_prepare(); 524 s3c_pm_restore_uarts(); 525 526 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 527 pmu_raw_readl(S5P_WAKEUP_STAT)); 528 529 s3c_pm_check_restore(); 530 531 S3C_PMDBG("%s: resuming the system...\n", __func__); 532 533 return 0; 534 } 535 536 static int exynos_suspend_prepare(void) 537 { 538 int ret; 539 540 /* 541 * REVISIT: It would be better if struct platform_suspend_ops 542 * .prepare handler get the suspend_state_t as a parameter to 543 * avoid hard-coding the suspend to mem state. It's safe to do 544 * it now only because the suspend_valid_only_mem function is 545 * used as the .valid callback used to check if a given state 546 * is supported by the platform anyways. 547 */ 548 ret = regulator_suspend_prepare(PM_SUSPEND_MEM); 549 if (ret) { 550 pr_err("Failed to prepare regulators for suspend (%d)\n", ret); 551 return ret; 552 } 553 554 s3c_pm_check_prepare(); 555 556 return 0; 557 } 558 559 static void exynos_suspend_finish(void) 560 { 561 int ret; 562 563 s3c_pm_check_cleanup(); 564 565 ret = regulator_suspend_finish(); 566 if (ret) 567 pr_warn("Failed to resume regulators from suspend (%d)\n", ret); 568 } 569 570 static const struct platform_suspend_ops exynos_suspend_ops = { 571 .enter = exynos_suspend_enter, 572 .prepare = exynos_suspend_prepare, 573 .finish = exynos_suspend_finish, 574 .valid = suspend_valid_only_mem, 575 }; 576 577 static const struct exynos_pm_data exynos3250_pm_data = { 578 .wkup_irq = exynos3250_wkup_irq, 579 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 580 .pm_suspend = exynos_pm_suspend, 581 .pm_resume = exynos3250_pm_resume, 582 .pm_prepare = exynos3250_pm_prepare, 583 .cpu_suspend = exynos3250_cpu_suspend, 584 }; 585 586 static const struct exynos_pm_data exynos4_pm_data = { 587 .wkup_irq = exynos4_wkup_irq, 588 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 589 .pm_suspend = exynos_pm_suspend, 590 .pm_resume = exynos_pm_resume, 591 .pm_prepare = exynos_pm_prepare, 592 .cpu_suspend = exynos_cpu_suspend, 593 }; 594 595 static const struct exynos_pm_data exynos5250_pm_data = { 596 .wkup_irq = exynos5250_wkup_irq, 597 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 598 .pm_suspend = exynos_pm_suspend, 599 .pm_resume = exynos_pm_resume, 600 .pm_prepare = exynos_pm_prepare, 601 .cpu_suspend = exynos_cpu_suspend, 602 }; 603 604 static const struct exynos_pm_data exynos5420_pm_data = { 605 .wkup_irq = exynos5250_wkup_irq, 606 .wake_disable_mask = (0x7F << 7) | (0x1F << 1), 607 .pm_resume_prepare = exynos5420_prepare_pm_resume, 608 .pm_resume = exynos5420_pm_resume, 609 .pm_suspend = exynos5420_pm_suspend, 610 .pm_prepare = exynos5420_pm_prepare, 611 .cpu_suspend = exynos5420_cpu_suspend, 612 }; 613 614 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { 615 { 616 .compatible = "samsung,exynos3250-pmu", 617 .data = &exynos3250_pm_data, 618 }, { 619 .compatible = "samsung,exynos4210-pmu", 620 .data = &exynos4_pm_data, 621 }, { 622 .compatible = "samsung,exynos4212-pmu", 623 .data = &exynos4_pm_data, 624 }, { 625 .compatible = "samsung,exynos4412-pmu", 626 .data = &exynos4_pm_data, 627 }, { 628 .compatible = "samsung,exynos5250-pmu", 629 .data = &exynos5250_pm_data, 630 }, { 631 .compatible = "samsung,exynos5420-pmu", 632 .data = &exynos5420_pm_data, 633 }, 634 { /*sentinel*/ }, 635 }; 636 637 static struct syscore_ops exynos_pm_syscore_ops; 638 639 void __init exynos_pm_init(void) 640 { 641 const struct of_device_id *match; 642 struct device_node *np; 643 u32 tmp; 644 645 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); 646 if (!np) { 647 pr_err("Failed to find PMU node\n"); 648 return; 649 } 650 651 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 652 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 653 return; 654 } 655 656 pm_data = (const struct exynos_pm_data *) match->data; 657 658 /* All wakeup disable */ 659 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 660 tmp |= pm_data->wake_disable_mask; 661 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 662 663 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; 664 exynos_pm_syscore_ops.resume = pm_data->pm_resume; 665 666 register_syscore_ops(&exynos_pm_syscore_ops); 667 suspend_set_ops(&exynos_suspend_ops); 668 } 669