1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes 15 * it to save wrong values... Be aware! 16 */ 17#include <linux/config.h> 18 19#include <asm/memory.h> 20#include <asm/glue.h> 21#include <asm/vfpmacros.h> 22#include <asm/arch/entry-macro.S> 23#include <asm/thread_notify.h> 24 25#include "entry-header.S" 26 27/* 28 * Interrupt handling. Preserves r7, r8, r9 29 */ 30 .macro irq_handler 311: get_irqnr_and_base r0, r6, r5, lr 32 movne r1, sp 33 @ 34 @ routine called with r0 = irq number, r1 = struct pt_regs * 35 @ 36 adrne lr, 1b 37 bne asm_do_IRQ 38 39#ifdef CONFIG_SMP 40 /* 41 * XXX 42 * 43 * this macro assumes that irqstat (r6) and base (r5) are 44 * preserved from get_irqnr_and_base above 45 */ 46 test_for_ipi r0, r6, r5, lr 47 movne r0, sp 48 adrne lr, 1b 49 bne do_IPI 50 51#ifdef CONFIG_LOCAL_TIMERS 52 test_for_ltirq r0, r6, r5, lr 53 movne r0, sp 54 adrne lr, 1b 55 bne do_local_timer 56#endif 57#endif 58 59 .endm 60 61/* 62 * Invalid mode handlers 63 */ 64 .macro inv_entry, reason 65 sub sp, sp, #S_FRAME_SIZE 66 stmib sp, {r1 - lr} 67 mov r1, #\reason 68 .endm 69 70__pabt_invalid: 71 inv_entry BAD_PREFETCH 72 b common_invalid 73 74__dabt_invalid: 75 inv_entry BAD_DATA 76 b common_invalid 77 78__irq_invalid: 79 inv_entry BAD_IRQ 80 b common_invalid 81 82__und_invalid: 83 inv_entry BAD_UNDEFINSTR 84 85 @ 86 @ XXX fall through to common_invalid 87 @ 88 89@ 90@ common_invalid - generic code for failed exception (re-entrant version of handlers) 91@ 92common_invalid: 93 zero_fp 94 95 ldmia r0, {r4 - r6} 96 add r0, sp, #S_PC @ here for interlock avoidance 97 mov r7, #-1 @ "" "" "" "" 98 str r4, [sp] @ save preserved r0 99 stmia r0, {r5 - r7} @ lr_<exception>, 100 @ cpsr_<exception>, "old_r0" 101 102 mov r0, sp 103 and r2, r6, #0x1f 104 b bad_mode 105 106/* 107 * SVC mode handlers 108 */ 109 110#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 111#define SPFIX(code...) code 112#else 113#define SPFIX(code...) 114#endif 115 116 .macro svc_entry 117 sub sp, sp, #S_FRAME_SIZE 118 SPFIX( tst sp, #4 ) 119 SPFIX( bicne sp, sp, #4 ) 120 stmib sp, {r1 - r12} 121 122 ldmia r0, {r1 - r3} 123 add r5, sp, #S_SP @ here for interlock avoidance 124 mov r4, #-1 @ "" "" "" "" 125 add r0, sp, #S_FRAME_SIZE @ "" "" "" "" 126 SPFIX( addne r0, r0, #4 ) 127 str r1, [sp] @ save the "real" r0 copied 128 @ from the exception stack 129 130 mov r1, lr 131 132 @ 133 @ We are now ready to fill in the remaining blanks on the stack: 134 @ 135 @ r0 - sp_svc 136 @ r1 - lr_svc 137 @ r2 - lr_<exception>, already fixed up for correct return/restart 138 @ r3 - spsr_<exception> 139 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 140 @ 141 stmia r5, {r0 - r4} 142 .endm 143 144 .align 5 145__dabt_svc: 146 svc_entry 147 148 @ 149 @ get ready to re-enable interrupts if appropriate 150 @ 151 mrs r9, cpsr 152 tst r3, #PSR_I_BIT 153 biceq r9, r9, #PSR_I_BIT 154 155 @ 156 @ Call the processor-specific abort handler: 157 @ 158 @ r2 - aborted context pc 159 @ r3 - aborted context cpsr 160 @ 161 @ The abort handler must return the aborted address in r0, and 162 @ the fault status register in r1. r9 must be preserved. 163 @ 164#ifdef MULTI_ABORT 165 ldr r4, .LCprocfns 166 mov lr, pc 167 ldr pc, [r4] 168#else 169 bl CPU_ABORT_HANDLER 170#endif 171 172 @ 173 @ set desired IRQ state, then call main handler 174 @ 175 msr cpsr_c, r9 176 mov r2, sp 177 bl do_DataAbort 178 179 @ 180 @ IRQs off again before pulling preserved data off the stack 181 @ 182 disable_irq 183 184 @ 185 @ restore SPSR and restart the instruction 186 @ 187 ldr r0, [sp, #S_PSR] 188 msr spsr_cxsf, r0 189 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 190 191 .align 5 192__irq_svc: 193 svc_entry 194 195#ifdef CONFIG_PREEMPT 196 get_thread_info tsk 197 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 198 add r7, r8, #1 @ increment it 199 str r7, [tsk, #TI_PREEMPT] 200#endif 201 202 irq_handler 203#ifdef CONFIG_PREEMPT 204 ldr r0, [tsk, #TI_FLAGS] @ get flags 205 tst r0, #_TIF_NEED_RESCHED 206 blne svc_preempt 207preempt_return: 208 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value 209 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 210 teq r0, r7 211 strne r0, [r0, -r0] @ bug() 212#endif 213 ldr r0, [sp, #S_PSR] @ irqs are already disabled 214 msr spsr_cxsf, r0 215 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 216 217 .ltorg 218 219#ifdef CONFIG_PREEMPT 220svc_preempt: 221 teq r8, #0 @ was preempt count = 0 222 ldreq r6, .LCirq_stat 223 movne pc, lr @ no 224 ldr r0, [r6, #4] @ local_irq_count 225 ldr r1, [r6, #8] @ local_bh_count 226 adds r0, r0, r1 227 movne pc, lr 228 mov r7, #0 @ preempt_schedule_irq 229 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 2301: bl preempt_schedule_irq @ irq en/disable is done inside 231 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 232 tst r0, #_TIF_NEED_RESCHED 233 beq preempt_return @ go again 234 b 1b 235#endif 236 237 .align 5 238__und_svc: 239 svc_entry 240 241 @ 242 @ call emulation code, which returns using r9 if it has emulated 243 @ the instruction, or the more conventional lr if we are to treat 244 @ this as a real undefined instruction 245 @ 246 @ r0 - instruction 247 @ 248 ldr r0, [r2, #-4] 249 adr r9, 1f 250 bl call_fpe 251 252 mov r0, sp @ struct pt_regs *regs 253 bl do_undefinstr 254 255 @ 256 @ IRQs off again before pulling preserved data off the stack 257 @ 2581: disable_irq 259 260 @ 261 @ restore SPSR and restart the instruction 262 @ 263 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 264 msr spsr_cxsf, lr 265 ldmia sp, {r0 - pc}^ @ Restore SVC registers 266 267 .align 5 268__pabt_svc: 269 svc_entry 270 271 @ 272 @ re-enable interrupts if appropriate 273 @ 274 mrs r9, cpsr 275 tst r3, #PSR_I_BIT 276 biceq r9, r9, #PSR_I_BIT 277 msr cpsr_c, r9 278 279 @ 280 @ set args, then call main handler 281 @ 282 @ r0 - address of faulting instruction 283 @ r1 - pointer to registers on stack 284 @ 285 mov r0, r2 @ address (pc) 286 mov r1, sp @ regs 287 bl do_PrefetchAbort @ call abort handler 288 289 @ 290 @ IRQs off again before pulling preserved data off the stack 291 @ 292 disable_irq 293 294 @ 295 @ restore SPSR and restart the instruction 296 @ 297 ldr r0, [sp, #S_PSR] 298 msr spsr_cxsf, r0 299 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 300 301 .align 5 302.LCcralign: 303 .word cr_alignment 304#ifdef MULTI_ABORT 305.LCprocfns: 306 .word processor 307#endif 308.LCfp: 309 .word fp_enter 310#ifdef CONFIG_PREEMPT 311.LCirq_stat: 312 .word irq_stat 313#endif 314 315/* 316 * User mode handlers 317 * 318 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 319 */ 320 321#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 322#error "sizeof(struct pt_regs) must be a multiple of 8" 323#endif 324 325 .macro usr_entry 326 sub sp, sp, #S_FRAME_SIZE 327 stmib sp, {r1 - r12} 328 329 ldmia r0, {r1 - r3} 330 add r0, sp, #S_PC @ here for interlock avoidance 331 mov r4, #-1 @ "" "" "" "" 332 333 str r1, [sp] @ save the "real" r0 copied 334 @ from the exception stack 335 336#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 337#ifndef CONFIG_MMU 338#warning "NPTL on non MMU needs fixing" 339#else 340 @ make sure our user space atomic helper is aborted 341 cmp r2, #TASK_SIZE 342 bichs r3, r3, #PSR_Z_BIT 343#endif 344#endif 345 346 @ 347 @ We are now ready to fill in the remaining blanks on the stack: 348 @ 349 @ r2 - lr_<exception>, already fixed up for correct return/restart 350 @ r3 - spsr_<exception> 351 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 352 @ 353 @ Also, separately save sp_usr and lr_usr 354 @ 355 stmia r0, {r2 - r4} 356 stmdb r0, {sp, lr}^ 357 358 @ 359 @ Enable the alignment trap while in kernel mode 360 @ 361 alignment_trap r0 362 363 @ 364 @ Clear FP to mark the first stack frame 365 @ 366 zero_fp 367 .endm 368 369 .align 5 370__dabt_usr: 371 usr_entry 372 373 @ 374 @ Call the processor-specific abort handler: 375 @ 376 @ r2 - aborted context pc 377 @ r3 - aborted context cpsr 378 @ 379 @ The abort handler must return the aborted address in r0, and 380 @ the fault status register in r1. 381 @ 382#ifdef MULTI_ABORT 383 ldr r4, .LCprocfns 384 mov lr, pc 385 ldr pc, [r4] 386#else 387 bl CPU_ABORT_HANDLER 388#endif 389 390 @ 391 @ IRQs on, then call the main handler 392 @ 393 enable_irq 394 mov r2, sp 395 adr lr, ret_from_exception 396 b do_DataAbort 397 398 .align 5 399__irq_usr: 400 usr_entry 401 402 get_thread_info tsk 403#ifdef CONFIG_PREEMPT 404 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 405 add r7, r8, #1 @ increment it 406 str r7, [tsk, #TI_PREEMPT] 407#endif 408 409 irq_handler 410#ifdef CONFIG_PREEMPT 411 ldr r0, [tsk, #TI_PREEMPT] 412 str r8, [tsk, #TI_PREEMPT] 413 teq r0, r7 414 strne r0, [r0, -r0] 415#endif 416 417 mov why, #0 418 b ret_to_user 419 420 .ltorg 421 422 .align 5 423__und_usr: 424 usr_entry 425 426 tst r3, #PSR_T_BIT @ Thumb mode? 427 bne fpundefinstr @ ignore FP 428 sub r4, r2, #4 429 430 @ 431 @ fall through to the emulation code, which returns using r9 if 432 @ it has emulated the instruction, or the more conventional lr 433 @ if we are to treat this as a real undefined instruction 434 @ 435 @ r0 - instruction 436 @ 4371: ldrt r0, [r4] 438 adr r9, ret_from_exception 439 adr lr, fpundefinstr 440 @ 441 @ fallthrough to call_fpe 442 @ 443 444/* 445 * The out of line fixup for the ldrt above. 446 */ 447 .section .fixup, "ax" 4482: mov pc, r9 449 .previous 450 .section __ex_table,"a" 451 .long 1b, 2b 452 .previous 453 454/* 455 * Check whether the instruction is a co-processor instruction. 456 * If yes, we need to call the relevant co-processor handler. 457 * 458 * Note that we don't do a full check here for the co-processor 459 * instructions; all instructions with bit 27 set are well 460 * defined. The only instructions that should fault are the 461 * co-processor instructions. However, we have to watch out 462 * for the ARM6/ARM7 SWI bug. 463 * 464 * Emulators may wish to make use of the following registers: 465 * r0 = instruction opcode. 466 * r2 = PC+4 467 * r10 = this threads thread_info structure. 468 */ 469call_fpe: 470 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 471#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 472 and r8, r0, #0x0f000000 @ mask out op-code bits 473 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 474#endif 475 moveq pc, lr 476 get_thread_info r10 @ get current thread 477 and r8, r0, #0x00000f00 @ mask out CP number 478 mov r7, #1 479 add r6, r10, #TI_USED_CP 480 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 481#ifdef CONFIG_IWMMXT 482 @ Test if we need to give access to iWMMXt coprocessors 483 ldr r5, [r10, #TI_FLAGS] 484 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 485 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 486 bcs iwmmxt_task_enable 487#endif 488 add pc, pc, r8, lsr #6 489 mov r0, r0 490 491 mov pc, lr @ CP#0 492 b do_fpe @ CP#1 (FPE) 493 b do_fpe @ CP#2 (FPE) 494 mov pc, lr @ CP#3 495#ifdef CONFIG_CRUNCH 496 b crunch_task_enable @ CP#4 (MaverickCrunch) 497 b crunch_task_enable @ CP#5 (MaverickCrunch) 498 b crunch_task_enable @ CP#6 (MaverickCrunch) 499#else 500 mov pc, lr @ CP#4 501 mov pc, lr @ CP#5 502 mov pc, lr @ CP#6 503#endif 504 mov pc, lr @ CP#7 505 mov pc, lr @ CP#8 506 mov pc, lr @ CP#9 507#ifdef CONFIG_VFP 508 b do_vfp @ CP#10 (VFP) 509 b do_vfp @ CP#11 (VFP) 510#else 511 mov pc, lr @ CP#10 (VFP) 512 mov pc, lr @ CP#11 (VFP) 513#endif 514 mov pc, lr @ CP#12 515 mov pc, lr @ CP#13 516 mov pc, lr @ CP#14 (Debug) 517 mov pc, lr @ CP#15 (Control) 518 519do_fpe: 520 enable_irq 521 ldr r4, .LCfp 522 add r10, r10, #TI_FPSTATE @ r10 = workspace 523 ldr pc, [r4] @ Call FP module USR entry point 524 525/* 526 * The FP module is called with these registers set: 527 * r0 = instruction 528 * r2 = PC+4 529 * r9 = normal "successful" return address 530 * r10 = FP workspace 531 * lr = unrecognised FP instruction return address 532 */ 533 534 .data 535ENTRY(fp_enter) 536 .word fpundefinstr 537 .text 538 539fpundefinstr: 540 mov r0, sp 541 adr lr, ret_from_exception 542 b do_undefinstr 543 544 .align 5 545__pabt_usr: 546 usr_entry 547 548 enable_irq @ Enable interrupts 549 mov r0, r2 @ address (pc) 550 mov r1, sp @ regs 551 bl do_PrefetchAbort @ call abort handler 552 /* fall through */ 553/* 554 * This is the return code to user mode for abort handlers 555 */ 556ENTRY(ret_from_exception) 557 get_thread_info tsk 558 mov why, #0 559 b ret_to_user 560 561/* 562 * Register switch for ARMv3 and ARMv4 processors 563 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 564 * previous and next are guaranteed not to be the same. 565 */ 566ENTRY(__switch_to) 567 add ip, r1, #TI_CPU_SAVE 568 ldr r3, [r2, #TI_TP_VALUE] 569 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 570#ifdef CONFIG_MMU 571 ldr r6, [r2, #TI_CPU_DOMAIN] 572#endif 573#if __LINUX_ARM_ARCH__ >= 6 574#ifdef CONFIG_CPU_32v6K 575 clrex 576#else 577 strex r5, r4, [ip] @ Clear exclusive monitor 578#endif 579#endif 580#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) 581 mra r4, r5, acc0 582 stmia ip, {r4, r5} 583#endif 584#if defined(CONFIG_HAS_TLS_REG) 585 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 586#elif !defined(CONFIG_TLS_REG_EMUL) 587 mov r4, #0xffff0fff 588 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 589#endif 590#ifdef CONFIG_MMU 591 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 592#endif 593#if defined(CONFIG_IWMMXT) 594 bl iwmmxt_task_switch 595#elif defined(CONFIG_CPU_XSCALE) 596 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra 597 ldmib r4, {r4, r5} 598 mar acc0, r4, r5 599#endif 600 mov r5, r0 601 add r4, r2, #TI_CPU_SAVE 602 ldr r0, =thread_notify_head 603 mov r1, #THREAD_NOTIFY_SWITCH 604 bl atomic_notifier_call_chain 605 mov r0, r5 606 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 607 608 __INIT 609 610/* 611 * User helpers. 612 * 613 * These are segment of kernel provided user code reachable from user space 614 * at a fixed address in kernel memory. This is used to provide user space 615 * with some operations which require kernel help because of unimplemented 616 * native feature and/or instructions in many ARM CPUs. The idea is for 617 * this code to be executed directly in user mode for best efficiency but 618 * which is too intimate with the kernel counter part to be left to user 619 * libraries. In fact this code might even differ from one CPU to another 620 * depending on the available instruction set and restrictions like on 621 * SMP systems. In other words, the kernel reserves the right to change 622 * this code as needed without warning. Only the entry points and their 623 * results are guaranteed to be stable. 624 * 625 * Each segment is 32-byte aligned and will be moved to the top of the high 626 * vector page. New segments (if ever needed) must be added in front of 627 * existing ones. This mechanism should be used only for things that are 628 * really small and justified, and not be abused freely. 629 * 630 * User space is expected to implement those things inline when optimizing 631 * for a processor that has the necessary native support, but only if such 632 * resulting binaries are already to be incompatible with earlier ARM 633 * processors due to the use of unsupported instructions other than what 634 * is provided here. In other words don't make binaries unable to run on 635 * earlier processors just for the sake of not using these kernel helpers 636 * if your compiled code is not going to use the new instructions for other 637 * purpose. 638 */ 639 640 .align 5 641 .globl __kuser_helper_start 642__kuser_helper_start: 643 644/* 645 * Reference prototype: 646 * 647 * void __kernel_memory_barrier(void) 648 * 649 * Input: 650 * 651 * lr = return address 652 * 653 * Output: 654 * 655 * none 656 * 657 * Clobbered: 658 * 659 * the Z flag might be lost 660 * 661 * Definition and user space usage example: 662 * 663 * typedef void (__kernel_dmb_t)(void); 664 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 665 * 666 * Apply any needed memory barrier to preserve consistency with data modified 667 * manually and __kuser_cmpxchg usage. 668 * 669 * This could be used as follows: 670 * 671 * #define __kernel_dmb() \ 672 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 673 * : : : "r0", "lr","cc" ) 674 */ 675 676__kuser_memory_barrier: @ 0xffff0fa0 677 678#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) 679 mcr p15, 0, r0, c7, c10, 5 @ dmb 680#endif 681 mov pc, lr 682 683 .align 5 684 685/* 686 * Reference prototype: 687 * 688 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 689 * 690 * Input: 691 * 692 * r0 = oldval 693 * r1 = newval 694 * r2 = ptr 695 * lr = return address 696 * 697 * Output: 698 * 699 * r0 = returned value (zero or non-zero) 700 * C flag = set if r0 == 0, clear if r0 != 0 701 * 702 * Clobbered: 703 * 704 * r3, ip, flags 705 * 706 * Definition and user space usage example: 707 * 708 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 709 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 710 * 711 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 712 * Return zero if *ptr was changed or non-zero if no exchange happened. 713 * The C flag is also set if *ptr was changed to allow for assembly 714 * optimization in the calling code. 715 * 716 * Notes: 717 * 718 * - This routine already includes memory barriers as needed. 719 * 720 * - A failure might be transient, i.e. it is possible, although unlikely, 721 * that "failure" be returned even if *ptr == oldval. 722 * 723 * For example, a user space atomic_add implementation could look like this: 724 * 725 * #define atomic_add(ptr, val) \ 726 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 727 * register unsigned int __result asm("r1"); \ 728 * asm volatile ( \ 729 * "1: @ atomic_add\n\t" \ 730 * "ldr r0, [r2]\n\t" \ 731 * "mov r3, #0xffff0fff\n\t" \ 732 * "add lr, pc, #4\n\t" \ 733 * "add r1, r0, %2\n\t" \ 734 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 735 * "bcc 1b" \ 736 * : "=&r" (__result) \ 737 * : "r" (__ptr), "rIL" (val) \ 738 * : "r0","r3","ip","lr","cc","memory" ); \ 739 * __result; }) 740 */ 741 742__kuser_cmpxchg: @ 0xffff0fc0 743 744#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 745 746 /* 747 * Poor you. No fast solution possible... 748 * The kernel itself must perform the operation. 749 * A special ghost syscall is used for that (see traps.c). 750 */ 751 stmfd sp!, {r7, lr} 752 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 753 orr r7, r7, #0xf0 754 swi #0x9ffff0 755 ldmfd sp!, {r7, pc} 756 757#elif __LINUX_ARM_ARCH__ < 6 758 759 /* 760 * Theory of operation: 761 * 762 * We set the Z flag before loading oldval. If ever an exception 763 * occurs we can not be sure the loaded value will still be the same 764 * when the exception returns, therefore the user exception handler 765 * will clear the Z flag whenever the interrupted user code was 766 * actually from the kernel address space (see the usr_entry macro). 767 * 768 * The post-increment on the str is used to prevent a race with an 769 * exception happening just after the str instruction which would 770 * clear the Z flag although the exchange was done. 771 */ 772#ifdef CONFIG_MMU 773 teq ip, ip @ set Z flag 774 ldr ip, [r2] @ load current val 775 add r3, r2, #1 @ prepare store ptr 776 teqeq ip, r0 @ compare with oldval if still allowed 777 streq r1, [r3, #-1]! @ store newval if still allowed 778 subs r0, r2, r3 @ if r2 == r3 the str occured 779#else 780#warning "NPTL on non MMU needs fixing" 781 mov r0, #-1 782 adds r0, r0, #0 783#endif 784 mov pc, lr 785 786#else 787 788#ifdef CONFIG_SMP 789 mcr p15, 0, r0, c7, c10, 5 @ dmb 790#endif 791 ldrex r3, [r2] 792 subs r3, r3, r0 793 strexeq r3, r1, [r2] 794 rsbs r0, r3, #0 795#ifdef CONFIG_SMP 796 mcr p15, 0, r0, c7, c10, 5 @ dmb 797#endif 798 mov pc, lr 799 800#endif 801 802 .align 5 803 804/* 805 * Reference prototype: 806 * 807 * int __kernel_get_tls(void) 808 * 809 * Input: 810 * 811 * lr = return address 812 * 813 * Output: 814 * 815 * r0 = TLS value 816 * 817 * Clobbered: 818 * 819 * the Z flag might be lost 820 * 821 * Definition and user space usage example: 822 * 823 * typedef int (__kernel_get_tls_t)(void); 824 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 825 * 826 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 827 * 828 * This could be used as follows: 829 * 830 * #define __kernel_get_tls() \ 831 * ({ register unsigned int __val asm("r0"); \ 832 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 833 * : "=r" (__val) : : "lr","cc" ); \ 834 * __val; }) 835 */ 836 837__kuser_get_tls: @ 0xffff0fe0 838 839#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 840 841 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 842 mov pc, lr 843 844#else 845 846 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 847 mov pc, lr 848 849#endif 850 851 .rep 5 852 .word 0 @ pad up to __kuser_helper_version 853 .endr 854 855/* 856 * Reference declaration: 857 * 858 * extern unsigned int __kernel_helper_version; 859 * 860 * Definition and user space usage example: 861 * 862 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 863 * 864 * User space may read this to determine the curent number of helpers 865 * available. 866 */ 867 868__kuser_helper_version: @ 0xffff0ffc 869 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 870 871 .globl __kuser_helper_end 872__kuser_helper_end: 873 874 875/* 876 * Vector stubs. 877 * 878 * This code is copied to 0xffff0200 so we can use branches in the 879 * vectors, rather than ldr's. Note that this code must not 880 * exceed 0x300 bytes. 881 * 882 * Common stub entry macro: 883 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 884 * 885 * SP points to a minimal amount of processor-private memory, the address 886 * of which is copied into r0 for the mode specific abort handler. 887 */ 888 .macro vector_stub, name, mode, correction=0 889 .align 5 890 891vector_\name: 892 .if \correction 893 sub lr, lr, #\correction 894 .endif 895 896 @ 897 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 898 @ (parent CPSR) 899 @ 900 stmia sp, {r0, lr} @ save r0, lr 901 mrs lr, spsr 902 str lr, [sp, #8] @ save spsr 903 904 @ 905 @ Prepare for SVC32 mode. IRQs remain disabled. 906 @ 907 mrs r0, cpsr 908 eor r0, r0, #(\mode ^ SVC_MODE) 909 msr spsr_cxsf, r0 910 911 @ 912 @ the branch table must immediately follow this code 913 @ 914 and lr, lr, #0x0f 915 mov r0, sp 916 ldr lr, [pc, lr, lsl #2] 917 movs pc, lr @ branch to handler in SVC mode 918 .endm 919 920 .globl __stubs_start 921__stubs_start: 922/* 923 * Interrupt dispatcher 924 */ 925 vector_stub irq, IRQ_MODE, 4 926 927 .long __irq_usr @ 0 (USR_26 / USR_32) 928 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 929 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 930 .long __irq_svc @ 3 (SVC_26 / SVC_32) 931 .long __irq_invalid @ 4 932 .long __irq_invalid @ 5 933 .long __irq_invalid @ 6 934 .long __irq_invalid @ 7 935 .long __irq_invalid @ 8 936 .long __irq_invalid @ 9 937 .long __irq_invalid @ a 938 .long __irq_invalid @ b 939 .long __irq_invalid @ c 940 .long __irq_invalid @ d 941 .long __irq_invalid @ e 942 .long __irq_invalid @ f 943 944/* 945 * Data abort dispatcher 946 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 947 */ 948 vector_stub dabt, ABT_MODE, 8 949 950 .long __dabt_usr @ 0 (USR_26 / USR_32) 951 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 952 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 953 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 954 .long __dabt_invalid @ 4 955 .long __dabt_invalid @ 5 956 .long __dabt_invalid @ 6 957 .long __dabt_invalid @ 7 958 .long __dabt_invalid @ 8 959 .long __dabt_invalid @ 9 960 .long __dabt_invalid @ a 961 .long __dabt_invalid @ b 962 .long __dabt_invalid @ c 963 .long __dabt_invalid @ d 964 .long __dabt_invalid @ e 965 .long __dabt_invalid @ f 966 967/* 968 * Prefetch abort dispatcher 969 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 970 */ 971 vector_stub pabt, ABT_MODE, 4 972 973 .long __pabt_usr @ 0 (USR_26 / USR_32) 974 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 975 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 976 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 977 .long __pabt_invalid @ 4 978 .long __pabt_invalid @ 5 979 .long __pabt_invalid @ 6 980 .long __pabt_invalid @ 7 981 .long __pabt_invalid @ 8 982 .long __pabt_invalid @ 9 983 .long __pabt_invalid @ a 984 .long __pabt_invalid @ b 985 .long __pabt_invalid @ c 986 .long __pabt_invalid @ d 987 .long __pabt_invalid @ e 988 .long __pabt_invalid @ f 989 990/* 991 * Undef instr entry dispatcher 992 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 993 */ 994 vector_stub und, UND_MODE 995 996 .long __und_usr @ 0 (USR_26 / USR_32) 997 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 998 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 999 .long __und_svc @ 3 (SVC_26 / SVC_32) 1000 .long __und_invalid @ 4 1001 .long __und_invalid @ 5 1002 .long __und_invalid @ 6 1003 .long __und_invalid @ 7 1004 .long __und_invalid @ 8 1005 .long __und_invalid @ 9 1006 .long __und_invalid @ a 1007 .long __und_invalid @ b 1008 .long __und_invalid @ c 1009 .long __und_invalid @ d 1010 .long __und_invalid @ e 1011 .long __und_invalid @ f 1012 1013 .align 5 1014 1015/*============================================================================= 1016 * Undefined FIQs 1017 *----------------------------------------------------------------------------- 1018 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1019 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1020 * Basically to switch modes, we *HAVE* to clobber one register... brain 1021 * damage alert! I don't think that we can execute any code in here in any 1022 * other mode than FIQ... Ok you can switch to another mode, but you can't 1023 * get out of that mode without clobbering one register. 1024 */ 1025vector_fiq: 1026 disable_fiq 1027 subs pc, lr, #4 1028 1029/*============================================================================= 1030 * Address exception handler 1031 *----------------------------------------------------------------------------- 1032 * These aren't too critical. 1033 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1034 */ 1035 1036vector_addrexcptn: 1037 b vector_addrexcptn 1038 1039/* 1040 * We group all the following data together to optimise 1041 * for CPUs with separate I & D caches. 1042 */ 1043 .align 5 1044 1045.LCvswi: 1046 .word vector_swi 1047 1048 .globl __stubs_end 1049__stubs_end: 1050 1051 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1052 1053 .globl __vectors_start 1054__vectors_start: 1055 swi SYS_ERROR0 1056 b vector_und + stubs_offset 1057 ldr pc, .LCvswi + stubs_offset 1058 b vector_pabt + stubs_offset 1059 b vector_dabt + stubs_offset 1060 b vector_addrexcptn + stubs_offset 1061 b vector_irq + stubs_offset 1062 b vector_fiq + stubs_offset 1063 1064 .globl __vectors_end 1065__vectors_end: 1066 1067 .data 1068 1069 .globl cr_alignment 1070 .globl cr_no_alignment 1071cr_alignment: 1072 .space 4 1073cr_no_alignment: 1074 .space 4 1075