xref: /linux/arch/arm/include/asm/mpu.h (revision 3eb66e91a25497065c5322b1268cbc3953642227)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ARM_MPU_H
3 #define __ARM_MPU_H
4 
5 /* MPUIR layout */
6 #define MPUIR_nU		1
7 #define MPUIR_DREGION		8
8 #define MPUIR_IREGION		16
9 #define MPUIR_DREGION_SZMASK	(0xFF << MPUIR_DREGION)
10 #define MPUIR_IREGION_SZMASK	(0xFF << MPUIR_IREGION)
11 
12 /* ID_MMFR0 data relevant to MPU */
13 #define MMFR0_PMSA		(0xF << 4)
14 #define MMFR0_PMSAv7		(3 << 4)
15 #define MMFR0_PMSAv8		(4 << 4)
16 
17 /* MPU D/I Size Register fields */
18 #define PMSAv7_RSR_SZ		1
19 #define PMSAv7_RSR_EN		0
20 #define PMSAv7_RSR_SD		8
21 
22 /* Number of subregions (SD) */
23 #define PMSAv7_NR_SUBREGS	8
24 #define PMSAv7_MIN_SUBREG_SIZE	256
25 
26 /* The D/I RSR value for an enabled region spanning the whole of memory */
27 #define PMSAv7_RSR_ALL_MEM	63
28 
29 /* Individual bits in the DR/IR ACR */
30 #define PMSAv7_ACR_XN		(1 << 12)
31 #define PMSAv7_ACR_SHARED	(1 << 2)
32 
33 /* C, B and TEX[2:0] bits only have semantic meanings when grouped */
34 #define PMSAv7_RGN_CACHEABLE		0xB
35 #define PMSAv7_RGN_SHARED_CACHEABLE	(PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED)
36 #define PMSAv7_RGN_STRONGLY_ORDERED	0
37 
38 /* Main region should only be shared for SMP */
39 #ifdef CONFIG_SMP
40 #define PMSAv7_RGN_NORMAL	(PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED)
41 #else
42 #define PMSAv7_RGN_NORMAL	PMSAv7_RGN_CACHEABLE
43 #endif
44 
45 /* Access permission bits of ACR (only define those that we use)*/
46 #define PMSAv7_AP_PL1RO_PL0NA	(0x5 << 8)
47 #define PMSAv7_AP_PL1RW_PL0RW	(0x3 << 8)
48 #define PMSAv7_AP_PL1RW_PL0R0	(0x2 << 8)
49 #define PMSAv7_AP_PL1RW_PL0NA	(0x1 << 8)
50 
51 #define PMSAv8_BAR_XN		1
52 
53 #define PMSAv8_LAR_EN		1
54 #define PMSAv8_LAR_IDX(n)	(((n) & 0x7) << 1)
55 
56 
57 #define PMSAv8_AP_PL1RW_PL0NA	(0 << 1)
58 #define PMSAv8_AP_PL1RW_PL0RW	(1 << 1)
59 #define PMSAv8_AP_PL1RO_PL0RO	(3 << 1)
60 
61 #ifdef CONFIG_SMP
62 #define PMSAv8_RGN_SHARED	(3 << 3) // inner sharable
63 #else
64 #define PMSAv8_RGN_SHARED	(0 << 3)
65 #endif
66 
67 #define PMSAv8_RGN_DEVICE_nGnRnE	0
68 #define PMSAv8_RGN_NORMAL		1
69 
70 #define PMSAv8_MAIR(attr, mt)	((attr) << ((mt) * 8))
71 
72 #ifdef CONFIG_CPU_V7M
73 #define PMSAv8_MINALIGN		32
74 #else
75 #define PMSAv8_MINALIGN		64
76 #endif
77 
78 /* For minimal static MPU region configurations */
79 #define PMSAv7_PROBE_REGION	0
80 #define PMSAv7_BG_REGION	1
81 #define PMSAv7_RAM_REGION	2
82 #define PMSAv7_ROM_REGION	3
83 
84 /* Fixed for PMSAv8 only */
85 #define PMSAv8_XIP_REGION	0
86 #define PMSAv8_KERNEL_REGION	1
87 
88 /* Maximum number of regions Linux is interested in */
89 #define MPU_MAX_REGIONS	16
90 
91 #define PMSAv7_DATA_SIDE	0
92 #define PMSAv7_INSTR_SIDE	1
93 
94 #ifndef __ASSEMBLY__
95 
96 struct mpu_rgn {
97 	/* Assume same attributes for d/i-side  */
98 	union {
99 		u32 drbar;   /* PMSAv7 */
100 		u32 prbar;   /* PMSAv8 */
101 	};
102 	union {
103 		u32 drsr;   /* PMSAv7 */
104 		u32 prlar;  /* PMSAv8 */
105 	};
106 	union {
107 		u32 dracr;  /* PMSAv7 */
108 		u32 unused; /* not used in PMSAv8 */
109 	};
110 };
111 
112 struct mpu_rgn_info {
113 	unsigned int used;
114 	struct mpu_rgn rgns[MPU_MAX_REGIONS];
115 };
116 extern struct mpu_rgn_info mpu_rgn_info;
117 
118 #ifdef CONFIG_ARM_MPU
119 extern void __init pmsav7_adjust_lowmem_bounds(void);
120 extern void __init pmsav8_adjust_lowmem_bounds(void);
121 
122 extern void __init pmsav7_setup(void);
123 extern void __init pmsav8_setup(void);
124 #else
pmsav7_adjust_lowmem_bounds(void)125 static inline void pmsav7_adjust_lowmem_bounds(void) {};
pmsav8_adjust_lowmem_bounds(void)126 static inline void pmsav8_adjust_lowmem_bounds(void) {};
pmsav7_setup(void)127 static inline void pmsav7_setup(void) {};
pmsav8_setup(void)128 static inline void pmsav8_setup(void) {};
129 #endif
130 
131 #endif /* __ASSEMBLY__ */
132 
133 #endif
134