1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 4 * Authors: Gregor Herburger, Matthias Schiffer 5 * 6 * Based on: 7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 8 */ 9/dts-v1/; 10 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include "am335x-tqma335x.dtsi" 14 15/ { 16 model = "TQ-Systems TQMa335x[L] SoM on MBa335x carrier board"; 17 compatible = "tq,tqma3359-mba335x", "tq,tqma3359", "ti,am33xx"; 18 chassis-type = "embedded"; 19 20 chosen { 21 stdout-path = &uart4; 22 }; 23 24 backlight: backlight { 25 compatible = "pwm-backlight"; 26 brightness-levels = <0 58 61 66 75 90 125 170 255>; 27 default-brightness-level = <7>; 28 enable-gpios = <&expander1 4 GPIO_ACTIVE_HIGH>; 29 power-supply = <®_mba335x_12v>; 30 status = "disabled"; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 36 button-s5 { 37 label = "S5"; 38 linux,code = <BTN_0>; 39 gpios = <&expander2 0 GPIO_ACTIVE_LOW>; 40 }; 41 42 button-s6 { 43 label = "S6"; 44 linux,code = <BTN_1>; 45 gpios = <&expander2 1 GPIO_ACTIVE_LOW>; 46 }; 47 48 button-s7 { 49 label = "S7"; 50 linux,code = <BTN_2>; 51 gpios = <&expander2 2 GPIO_ACTIVE_LOW>; 52 }; 53 }; 54 55 reg_mba335x_12v: regulator-12v { 56 compatible = "regulator-fixed"; 57 regulator-name = "MBa335x-V12"; 58 regulator-min-microvolt = <12000000>; 59 regulator-max-microvolt = <12000000>; 60 regulator-always-on; 61 }; 62 63 vcc3v3: regulator-vcc3v3 { 64 compatible = "regulator-fixed"; 65 regulator-name = "VCC3V3"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 regulator-always-on; 69 }; 70 71 sound { 72 compatible = "simple-audio-card"; 73 simple-audio-card,name = "tqm-tlv320aic32"; 74 simple-audio-card,widgets = 75 "Headphone", "Headphone Jack", 76 "Line", "Line In", 77 "Line", "Line Out", 78 "Microphone", "Mic Jack"; 79 simple-audio-card,routing = 80 "Headphone Jack", "HPL", 81 "Headphone Jack", "HPR", 82 "Line Out", "LOL", 83 "Line Out", "LOR", 84 "IN3_L", "Mic Jack", 85 "Mic Jack", "Mic Bias", 86 "Line In", "IN1_L", 87 "Line In", "IN1_R"; 88 simple-audio-card,format = "i2s"; 89 simple-audio-card,bitclock-master = <&sound_master>; 90 simple-audio-card,frame-master = <&sound_master>; 91 92 simple-audio-card,cpu { 93 sound-dai = <&mcasp0>; 94 #sound-dai-cells = <0>; 95 system-clock-direction-out; 96 }; 97 98 sound_master: simple-audio-card,codec { 99 sound-dai = <&tlv320aic32x4>; 100 system-clock-frequency = <24000000>; 101 system-clock-direction-out; 102 }; 103 }; 104}; 105 106&am33xx_pinmux { 107 codec_pins: codec-pins { 108 pinctrl-single,pins = < 109 /* xdma_event_intr0.clkout1 */ 110 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) 111 >; 112 }; 113 114 cpsw_default_pins: cpsw-default-pins { 115 pinctrl-single,pins = < 116 /* Port 1 */ 117 /* mii1_tx_en.rgmii1_tctl */ 118 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 119 /* mii1_rx_dv.rgmii1_rctl */ 120 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) 121 /* mii1_txd3.rgmii1_td3 */ 122 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 123 /* mii1_txd2.rgmii1_td2 */ 124 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 125 /* mii1_txd1.rgmii1_td1 */ 126 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 127 /* mii1_txd0.rgmii1_td0 */ 128 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 129 /* mii1_tx_clk.rgmii1_tclk */ 130 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 131 /* mii1_rx_clk.rgmii1_rclk */ 132 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) 133 /* mii1_rxd3.rgmii1_rd3 */ 134 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) 135 /* mii1_rxd2.rgmii1_rd2 */ 136 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) 137 /* mii1_rxd1.rgmii1_rd1 */ 138 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) 139 /* mii1_rxd0.rgmii1_rd0 */ 140 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) 141 142 /* Port 2 */ 143 /* gpmc_a0.rgmii2_tctl */ 144 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 145 /* gpmc_a1.rgmii2_rctl */ 146 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) 147 /* gpmc_a2.rgmii2_td3 */ 148 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 149 /* gpmc_a3.rgmii2_td2 */ 150 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 151 /* gpmc_a4.rgmii2_td1 */ 152 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 153 /* gpmc_a5.rgmii2_td0 */ 154 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 155 /* gpmc_a6.rgmii2_tclk */ 156 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 157 /* gpmc_a7.rgmii2_rclk */ 158 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) 159 /* gpmc_a8.rgmii2_rd3 */ 160 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) 161 /* gpmc_a9.rgmii2_rd2 */ 162 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) 163 /* gpmc_a10.rgmii2_rd1 */ 164 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) 165 /* gpmc_a11.rgmii2_rd0 */ 166 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) 167 >; 168 }; 169 170 cpsw_sleep_pins: cpsw-sleep-pins { 171 pinctrl-single,pins = < 172 /* Port 1 */ 173 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 174 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 175 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 176 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 177 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 178 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 179 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 180 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 181 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 182 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 183 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 184 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 185 186 /* Port 2 */ 187 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) 188 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) 189 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) 190 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) 191 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) 192 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) 193 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) 194 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) 195 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) 196 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) 197 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) 198 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) 199 >; 200 }; 201 202 davinci_mdio_default_pins: davinci_mdio-default-pins { 203 pinctrl-single,pins = < 204 /* mdio.mdio_data */ 205 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 206 /* mdc.mdio_clk */ 207 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 208 >; 209 }; 210 211 davinci_mdio_sleep_pins: davinci_mdio-sleep-pins { 212 pinctrl-single,pins = < 213 /* mdio.mdio_data */ 214 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP, MUX_MODE7) 215 /* mdc.mdio_clk */ 216 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLUP, MUX_MODE7) 217 >; 218 }; 219 220 davinci_mdio_phy0_pins: davinci_mdio-phy0-pins { 221 pinctrl-single,pins = < 222 /* usb0_drvvbus.gpio0_18 - PHY interrupt */ 223 AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_INPUT, MUX_MODE7) 224 >; 225 }; 226 227 davinci_mdio_phy1_pins: davinci_mdio-phy1-pins { 228 pinctrl-single,pins = < 229 /* gpmc_csn0.gpio1_29 - PHY interrupt */ 230 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) 231 >; 232 }; 233 234 dcan0_pins: dcan0-pins { 235 pinctrl-single,pins = < 236 /* uart1_ctsn.d_can0_tx */ 237 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 238 /* uart1_rtsn.d_can0_rx */ 239 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) 240 >; 241 }; 242 243 dcan1_pins: dcan1-pins { 244 pinctrl-single,pins = < 245 /* uart0_ctsn.d_can1_tx */ 246 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 247 /* uart0_rtsn.d_can1_rx */ 248 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) 249 >; 250 }; 251 252 ecap2_pins: ecap2-pins { 253 pinctrl-single,pins = < 254 /* mcasp0_ahclkr.ecap2_in_pwm2_out */ 255 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE4) 256 >; 257 }; 258 259 expander1_pins: expander1-pins { 260 pinctrl-single,pins = < 261 /* gpmc_csn3.gpio2_0 - interrupt */ 262 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE7 ) 263 >; 264 }; 265 266 expander2_pins: expander2-pins { 267 pinctrl-single,pins = < 268 /* gpmc_ben1.gpio1_28 - interrupt */ 269 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) 270 >; 271 }; 272 273 i2c1_pins: i2c1-pins { 274 pinctrl-single,pins = < 275 /* uart1_rxd.i2c1_sda */ 276 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE3) 277 /* uart1_txd.i2c1_scl */ 278 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE3) 279 >; 280 }; 281 282 lcd_pins: lcd-pins { 283 pinctrl-single,pins = < 284 /* gpmc_ad8.lcd_data23 */ 285 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) 286 /* gpmc_ad9.lcd_data22 */ 287 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) 288 /* gpmc_ad10.lcd_data21 */ 289 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) 290 /* gpmc_ad11.lcd_data20 */ 291 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) 292 /* gpmc_ad12.lcd_data19 */ 293 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) 294 /* gpmc_ad13.lcd_data18 */ 295 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) 296 /* gpmc_ad14.lcd_data17 */ 297 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) 298 /* gpmc_ad15.lcd_data16 */ 299 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) 300 /* lcd_data0.lcd_data0 */ 301 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 302 /* lcd_data1.lcd_data1 */ 303 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 304 /* lcd_data2.lcd_data2 */ 305 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 306 /* lcd_data3.lcd_data3 */ 307 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 308 /* lcd_data4.lcd_data4 */ 309 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 310 /* lcd_data5.lcd_data5 */ 311 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 312 /* lcd_data6.lcd_data6 */ 313 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 314 /* lcd_data7.lcd_data7 */ 315 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 316 /* lcd_data8.lcd_data8 */ 317 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 318 /* lcd_data9.lcd_data9 */ 319 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 320 /* lcd_data10.lcd_data10 */ 321 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 322 /* lcd_data11.lcd_data11 */ 323 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 324 /* lcd_data12.lcd_data12 */ 325 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 326 /* lcd_data13.lcd_data13 */ 327 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 328 /* lcd_data14.lcd_data14 */ 329 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 330 /* lcd_data15.lcd_data15 */ 331 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 332 /* lcd_vsync.lcd_vsync */ 333 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) 334 /* lcd_hsync.lcd_hsync */ 335 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) 336 /* lcd_pclk.lcd_pclk */ 337 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) 338 /* lcd_ac_bias_en.lcd_ac_bias_en */ 339 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) 340 >; 341 }; 342 343 mcasp0_pins: mcasp0-pins { 344 pinctrl-single,pins = < 345 /* mcasp0_fsx.mcasp0_fsx */ 346 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) 347 /* mcasp0_aclkx.mcasp0_aclkx*/ 348 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) 349 /* mcasp0_axr0.mcasp0_axr0 */ 350 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) 351 /* mcasp0_axr1.mcasp0_axr1 */ 352 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) 353 /* mcasp0_aclkr.mcasp0_aclkr */ 354 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE0) 355 /* mcasp0_fsr.mcasp0_fsr */ 356 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT_PULLDOWN, MUX_MODE0) 357 >; 358 }; 359 360 mmc1_pins: mmc1-pins { 361 pinctrl-single,pins = < 362 /* mmc0_dat3.mmc0_dat3 */ 363 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 364 /* mmc0_dat2.mmc0_dat2 */ 365 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 366 /* mmc0_dat1.mmc0_dat1 */ 367 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 368 /* mmc0_dat0.mmc0_dat0 */ 369 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 370 /* mmc0_clk.mmc0_clk */ 371 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 372 /* mmc0_cmd.mmc0_cmd */ 373 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 374 >; 375 }; 376 377 polytouch_pins: polytouch-pins { 378 pinctrl-single,pins = < 379 /* gpmc_clk.gpio2_1 - touch interrupt */ 380 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) 381 >; 382 }; 383 384 uart0_pins: uart0-pins { 385 pinctrl-single,pins = < 386 /* uart0_rxd.uart0_rxd */ 387 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 388 /* uart0_txd.uart0_txd */ 389 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 390 >; 391 }; 392 393 uart3_pins: uart3-pins { 394 pinctrl-single,pins = < 395 /* spi0_cs1.uart3_rxd */ 396 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) 397 /* ecap0_in_pwm0_out.uart3_txd */ 398 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) 399 >; 400 }; 401 402 uart4_pins: uart4-pins { 403 pinctrl-single,pins = < 404 /* gpmc_wait0.uart4_rxd */ 405 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) 406 /* gpmc_wpn.uart4_txd */ 407 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) 408 >; 409 }; 410}; 411 412&cpsw_port1 { 413 phy-handle = <ðphy0>; 414 phy-mode = "rgmii-id"; 415 ti,dual-emac-pvid = <1>; 416}; 417 418&cpsw_port2 { 419 phy-handle = <ðphy1>; 420 phy-mode = "rgmii-id"; 421 ti,dual-emac-pvid = <2>; 422}; 423 424&davinci_mdio_sw { 425 pinctrl-names = "default", "sleep"; 426 pinctrl-0 = <&davinci_mdio_default_pins>; 427 pinctrl-1 = <&davinci_mdio_sleep_pins>; 428 status = "okay"; 429 430 ethphy0: ethernet-phy@0 { 431 compatible = "ethernet-phy-ieee802.3-c22"; 432 reg = <0>; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&davinci_mdio_phy0_pins>; 435 interrupt-parent = <&gpio0>; 436 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 437 rxc-skew-ps = <1860>; 438 rxd0-skew-ps = <0>; 439 rxd1-skew-ps = <0>; 440 rxd2-skew-ps = <0>; 441 rxd3-skew-ps = <0>; 442 rxdv-skew-ps = <0>; 443 txc-skew-ps = <1860>; 444 txd0-skew-ps = <0>; 445 txd1-skew-ps = <0>; 446 txd2-skew-ps = <0>; 447 txd3-skew-ps = <0>; 448 txen-skew-ps = <0>; 449 }; 450 451 ethphy1: ethernet-phy@1 { 452 compatible = "ethernet-phy-ieee802.3-c22"; 453 reg = <1>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&davinci_mdio_phy1_pins>; 456 interrupt-parent = <&gpio1>; 457 interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 458 rxc-skew-ps = <1860>; 459 rxd0-skew-ps = <0>; 460 rxd1-skew-ps = <0>; 461 rxd2-skew-ps = <0>; 462 rxd3-skew-ps = <0>; 463 rxdv-skew-ps = <0>; 464 txc-skew-ps = <1860>; 465 txd0-skew-ps = <0>; 466 txd1-skew-ps = <0>; 467 txd2-skew-ps = <0>; 468 txd3-skew-ps = <0>; 469 txen-skew-ps = <0>; 470 }; 471}; 472 473&dcan0 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&dcan0_pins>; 476 status = "okay"; 477}; 478 479&dcan1 { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&dcan1_pins>; 482 status = "okay"; 483}; 484 485&ds1339 { 486 interrupt-parent = <&expander2>; 487 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 488}; 489 490&ecap2 { 491 pinctrl-names = "default"; 492 pinctrl-0 = <&ecap2_pins>; 493}; 494 495&i2c0 { 496 tlv320aic32x4: audio-codec@18 { 497 compatible = "ti,tlv320aic32x4"; 498 reg = <0x18>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&codec_pins>; 501 clocks = <&clk_24mhz>; 502 clock-names = "mclk"; 503 iov-supply = <&vcc3v3>; 504 ldoin-supply = <&vcc3v3>; 505 #sound-dai-cells = <0>; 506 }; 507 508 jc42_2: temperature-sensor@19 { 509 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 510 reg = <0x19>; 511 }; 512 513 expander1: gpio@20 { 514 compatible = "nxp,pca9554"; 515 reg = <0x20>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&expander1_pins>; 518 vcc-supply = <&vcc3v3>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 interrupt-parent = <&gpio2>; 524 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 525 }; 526 527 expander2: gpio@21 { 528 compatible = "nxp,pca9554"; 529 reg = <0x21>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&expander2_pins>; 532 vcc-supply = <&vcc3v3>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 interrupt-parent = <&gpio1>; 538 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 539 }; 540 541 eeprom3: eeprom@51 { 542 compatible = "nxp,se97b", "atmel,24c02"; 543 reg = <0x51>; 544 pagesize = <16>; 545 vcc-supply = <&vcc3v3>; 546 }; 547}; 548 549&i2c1 { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&i2c1_pins>; 552 clock-frequency = <100000>; 553 status = "okay"; 554}; 555 556&lcdc { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&lcd_pins>; 559 blue-and-red-wiring = "crossed"; 560}; 561 562&mac_sw { 563 pinctrl-names = "default", "sleep"; 564 pinctrl-0 = <&cpsw_default_pins>; 565 pinctrl-1 = <&cpsw_sleep_pins>; 566 status = "okay"; 567}; 568 569&mcasp0 { 570 pinctrl-names = "default"; 571 pinctrl-0 = <&mcasp0_pins>; 572 #sound-dai-cells = <0>; 573 op-mode = <0>; 574 tdm-slots = <2>; 575 /* 16 serializer */ 576 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 577 2 1 0 0 578 0 0 0 0 579 0 0 0 0 580 0 0 0 0 581 >; 582 tx-num-evt = <32>; 583 rx-num-evt = <32>; 584 status = "okay"; 585}; 586 587&mmc1 { 588 pinctrl-names = "default"; 589 pinctrl-0 = <&mmc1_pins>; 590 vmmc-supply = <&vcc3v3>; 591 bus-width = <4>; 592 no-1-8-v; 593 no-mmc; 594 no-sdio; 595 status = "okay"; 596}; 597 598&tps { 599 interrupt-parent = <&expander2>; 600 interrupts = <4 IRQ_TYPE_EDGE_RISING>; 601}; 602 603&uart0 { 604 pinctrl-names = "default"; 605 pinctrl-0 = <&uart0_pins>; 606 status = "okay"; 607}; 608 609&uart3 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&uart3_pins>; 612 status = "okay"; 613}; 614 615&uart4 { 616 pinctrl-names = "default"; 617 pinctrl-0 = <&uart4_pins>; 618 status = "okay"; 619}; 620 621&usb0 { 622 dr_mode = "host"; 623}; 624 625&usb1 { 626 /* Should be "otg", but role switching currently doesn't work */ 627 dr_mode = "peripheral"; 628}; 629 630/* SOM supply */ 631&vcc3v3in { 632 vin-supply = <&vcc3v3>; 633}; 634