1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_DEVMEM_IS_ALLOWED 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_HAVE_CUSTOM_GPIO_H 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_MIGHT_HAVE_PC_PARPORT 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_USE_BUILTIN_BSWAP 13 select ARCH_USE_CMPXCHG_LOCKREF 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_EXTABLE_SORT if MMU 16 select CLONE_BACKWARDS 17 select CPU_PM if (SUSPEND || CPU_IDLE) 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 19 select EDAC_SUPPORT 20 select EDAC_ATOMIC_SCRUB 21 select GENERIC_ALLOCATOR 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_EARLY_IOREMAP 25 select GENERIC_IDLE_POLL_SETUP 26 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW_LEVEL 29 select GENERIC_PCI_IOMAP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select HANDLE_DOMAIN_IRQ 35 select HARDIRQS_SW_RESEND 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 40 select HAVE_ARCH_MMAP_RND_BITS if MMU 41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 42 select HAVE_ARCH_TRACEHOOK 43 select HAVE_ARM_SMCCC if CPU_V7 44 select HAVE_BPF_JIT 45 select HAVE_CC_STACKPROTECTOR 46 select HAVE_CONTEXT_TRACKING 47 select HAVE_C_RECORDMCOUNT 48 select HAVE_DEBUG_KMEMLEAK 49 select HAVE_DMA_API_DEBUG 50 select HAVE_DMA_CONTIGUOUS if MMU 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 56 select HAVE_GENERIC_DMA_COHERENT 57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 58 select HAVE_IDE if PCI || ISA || PCMCIA 59 select HAVE_IRQ_TIME_ACCOUNTING 60 select HAVE_KERNEL_GZIP 61 select HAVE_KERNEL_LZ4 62 select HAVE_KERNEL_LZMA 63 select HAVE_KERNEL_LZO 64 select HAVE_KERNEL_XZ 65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 66 select HAVE_KRETPROBES if (HAVE_KPROBES) 67 select HAVE_MEMBLOCK 68 select HAVE_MOD_ARCH_SPECIFIC 69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 70 select HAVE_OPTPROBES if !THUMB2_KERNEL 71 select HAVE_PERF_EVENTS 72 select HAVE_PERF_REGS 73 select HAVE_PERF_USER_STACK_DUMP 74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 75 select HAVE_REGS_AND_STACK_ACCESS_API 76 select HAVE_SYSCALL_TRACEPOINTS 77 select HAVE_UID16 78 select HAVE_VIRT_CPU_ACCOUNTING_GEN 79 select IRQ_FORCED_THREADING 80 select MODULES_USE_ELF_REL 81 select NO_BOOTMEM 82 select OF_EARLY_FLATTREE if OF 83 select OF_RESERVED_MEM if OF 84 select OLD_SIGACTION 85 select OLD_SIGSUSPEND3 86 select PERF_USE_VMALLOC 87 select RTC_LIB 88 select SYS_SUPPORTS_APM_EMULATION 89 # Above selects are sorted alphabetically; please add new ones 90 # according to that. Thanks. 91 help 92 The ARM series is a line of low-power-consumption RISC chip designs 93 licensed by ARM Ltd and targeted at embedded applications and 94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 95 manufactured, but legacy ARM-based PC hardware remains popular in 96 Europe. There is an ARM Linux project with a web page at 97 <http://www.arm.linux.org.uk/>. 98 99config ARM_HAS_SG_CHAIN 100 select ARCH_HAS_SG_CHAIN 101 bool 102 103config NEED_SG_DMA_LENGTH 104 bool 105 106config ARM_DMA_USE_IOMMU 107 bool 108 select ARM_HAS_SG_CHAIN 109 select NEED_SG_DMA_LENGTH 110 111if ARM_DMA_USE_IOMMU 112 113config ARM_DMA_IOMMU_ALIGNMENT 114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 115 range 4 9 116 default 8 117 help 118 DMA mapping framework by default aligns all buffers to the smallest 119 PAGE_SIZE order which is greater than or equal to the requested buffer 120 size. This works well for buffers up to a few hundreds kilobytes, but 121 for larger buffers it just a waste of address space. Drivers which has 122 relatively small addressing window (like 64Mib) might run out of 123 virtual space with just a few allocations. 124 125 With this parameter you can specify the maximum PAGE_SIZE order for 126 DMA IOMMU buffers. Larger buffers will be aligned only to this 127 specified order. The order is expressed as a power of two multiplied 128 by the PAGE_SIZE. 129 130endif 131 132config MIGHT_HAVE_PCI 133 bool 134 135config SYS_SUPPORTS_APM_EMULATION 136 bool 137 138config HAVE_TCM 139 bool 140 select GENERIC_ALLOCATOR 141 142config HAVE_PROC_CPU 143 bool 144 145config NO_IOPORT_MAP 146 bool 147 148config EISA 149 bool 150 ---help--- 151 The Extended Industry Standard Architecture (EISA) bus was 152 developed as an open alternative to the IBM MicroChannel bus. 153 154 The EISA bus provided some of the features of the IBM MicroChannel 155 bus while maintaining backward compatibility with cards made for 156 the older ISA bus. The EISA bus saw limited use between 1988 and 157 1995 when it was made obsolete by the PCI bus. 158 159 Say Y here if you are building a kernel for an EISA-based machine. 160 161 Otherwise, say N. 162 163config SBUS 164 bool 165 166config STACKTRACE_SUPPORT 167 bool 168 default y 169 170config LOCKDEP_SUPPORT 171 bool 172 default y 173 174config TRACE_IRQFLAGS_SUPPORT 175 bool 176 default !CPU_V7M 177 178config RWSEM_XCHGADD_ALGORITHM 179 bool 180 default y 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config NEED_DMA_MAP_STATE 209 def_bool y 210 211config ARCH_SUPPORTS_UPROBES 212 def_bool y 213 214config ARCH_HAS_DMA_SET_COHERENT_MASK 215 bool 216 217config GENERIC_ISA_DMA 218 bool 219 220config FIQ 221 bool 222 223config NEED_RET_TO_USER 224 bool 225 226config ARCH_MTD_XIP 227 bool 228 229config VECTORS_BASE 230 hex 231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 232 default DRAM_BASE if REMAP_VECTORS_TO_RAM 233 default 0x00000000 234 help 235 The base address of exception vectors. This must be two pages 236 in size. 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 help 243 Patch phys-to-virt and virt-to-phys translation functions at 244 boot and module load time according to the position of the 245 kernel in system memory. 246 247 This can only be used with non-XIP MMU kernels where the base 248 of physical memory is at a 16MB boundary. 249 250 Only disable this option if you know that you do not require 251 this feature (eg, building a kernel for a single machine) and 252 you need to shrink the kernel to the minimal size. 253 254config NEED_MACH_IO_H 255 bool 256 help 257 Select this when mach/io.h is required to provide special 258 definitions for this platform. The need for mach/io.h should 259 be avoided when possible. 260 261config NEED_MACH_MEMORY_H 262 bool 263 help 264 Select this when mach/memory.h is required to provide special 265 definitions for this platform. The need for mach/memory.h should 266 be avoided when possible. 267 268config PHYS_OFFSET 269 hex "Physical address of main memory" if MMU 270 depends on !ARM_PATCH_PHYS_VIRT 271 default DRAM_BASE if !MMU 272 default 0x00000000 if ARCH_EBSA110 || \ 273 ARCH_FOOTBRIDGE || \ 274 ARCH_INTEGRATOR || \ 275 ARCH_IOP13XX || \ 276 ARCH_KS8695 || \ 277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 279 default 0x20000000 if ARCH_S5PV210 280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 281 default 0xc0000000 if ARCH_SA1100 282 help 283 Please provide the physical address corresponding to the 284 location of main memory in your system. 285 286config GENERIC_BUG 287 def_bool y 288 depends on BUG 289 290config PGTABLE_LEVELS 291 int 292 default 3 if ARM_LPAE 293 default 2 294 295source "init/Kconfig" 296 297source "kernel/Kconfig.freezer" 298 299menu "System Type" 300 301config MMU 302 bool "MMU-based Paged Memory Management Support" 303 default y 304 help 305 Select if you want MMU-based virtualised addressing space 306 support by paged memory management. If unsure, say 'Y'. 307 308config ARCH_MMAP_RND_BITS_MIN 309 default 8 310 311config ARCH_MMAP_RND_BITS_MAX 312 default 14 if PAGE_OFFSET=0x40000000 313 default 15 if PAGE_OFFSET=0x80000000 314 default 16 315 316# 317# The "ARM system type" choice list is ordered alphabetically by option 318# text. Please add new entries in the option alphabetic order. 319# 320choice 321 prompt "ARM system type" 322 default ARM_SINGLE_ARMV7M if !MMU 323 default ARCH_MULTIPLATFORM if MMU 324 325config ARCH_MULTIPLATFORM 326 bool "Allow multiple platforms to be selected" 327 depends on MMU 328 select ARCH_WANT_OPTIONAL_GPIOLIB 329 select ARM_HAS_SG_CHAIN 330 select ARM_PATCH_PHYS_VIRT 331 select AUTO_ZRELADDR 332 select CLKSRC_OF 333 select COMMON_CLK 334 select GENERIC_CLOCKEVENTS 335 select MIGHT_HAVE_PCI 336 select MULTI_IRQ_HANDLER 337 select SPARSE_IRQ 338 select USE_OF 339 340config ARM_SINGLE_ARMV7M 341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 342 depends on !MMU 343 select ARCH_WANT_OPTIONAL_GPIOLIB 344 select ARM_NVIC 345 select AUTO_ZRELADDR 346 select CLKSRC_OF 347 select COMMON_CLK 348 select CPU_V7M 349 select GENERIC_CLOCKEVENTS 350 select NO_IOPORT_MAP 351 select SPARSE_IRQ 352 select USE_OF 353 354 355config ARCH_CLPS711X 356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 357 select ARCH_REQUIRE_GPIOLIB 358 select AUTO_ZRELADDR 359 select CLKSRC_MMIO 360 select COMMON_CLK 361 select CPU_ARM720T 362 select GENERIC_CLOCKEVENTS 363 select MFD_SYSCON 364 select SOC_BUS 365 help 366 Support for Cirrus Logic 711x/721x/731x based boards. 367 368config ARCH_GEMINI 369 bool "Cortina Systems Gemini" 370 select ARCH_REQUIRE_GPIOLIB 371 select CLKSRC_MMIO 372 select CPU_FA526 373 select GENERIC_CLOCKEVENTS 374 help 375 Support for the Cortina Systems Gemini family SoCs 376 377config ARCH_EBSA110 378 bool "EBSA-110" 379 select ARCH_USES_GETTIMEOFFSET 380 select CPU_SA110 381 select ISA 382 select NEED_MACH_IO_H 383 select NEED_MACH_MEMORY_H 384 select NO_IOPORT_MAP 385 help 386 This is an evaluation board for the StrongARM processor available 387 from Digital. It has limited hardware on-board, including an 388 Ethernet interface, two PCMCIA sockets, two serial ports and a 389 parallel port. 390 391config ARCH_EP93XX 392 bool "EP93xx-based" 393 select ARCH_HAS_HOLES_MEMORYMODEL 394 select ARCH_REQUIRE_GPIOLIB 395 select ARM_AMBA 396 select ARM_PATCH_PHYS_VIRT 397 select ARM_VIC 398 select AUTO_ZRELADDR 399 select CLKDEV_LOOKUP 400 select CLKSRC_MMIO 401 select CPU_ARM920T 402 select GENERIC_CLOCKEVENTS 403 help 404 This enables support for the Cirrus EP93xx series of CPUs. 405 406config ARCH_FOOTBRIDGE 407 bool "FootBridge" 408 select CPU_SA110 409 select FOOTBRIDGE 410 select GENERIC_CLOCKEVENTS 411 select HAVE_IDE 412 select NEED_MACH_IO_H if !MMU 413 select NEED_MACH_MEMORY_H 414 help 415 Support for systems based on the DC21285 companion chip 416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 417 418config ARCH_NETX 419 bool "Hilscher NetX based" 420 select ARM_VIC 421 select CLKSRC_MMIO 422 select CPU_ARM926T 423 select GENERIC_CLOCKEVENTS 424 help 425 This enables support for systems based on the Hilscher NetX Soc 426 427config ARCH_IOP13XX 428 bool "IOP13xx-based" 429 depends on MMU 430 select CPU_XSC3 431 select NEED_MACH_MEMORY_H 432 select NEED_RET_TO_USER 433 select PCI 434 select PLAT_IOP 435 select VMSPLIT_1G 436 select SPARSE_IRQ 437 help 438 Support for Intel's IOP13XX (XScale) family of processors. 439 440config ARCH_IOP32X 441 bool "IOP32x-based" 442 depends on MMU 443 select ARCH_REQUIRE_GPIOLIB 444 select CPU_XSCALE 445 select GPIO_IOP 446 select NEED_RET_TO_USER 447 select PCI 448 select PLAT_IOP 449 help 450 Support for Intel's 80219 and IOP32X (XScale) family of 451 processors. 452 453config ARCH_IOP33X 454 bool "IOP33x-based" 455 depends on MMU 456 select ARCH_REQUIRE_GPIOLIB 457 select CPU_XSCALE 458 select GPIO_IOP 459 select NEED_RET_TO_USER 460 select PCI 461 select PLAT_IOP 462 help 463 Support for Intel's IOP33X (XScale) family of processors. 464 465config ARCH_IXP4XX 466 bool "IXP4xx-based" 467 depends on MMU 468 select ARCH_HAS_DMA_SET_COHERENT_MASK 469 select ARCH_REQUIRE_GPIOLIB 470 select ARCH_SUPPORTS_BIG_ENDIAN 471 select CLKSRC_MMIO 472 select CPU_XSCALE 473 select DMABOUNCE if PCI 474 select GENERIC_CLOCKEVENTS 475 select MIGHT_HAVE_PCI 476 select NEED_MACH_IO_H 477 select USB_EHCI_BIG_ENDIAN_DESC 478 select USB_EHCI_BIG_ENDIAN_MMIO 479 help 480 Support for Intel's IXP4XX (XScale) family of processors. 481 482config ARCH_DOVE 483 bool "Marvell Dove" 484 select ARCH_REQUIRE_GPIOLIB 485 select CPU_PJ4 486 select GENERIC_CLOCKEVENTS 487 select MIGHT_HAVE_PCI 488 select MULTI_IRQ_HANDLER 489 select MVEBU_MBUS 490 select PINCTRL 491 select PINCTRL_DOVE 492 select PLAT_ORION_LEGACY 493 select SPARSE_IRQ 494 select PM_GENERIC_DOMAINS if PM 495 help 496 Support for the Marvell Dove SoC 88AP510 497 498config ARCH_KS8695 499 bool "Micrel/Kendin KS8695" 500 select ARCH_REQUIRE_GPIOLIB 501 select CLKSRC_MMIO 502 select CPU_ARM922T 503 select GENERIC_CLOCKEVENTS 504 select NEED_MACH_MEMORY_H 505 help 506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 507 System-on-Chip devices. 508 509config ARCH_W90X900 510 bool "Nuvoton W90X900 CPU" 511 select ARCH_REQUIRE_GPIOLIB 512 select CLKDEV_LOOKUP 513 select CLKSRC_MMIO 514 select CPU_ARM926T 515 select GENERIC_CLOCKEVENTS 516 help 517 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 518 At present, the w90x900 has been renamed nuc900, regarding 519 the ARM series product line, you can login the following 520 link address to know more. 521 522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 524 525config ARCH_LPC32XX 526 bool "NXP LPC32XX" 527 select ARCH_REQUIRE_GPIOLIB 528 select ARM_AMBA 529 select CLKDEV_LOOKUP 530 select CLKSRC_MMIO 531 select CPU_ARM926T 532 select GENERIC_CLOCKEVENTS 533 select HAVE_IDE 534 select USE_OF 535 help 536 Support for the NXP LPC32XX family of processors 537 538config ARCH_PXA 539 bool "PXA2xx/PXA3xx-based" 540 depends on MMU 541 select ARCH_MTD_XIP 542 select ARCH_REQUIRE_GPIOLIB 543 select ARM_CPU_SUSPEND if PM 544 select AUTO_ZRELADDR 545 select COMMON_CLK 546 select CLKDEV_LOOKUP 547 select CLKSRC_PXA 548 select CLKSRC_MMIO 549 select CLKSRC_OF 550 select GENERIC_CLOCKEVENTS 551 select GPIO_PXA 552 select HAVE_IDE 553 select IRQ_DOMAIN 554 select MULTI_IRQ_HANDLER 555 select PLAT_PXA 556 select SPARSE_IRQ 557 help 558 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 559 560config ARCH_RPC 561 bool "RiscPC" 562 depends on MMU 563 select ARCH_ACORN 564 select ARCH_MAY_HAVE_PC_FDC 565 select ARCH_SPARSEMEM_ENABLE 566 select ARCH_USES_GETTIMEOFFSET 567 select CPU_SA110 568 select FIQ 569 select HAVE_IDE 570 select HAVE_PATA_PLATFORM 571 select ISA_DMA_API 572 select NEED_MACH_IO_H 573 select NEED_MACH_MEMORY_H 574 select NO_IOPORT_MAP 575 select VIRT_TO_BUS 576 help 577 On the Acorn Risc-PC, Linux can support the internal IDE disk and 578 CD-ROM interface, serial and parallel port, and the floppy drive. 579 580config ARCH_SA1100 581 bool "SA1100-based" 582 select ARCH_MTD_XIP 583 select ARCH_REQUIRE_GPIOLIB 584 select ARCH_SPARSEMEM_ENABLE 585 select CLKDEV_LOOKUP 586 select CLKSRC_MMIO 587 select CLKSRC_PXA 588 select CLKSRC_OF if OF 589 select CPU_FREQ 590 select CPU_SA1100 591 select GENERIC_CLOCKEVENTS 592 select HAVE_IDE 593 select IRQ_DOMAIN 594 select ISA 595 select MULTI_IRQ_HANDLER 596 select NEED_MACH_MEMORY_H 597 select SPARSE_IRQ 598 help 599 Support for StrongARM 11x0 based boards. 600 601config ARCH_S3C24XX 602 bool "Samsung S3C24XX SoCs" 603 select ARCH_REQUIRE_GPIOLIB 604 select ATAGS 605 select CLKDEV_LOOKUP 606 select CLKSRC_SAMSUNG_PWM 607 select GENERIC_CLOCKEVENTS 608 select GPIO_SAMSUNG 609 select HAVE_S3C2410_I2C if I2C 610 select HAVE_S3C2410_WATCHDOG if WATCHDOG 611 select HAVE_S3C_RTC if RTC_CLASS 612 select MULTI_IRQ_HANDLER 613 select NEED_MACH_IO_H 614 select SAMSUNG_ATAGS 615 help 616 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 617 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 618 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 619 Samsung SMDK2410 development board (and derivatives). 620 621config ARCH_DAVINCI 622 bool "TI DaVinci" 623 select ARCH_HAS_HOLES_MEMORYMODEL 624 select ARCH_REQUIRE_GPIOLIB 625 select CLKDEV_LOOKUP 626 select GENERIC_ALLOCATOR 627 select GENERIC_CLOCKEVENTS 628 select GENERIC_IRQ_CHIP 629 select HAVE_IDE 630 select USE_OF 631 select ZONE_DMA 632 help 633 Support for TI's DaVinci platform. 634 635config ARCH_OMAP1 636 bool "TI OMAP1" 637 depends on MMU 638 select ARCH_HAS_HOLES_MEMORYMODEL 639 select ARCH_OMAP 640 select ARCH_REQUIRE_GPIOLIB 641 select CLKDEV_LOOKUP 642 select CLKSRC_MMIO 643 select GENERIC_CLOCKEVENTS 644 select GENERIC_IRQ_CHIP 645 select HAVE_IDE 646 select IRQ_DOMAIN 647 select MULTI_IRQ_HANDLER 648 select NEED_MACH_IO_H if PCCARD 649 select NEED_MACH_MEMORY_H 650 select SPARSE_IRQ 651 help 652 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 653 654endchoice 655 656menu "Multiple platform selection" 657 depends on ARCH_MULTIPLATFORM 658 659comment "CPU Core family selection" 660 661config ARCH_MULTI_V4 662 bool "ARMv4 based platforms (FA526)" 663 depends on !ARCH_MULTI_V6_V7 664 select ARCH_MULTI_V4_V5 665 select CPU_FA526 666 667config ARCH_MULTI_V4T 668 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 669 depends on !ARCH_MULTI_V6_V7 670 select ARCH_MULTI_V4_V5 671 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 672 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 673 CPU_ARM925T || CPU_ARM940T) 674 675config ARCH_MULTI_V5 676 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 677 depends on !ARCH_MULTI_V6_V7 678 select ARCH_MULTI_V4_V5 679 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 680 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 681 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 682 683config ARCH_MULTI_V4_V5 684 bool 685 686config ARCH_MULTI_V6 687 bool "ARMv6 based platforms (ARM11)" 688 select ARCH_MULTI_V6_V7 689 select CPU_V6K 690 691config ARCH_MULTI_V7 692 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 693 default y 694 select ARCH_MULTI_V6_V7 695 select CPU_V7 696 select HAVE_SMP 697 698config ARCH_MULTI_V6_V7 699 bool 700 select MIGHT_HAVE_CACHE_L2X0 701 702config ARCH_MULTI_CPU_AUTO 703 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 704 select ARCH_MULTI_V5 705 706endmenu 707 708config ARCH_VIRT 709 bool "Dummy Virtual Machine" 710 depends on ARCH_MULTI_V7 711 select ARM_AMBA 712 select ARM_GIC 713 select ARM_GIC_V2M if PCI_MSI 714 select ARM_GIC_V3 715 select ARM_PSCI 716 select HAVE_ARM_ARCH_TIMER 717 718# 719# This is sorted alphabetically by mach-* pathname. However, plat-* 720# Kconfigs may be included either alphabetically (according to the 721# plat- suffix) or along side the corresponding mach-* source. 722# 723source "arch/arm/mach-mvebu/Kconfig" 724 725source "arch/arm/mach-alpine/Kconfig" 726 727source "arch/arm/mach-asm9260/Kconfig" 728 729source "arch/arm/mach-at91/Kconfig" 730 731source "arch/arm/mach-axxia/Kconfig" 732 733source "arch/arm/mach-bcm/Kconfig" 734 735source "arch/arm/mach-berlin/Kconfig" 736 737source "arch/arm/mach-clps711x/Kconfig" 738 739source "arch/arm/mach-cns3xxx/Kconfig" 740 741source "arch/arm/mach-davinci/Kconfig" 742 743source "arch/arm/mach-digicolor/Kconfig" 744 745source "arch/arm/mach-dove/Kconfig" 746 747source "arch/arm/mach-ep93xx/Kconfig" 748 749source "arch/arm/mach-footbridge/Kconfig" 750 751source "arch/arm/mach-gemini/Kconfig" 752 753source "arch/arm/mach-highbank/Kconfig" 754 755source "arch/arm/mach-hisi/Kconfig" 756 757source "arch/arm/mach-integrator/Kconfig" 758 759source "arch/arm/mach-iop32x/Kconfig" 760 761source "arch/arm/mach-iop33x/Kconfig" 762 763source "arch/arm/mach-iop13xx/Kconfig" 764 765source "arch/arm/mach-ixp4xx/Kconfig" 766 767source "arch/arm/mach-keystone/Kconfig" 768 769source "arch/arm/mach-ks8695/Kconfig" 770 771source "arch/arm/mach-meson/Kconfig" 772 773source "arch/arm/mach-moxart/Kconfig" 774 775source "arch/arm/mach-mv78xx0/Kconfig" 776 777source "arch/arm/mach-imx/Kconfig" 778 779source "arch/arm/mach-mediatek/Kconfig" 780 781source "arch/arm/mach-mxs/Kconfig" 782 783source "arch/arm/mach-netx/Kconfig" 784 785source "arch/arm/mach-nomadik/Kconfig" 786 787source "arch/arm/mach-nspire/Kconfig" 788 789source "arch/arm/plat-omap/Kconfig" 790 791source "arch/arm/mach-omap1/Kconfig" 792 793source "arch/arm/mach-omap2/Kconfig" 794 795source "arch/arm/mach-orion5x/Kconfig" 796 797source "arch/arm/mach-picoxcell/Kconfig" 798 799source "arch/arm/mach-pxa/Kconfig" 800source "arch/arm/plat-pxa/Kconfig" 801 802source "arch/arm/mach-mmp/Kconfig" 803 804source "arch/arm/mach-qcom/Kconfig" 805 806source "arch/arm/mach-realview/Kconfig" 807 808source "arch/arm/mach-rockchip/Kconfig" 809 810source "arch/arm/mach-sa1100/Kconfig" 811 812source "arch/arm/mach-socfpga/Kconfig" 813 814source "arch/arm/mach-spear/Kconfig" 815 816source "arch/arm/mach-sti/Kconfig" 817 818source "arch/arm/mach-s3c24xx/Kconfig" 819 820source "arch/arm/mach-s3c64xx/Kconfig" 821 822source "arch/arm/mach-s5pv210/Kconfig" 823 824source "arch/arm/mach-exynos/Kconfig" 825source "arch/arm/plat-samsung/Kconfig" 826 827source "arch/arm/mach-shmobile/Kconfig" 828 829source "arch/arm/mach-sunxi/Kconfig" 830 831source "arch/arm/mach-prima2/Kconfig" 832 833source "arch/arm/mach-tango/Kconfig" 834 835source "arch/arm/mach-tegra/Kconfig" 836 837source "arch/arm/mach-u300/Kconfig" 838 839source "arch/arm/mach-uniphier/Kconfig" 840 841source "arch/arm/mach-ux500/Kconfig" 842 843source "arch/arm/mach-versatile/Kconfig" 844 845source "arch/arm/mach-vexpress/Kconfig" 846source "arch/arm/plat-versatile/Kconfig" 847 848source "arch/arm/mach-vt8500/Kconfig" 849 850source "arch/arm/mach-w90x900/Kconfig" 851 852source "arch/arm/mach-zx/Kconfig" 853 854source "arch/arm/mach-zynq/Kconfig" 855 856# ARMv7-M architecture 857config ARCH_EFM32 858 bool "Energy Micro efm32" 859 depends on ARM_SINGLE_ARMV7M 860 select ARCH_REQUIRE_GPIOLIB 861 help 862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 863 processors. 864 865config ARCH_LPC18XX 866 bool "NXP LPC18xx/LPC43xx" 867 depends on ARM_SINGLE_ARMV7M 868 select ARCH_HAS_RESET_CONTROLLER 869 select ARM_AMBA 870 select CLKSRC_LPC32XX 871 select PINCTRL 872 help 873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 874 high performance microcontrollers. 875 876config ARCH_STM32 877 bool "STMicrolectronics STM32" 878 depends on ARM_SINGLE_ARMV7M 879 select ARCH_HAS_RESET_CONTROLLER 880 select ARMV7M_SYSTICK 881 select CLKSRC_STM32 882 select RESET_CONTROLLER 883 help 884 Support for STMicroelectronics STM32 processors. 885 886# Definitions to make life easier 887config ARCH_ACORN 888 bool 889 890config PLAT_IOP 891 bool 892 select GENERIC_CLOCKEVENTS 893 894config PLAT_ORION 895 bool 896 select CLKSRC_MMIO 897 select COMMON_CLK 898 select GENERIC_IRQ_CHIP 899 select IRQ_DOMAIN 900 901config PLAT_ORION_LEGACY 902 bool 903 select PLAT_ORION 904 905config PLAT_PXA 906 bool 907 908config PLAT_VERSATILE 909 bool 910 911source "arch/arm/firmware/Kconfig" 912 913source arch/arm/mm/Kconfig 914 915config IWMMXT 916 bool "Enable iWMMXt support" 917 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 918 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 919 help 920 Enable support for iWMMXt context switching at run time if 921 running on a CPU that supports it. 922 923config MULTI_IRQ_HANDLER 924 bool 925 help 926 Allow each machine to specify it's own IRQ handler at run time. 927 928if !MMU 929source "arch/arm/Kconfig-nommu" 930endif 931 932config PJ4B_ERRATA_4742 933 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 934 depends on CPU_PJ4B && MACH_ARMADA_370 935 default y 936 help 937 When coming out of either a Wait for Interrupt (WFI) or a Wait for 938 Event (WFE) IDLE states, a specific timing sensitivity exists between 939 the retiring WFI/WFE instructions and the newly issued subsequent 940 instructions. This sensitivity can result in a CPU hang scenario. 941 Workaround: 942 The software must insert either a Data Synchronization Barrier (DSB) 943 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 944 instruction 945 946config ARM_ERRATA_326103 947 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 948 depends on CPU_V6 949 help 950 Executing a SWP instruction to read-only memory does not set bit 11 951 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 952 treat the access as a read, preventing a COW from occurring and 953 causing the faulting task to livelock. 954 955config ARM_ERRATA_411920 956 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 957 depends on CPU_V6 || CPU_V6K 958 help 959 Invalidation of the Instruction Cache operation can 960 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 961 It does not affect the MPCore. This option enables the ARM Ltd. 962 recommended workaround. 963 964config ARM_ERRATA_430973 965 bool "ARM errata: Stale prediction on replaced interworking branch" 966 depends on CPU_V7 967 help 968 This option enables the workaround for the 430973 Cortex-A8 969 r1p* erratum. If a code sequence containing an ARM/Thumb 970 interworking branch is replaced with another code sequence at the 971 same virtual address, whether due to self-modifying code or virtual 972 to physical address re-mapping, Cortex-A8 does not recover from the 973 stale interworking branch prediction. This results in Cortex-A8 974 executing the new code sequence in the incorrect ARM or Thumb state. 975 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 976 and also flushes the branch target cache at every context switch. 977 Note that setting specific bits in the ACTLR register may not be 978 available in non-secure mode. 979 980config ARM_ERRATA_458693 981 bool "ARM errata: Processor deadlock when a false hazard is created" 982 depends on CPU_V7 983 depends on !ARCH_MULTIPLATFORM 984 help 985 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 986 erratum. For very specific sequences of memory operations, it is 987 possible for a hazard condition intended for a cache line to instead 988 be incorrectly associated with a different cache line. This false 989 hazard might then cause a processor deadlock. The workaround enables 990 the L1 caching of the NEON accesses and disables the PLD instruction 991 in the ACTLR register. Note that setting specific bits in the ACTLR 992 register may not be available in non-secure mode. 993 994config ARM_ERRATA_460075 995 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 996 depends on CPU_V7 997 depends on !ARCH_MULTIPLATFORM 998 help 999 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1000 erratum. Any asynchronous access to the L2 cache may encounter a 1001 situation in which recent store transactions to the L2 cache are lost 1002 and overwritten with stale memory contents from external memory. The 1003 workaround disables the write-allocate mode for the L2 cache via the 1004 ACTLR register. Note that setting specific bits in the ACTLR register 1005 may not be available in non-secure mode. 1006 1007config ARM_ERRATA_742230 1008 bool "ARM errata: DMB operation may be faulty" 1009 depends on CPU_V7 && SMP 1010 depends on !ARCH_MULTIPLATFORM 1011 help 1012 This option enables the workaround for the 742230 Cortex-A9 1013 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1014 between two write operations may not ensure the correct visibility 1015 ordering of the two writes. This workaround sets a specific bit in 1016 the diagnostic register of the Cortex-A9 which causes the DMB 1017 instruction to behave as a DSB, ensuring the correct behaviour of 1018 the two writes. 1019 1020config ARM_ERRATA_742231 1021 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1022 depends on CPU_V7 && SMP 1023 depends on !ARCH_MULTIPLATFORM 1024 help 1025 This option enables the workaround for the 742231 Cortex-A9 1026 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1027 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1028 accessing some data located in the same cache line, may get corrupted 1029 data due to bad handling of the address hazard when the line gets 1030 replaced from one of the CPUs at the same time as another CPU is 1031 accessing it. This workaround sets specific bits in the diagnostic 1032 register of the Cortex-A9 which reduces the linefill issuing 1033 capabilities of the processor. 1034 1035config ARM_ERRATA_643719 1036 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1037 depends on CPU_V7 && SMP 1038 default y 1039 help 1040 This option enables the workaround for the 643719 Cortex-A9 (prior to 1041 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1042 register returns zero when it should return one. The workaround 1043 corrects this value, ensuring cache maintenance operations which use 1044 it behave as intended and avoiding data corruption. 1045 1046config ARM_ERRATA_720789 1047 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1048 depends on CPU_V7 1049 help 1050 This option enables the workaround for the 720789 Cortex-A9 (prior to 1051 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1052 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1053 As a consequence of this erratum, some TLB entries which should be 1054 invalidated are not, resulting in an incoherency in the system page 1055 tables. The workaround changes the TLB flushing routines to invalidate 1056 entries regardless of the ASID. 1057 1058config ARM_ERRATA_743622 1059 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1060 depends on CPU_V7 1061 depends on !ARCH_MULTIPLATFORM 1062 help 1063 This option enables the workaround for the 743622 Cortex-A9 1064 (r2p*) erratum. Under very rare conditions, a faulty 1065 optimisation in the Cortex-A9 Store Buffer may lead to data 1066 corruption. This workaround sets a specific bit in the diagnostic 1067 register of the Cortex-A9 which disables the Store Buffer 1068 optimisation, preventing the defect from occurring. This has no 1069 visible impact on the overall performance or power consumption of the 1070 processor. 1071 1072config ARM_ERRATA_751472 1073 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1074 depends on CPU_V7 1075 depends on !ARCH_MULTIPLATFORM 1076 help 1077 This option enables the workaround for the 751472 Cortex-A9 (prior 1078 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1079 completion of a following broadcasted operation if the second 1080 operation is received by a CPU before the ICIALLUIS has completed, 1081 potentially leading to corrupted entries in the cache or TLB. 1082 1083config ARM_ERRATA_754322 1084 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1085 depends on CPU_V7 1086 help 1087 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1088 r3p*) erratum. A speculative memory access may cause a page table walk 1089 which starts prior to an ASID switch but completes afterwards. This 1090 can populate the micro-TLB with a stale entry which may be hit with 1091 the new ASID. This workaround places two dsb instructions in the mm 1092 switching code so that no page table walks can cross the ASID switch. 1093 1094config ARM_ERRATA_754327 1095 bool "ARM errata: no automatic Store Buffer drain" 1096 depends on CPU_V7 && SMP 1097 help 1098 This option enables the workaround for the 754327 Cortex-A9 (prior to 1099 r2p0) erratum. The Store Buffer does not have any automatic draining 1100 mechanism and therefore a livelock may occur if an external agent 1101 continuously polls a memory location waiting to observe an update. 1102 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1103 written polling loops from denying visibility of updates to memory. 1104 1105config ARM_ERRATA_364296 1106 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1107 depends on CPU_V6 1108 help 1109 This options enables the workaround for the 364296 ARM1136 1110 r0p2 erratum (possible cache data corruption with 1111 hit-under-miss enabled). It sets the undocumented bit 31 in 1112 the auxiliary control register and the FI bit in the control 1113 register, thus disabling hit-under-miss without putting the 1114 processor into full low interrupt latency mode. ARM11MPCore 1115 is not affected. 1116 1117config ARM_ERRATA_764369 1118 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1119 depends on CPU_V7 && SMP 1120 help 1121 This option enables the workaround for erratum 764369 1122 affecting Cortex-A9 MPCore with two or more processors (all 1123 current revisions). Under certain timing circumstances, a data 1124 cache line maintenance operation by MVA targeting an Inner 1125 Shareable memory region may fail to proceed up to either the 1126 Point of Coherency or to the Point of Unification of the 1127 system. This workaround adds a DSB instruction before the 1128 relevant cache maintenance functions and sets a specific bit 1129 in the diagnostic control register of the SCU. 1130 1131config ARM_ERRATA_775420 1132 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1133 depends on CPU_V7 1134 help 1135 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1136 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1137 operation aborts with MMU exception, it might cause the processor 1138 to deadlock. This workaround puts DSB before executing ISB if 1139 an abort may occur on cache maintenance. 1140 1141config ARM_ERRATA_798181 1142 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1143 depends on CPU_V7 && SMP 1144 help 1145 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1146 adequately shooting down all use of the old entries. This 1147 option enables the Linux kernel workaround for this erratum 1148 which sends an IPI to the CPUs that are running the same ASID 1149 as the one being invalidated. 1150 1151config ARM_ERRATA_773022 1152 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1153 depends on CPU_V7 1154 help 1155 This option enables the workaround for the 773022 Cortex-A15 1156 (up to r0p4) erratum. In certain rare sequences of code, the 1157 loop buffer may deliver incorrect instructions. This 1158 workaround disables the loop buffer to avoid the erratum. 1159 1160endmenu 1161 1162source "arch/arm/common/Kconfig" 1163 1164menu "Bus support" 1165 1166config ISA 1167 bool 1168 help 1169 Find out whether you have ISA slots on your motherboard. ISA is the 1170 name of a bus system, i.e. the way the CPU talks to the other stuff 1171 inside your box. Other bus systems are PCI, EISA, MicroChannel 1172 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1173 newer boards don't support it. If you have ISA, say Y, otherwise N. 1174 1175# Select ISA DMA controller support 1176config ISA_DMA 1177 bool 1178 select ISA_DMA_API 1179 1180# Select ISA DMA interface 1181config ISA_DMA_API 1182 bool 1183 1184config PCI 1185 bool "PCI support" if MIGHT_HAVE_PCI 1186 help 1187 Find out whether you have a PCI motherboard. PCI is the name of a 1188 bus system, i.e. the way the CPU talks to the other stuff inside 1189 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1190 VESA. If you have PCI, say Y, otherwise N. 1191 1192config PCI_DOMAINS 1193 bool 1194 depends on PCI 1195 1196config PCI_DOMAINS_GENERIC 1197 def_bool PCI_DOMAINS 1198 1199config PCI_NANOENGINE 1200 bool "BSE nanoEngine PCI support" 1201 depends on SA1100_NANOENGINE 1202 help 1203 Enable PCI on the BSE nanoEngine board. 1204 1205config PCI_SYSCALL 1206 def_bool PCI 1207 1208config PCI_HOST_ITE8152 1209 bool 1210 depends on PCI && MACH_ARMCORE 1211 default y 1212 select DMABOUNCE 1213 1214source "drivers/pci/Kconfig" 1215 1216source "drivers/pcmcia/Kconfig" 1217 1218endmenu 1219 1220menu "Kernel Features" 1221 1222config HAVE_SMP 1223 bool 1224 help 1225 This option should be selected by machines which have an SMP- 1226 capable CPU. 1227 1228 The only effect of this option is to make the SMP-related 1229 options available to the user for configuration. 1230 1231config SMP 1232 bool "Symmetric Multi-Processing" 1233 depends on CPU_V6K || CPU_V7 1234 depends on GENERIC_CLOCKEVENTS 1235 depends on HAVE_SMP 1236 depends on MMU || ARM_MPU 1237 select IRQ_WORK 1238 help 1239 This enables support for systems with more than one CPU. If you have 1240 a system with only one CPU, say N. If you have a system with more 1241 than one CPU, say Y. 1242 1243 If you say N here, the kernel will run on uni- and multiprocessor 1244 machines, but will use only one CPU of a multiprocessor machine. If 1245 you say Y here, the kernel will run on many, but not all, 1246 uniprocessor machines. On a uniprocessor machine, the kernel 1247 will run faster if you say N here. 1248 1249 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1250 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1251 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1252 1253 If you don't know what to do here, say N. 1254 1255config SMP_ON_UP 1256 bool "Allow booting SMP kernel on uniprocessor systems" 1257 depends on SMP && !XIP_KERNEL && MMU 1258 default y 1259 help 1260 SMP kernels contain instructions which fail on non-SMP processors. 1261 Enabling this option allows the kernel to modify itself to make 1262 these instructions safe. Disabling it allows about 1K of space 1263 savings. 1264 1265 If you don't know what to do here, say Y. 1266 1267config ARM_CPU_TOPOLOGY 1268 bool "Support cpu topology definition" 1269 depends on SMP && CPU_V7 1270 default y 1271 help 1272 Support ARM cpu topology definition. The MPIDR register defines 1273 affinity between processors which is then used to describe the cpu 1274 topology of an ARM System. 1275 1276config SCHED_MC 1277 bool "Multi-core scheduler support" 1278 depends on ARM_CPU_TOPOLOGY 1279 help 1280 Multi-core scheduler support improves the CPU scheduler's decision 1281 making when dealing with multi-core CPU chips at a cost of slightly 1282 increased overhead in some places. If unsure say N here. 1283 1284config SCHED_SMT 1285 bool "SMT scheduler support" 1286 depends on ARM_CPU_TOPOLOGY 1287 help 1288 Improves the CPU scheduler's decision making when dealing with 1289 MultiThreading at a cost of slightly increased overhead in some 1290 places. If unsure say N here. 1291 1292config HAVE_ARM_SCU 1293 bool 1294 help 1295 This option enables support for the ARM system coherency unit 1296 1297config HAVE_ARM_ARCH_TIMER 1298 bool "Architected timer support" 1299 depends on CPU_V7 1300 select ARM_ARCH_TIMER 1301 select GENERIC_CLOCKEVENTS 1302 help 1303 This option enables support for the ARM architected timer 1304 1305config HAVE_ARM_TWD 1306 bool 1307 select CLKSRC_OF if OF 1308 help 1309 This options enables support for the ARM timer and watchdog unit 1310 1311config MCPM 1312 bool "Multi-Cluster Power Management" 1313 depends on CPU_V7 && SMP 1314 help 1315 This option provides the common power management infrastructure 1316 for (multi-)cluster based systems, such as big.LITTLE based 1317 systems. 1318 1319config MCPM_QUAD_CLUSTER 1320 bool 1321 depends on MCPM 1322 help 1323 To avoid wasting resources unnecessarily, MCPM only supports up 1324 to 2 clusters by default. 1325 Platforms with 3 or 4 clusters that use MCPM must select this 1326 option to allow the additional clusters to be managed. 1327 1328config BIG_LITTLE 1329 bool "big.LITTLE support (Experimental)" 1330 depends on CPU_V7 && SMP 1331 select MCPM 1332 help 1333 This option enables support selections for the big.LITTLE 1334 system architecture. 1335 1336config BL_SWITCHER 1337 bool "big.LITTLE switcher support" 1338 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1339 select ARM_CPU_SUSPEND 1340 select CPU_PM 1341 help 1342 The big.LITTLE "switcher" provides the core functionality to 1343 transparently handle transition between a cluster of A15's 1344 and a cluster of A7's in a big.LITTLE system. 1345 1346config BL_SWITCHER_DUMMY_IF 1347 tristate "Simple big.LITTLE switcher user interface" 1348 depends on BL_SWITCHER && DEBUG_KERNEL 1349 help 1350 This is a simple and dummy char dev interface to control 1351 the big.LITTLE switcher core code. It is meant for 1352 debugging purposes only. 1353 1354choice 1355 prompt "Memory split" 1356 depends on MMU 1357 default VMSPLIT_3G 1358 help 1359 Select the desired split between kernel and user memory. 1360 1361 If you are not absolutely sure what you are doing, leave this 1362 option alone! 1363 1364 config VMSPLIT_3G 1365 bool "3G/1G user/kernel split" 1366 config VMSPLIT_3G_OPT 1367 bool "3G/1G user/kernel split (for full 1G low memory)" 1368 config VMSPLIT_2G 1369 bool "2G/2G user/kernel split" 1370 config VMSPLIT_1G 1371 bool "1G/3G user/kernel split" 1372endchoice 1373 1374config PAGE_OFFSET 1375 hex 1376 default PHYS_OFFSET if !MMU 1377 default 0x40000000 if VMSPLIT_1G 1378 default 0x80000000 if VMSPLIT_2G 1379 default 0xB0000000 if VMSPLIT_3G_OPT 1380 default 0xC0000000 1381 1382config NR_CPUS 1383 int "Maximum number of CPUs (2-32)" 1384 range 2 32 1385 depends on SMP 1386 default "4" 1387 1388config HOTPLUG_CPU 1389 bool "Support for hot-pluggable CPUs" 1390 depends on SMP 1391 help 1392 Say Y here to experiment with turning CPUs off and on. CPUs 1393 can be controlled through /sys/devices/system/cpu. 1394 1395config ARM_PSCI 1396 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1397 depends on HAVE_ARM_SMCCC 1398 select ARM_PSCI_FW 1399 help 1400 Say Y here if you want Linux to communicate with system firmware 1401 implementing the PSCI specification for CPU-centric power 1402 management operations described in ARM document number ARM DEN 1403 0022A ("Power State Coordination Interface System Software on 1404 ARM processors"). 1405 1406# The GPIO number here must be sorted by descending number. In case of 1407# a multiplatform kernel, we just want the highest value required by the 1408# selected platforms. 1409config ARCH_NR_GPIO 1410 int 1411 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1412 ARCH_ZYNQ 1413 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1414 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1415 default 416 if ARCH_SUNXI 1416 default 392 if ARCH_U8500 1417 default 352 if ARCH_VT8500 1418 default 288 if ARCH_ROCKCHIP 1419 default 264 if MACH_H4700 1420 default 0 1421 help 1422 Maximum number of GPIOs in the system. 1423 1424 If unsure, leave the default value. 1425 1426source kernel/Kconfig.preempt 1427 1428config HZ_FIXED 1429 int 1430 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1431 ARCH_S5PV210 || ARCH_EXYNOS4 1432 default 128 if SOC_AT91RM9200 1433 default 0 1434 1435choice 1436 depends on HZ_FIXED = 0 1437 prompt "Timer frequency" 1438 1439config HZ_100 1440 bool "100 Hz" 1441 1442config HZ_200 1443 bool "200 Hz" 1444 1445config HZ_250 1446 bool "250 Hz" 1447 1448config HZ_300 1449 bool "300 Hz" 1450 1451config HZ_500 1452 bool "500 Hz" 1453 1454config HZ_1000 1455 bool "1000 Hz" 1456 1457endchoice 1458 1459config HZ 1460 int 1461 default HZ_FIXED if HZ_FIXED != 0 1462 default 100 if HZ_100 1463 default 200 if HZ_200 1464 default 250 if HZ_250 1465 default 300 if HZ_300 1466 default 500 if HZ_500 1467 default 1000 1468 1469config SCHED_HRTICK 1470 def_bool HIGH_RES_TIMERS 1471 1472config THUMB2_KERNEL 1473 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1474 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1475 default y if CPU_THUMBONLY 1476 select AEABI 1477 select ARM_ASM_UNIFIED 1478 select ARM_UNWIND 1479 help 1480 By enabling this option, the kernel will be compiled in 1481 Thumb-2 mode. A compiler/assembler that understand the unified 1482 ARM-Thumb syntax is needed. 1483 1484 If unsure, say N. 1485 1486config THUMB2_AVOID_R_ARM_THM_JUMP11 1487 bool "Work around buggy Thumb-2 short branch relocations in gas" 1488 depends on THUMB2_KERNEL && MODULES 1489 default y 1490 help 1491 Various binutils versions can resolve Thumb-2 branches to 1492 locally-defined, preemptible global symbols as short-range "b.n" 1493 branch instructions. 1494 1495 This is a problem, because there's no guarantee the final 1496 destination of the symbol, or any candidate locations for a 1497 trampoline, are within range of the branch. For this reason, the 1498 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1499 relocation in modules at all, and it makes little sense to add 1500 support. 1501 1502 The symptom is that the kernel fails with an "unsupported 1503 relocation" error when loading some modules. 1504 1505 Until fixed tools are available, passing 1506 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1507 code which hits this problem, at the cost of a bit of extra runtime 1508 stack usage in some cases. 1509 1510 The problem is described in more detail at: 1511 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1512 1513 Only Thumb-2 kernels are affected. 1514 1515 Unless you are sure your tools don't have this problem, say Y. 1516 1517config ARM_ASM_UNIFIED 1518 bool 1519 1520config ARM_PATCH_IDIV 1521 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1522 depends on CPU_32v7 && !XIP_KERNEL 1523 default y 1524 help 1525 The ARM compiler inserts calls to __aeabi_idiv() and 1526 __aeabi_uidiv() when it needs to perform division on signed 1527 and unsigned integers. Some v7 CPUs have support for the sdiv 1528 and udiv instructions that can be used to implement those 1529 functions. 1530 1531 Enabling this option allows the kernel to modify itself to 1532 replace the first two instructions of these library functions 1533 with the sdiv or udiv plus "bx lr" instructions when the CPU 1534 it is running on supports them. Typically this will be faster 1535 and less power intensive than running the original library 1536 code to do integer division. 1537 1538config AEABI 1539 bool "Use the ARM EABI to compile the kernel" 1540 help 1541 This option allows for the kernel to be compiled using the latest 1542 ARM ABI (aka EABI). This is only useful if you are using a user 1543 space environment that is also compiled with EABI. 1544 1545 Since there are major incompatibilities between the legacy ABI and 1546 EABI, especially with regard to structure member alignment, this 1547 option also changes the kernel syscall calling convention to 1548 disambiguate both ABIs and allow for backward compatibility support 1549 (selected with CONFIG_OABI_COMPAT). 1550 1551 To use this you need GCC version 4.0.0 or later. 1552 1553config OABI_COMPAT 1554 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1555 depends on AEABI && !THUMB2_KERNEL 1556 help 1557 This option preserves the old syscall interface along with the 1558 new (ARM EABI) one. It also provides a compatibility layer to 1559 intercept syscalls that have structure arguments which layout 1560 in memory differs between the legacy ABI and the new ARM EABI 1561 (only for non "thumb" binaries). This option adds a tiny 1562 overhead to all syscalls and produces a slightly larger kernel. 1563 1564 The seccomp filter system will not be available when this is 1565 selected, since there is no way yet to sensibly distinguish 1566 between calling conventions during filtering. 1567 1568 If you know you'll be using only pure EABI user space then you 1569 can say N here. If this option is not selected and you attempt 1570 to execute a legacy ABI binary then the result will be 1571 UNPREDICTABLE (in fact it can be predicted that it won't work 1572 at all). If in doubt say N. 1573 1574config ARCH_HAS_HOLES_MEMORYMODEL 1575 bool 1576 1577config ARCH_SPARSEMEM_ENABLE 1578 bool 1579 1580config ARCH_SPARSEMEM_DEFAULT 1581 def_bool ARCH_SPARSEMEM_ENABLE 1582 1583config ARCH_SELECT_MEMORY_MODEL 1584 def_bool ARCH_SPARSEMEM_ENABLE 1585 1586config HAVE_ARCH_PFN_VALID 1587 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1588 1589config HAVE_GENERIC_RCU_GUP 1590 def_bool y 1591 depends on ARM_LPAE 1592 1593config HIGHMEM 1594 bool "High Memory Support" 1595 depends on MMU 1596 help 1597 The address space of ARM processors is only 4 Gigabytes large 1598 and it has to accommodate user address space, kernel address 1599 space as well as some memory mapped IO. That means that, if you 1600 have a large amount of physical memory and/or IO, not all of the 1601 memory can be "permanently mapped" by the kernel. The physical 1602 memory that is not permanently mapped is called "high memory". 1603 1604 Depending on the selected kernel/user memory split, minimum 1605 vmalloc space and actual amount of RAM, you may not need this 1606 option which should result in a slightly faster kernel. 1607 1608 If unsure, say n. 1609 1610config HIGHPTE 1611 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1612 depends on HIGHMEM 1613 default y 1614 help 1615 The VM uses one page of physical memory for each page table. 1616 For systems with a lot of processes, this can use a lot of 1617 precious low memory, eventually leading to low memory being 1618 consumed by page tables. Setting this option will allow 1619 user-space 2nd level page tables to reside in high memory. 1620 1621config CPU_SW_DOMAIN_PAN 1622 bool "Enable use of CPU domains to implement privileged no-access" 1623 depends on MMU && !ARM_LPAE 1624 default y 1625 help 1626 Increase kernel security by ensuring that normal kernel accesses 1627 are unable to access userspace addresses. This can help prevent 1628 use-after-free bugs becoming an exploitable privilege escalation 1629 by ensuring that magic values (such as LIST_POISON) will always 1630 fault when dereferenced. 1631 1632 CPUs with low-vector mappings use a best-efforts implementation. 1633 Their lower 1MB needs to remain accessible for the vectors, but 1634 the remainder of userspace will become appropriately inaccessible. 1635 1636config HW_PERF_EVENTS 1637 def_bool y 1638 depends on ARM_PMU 1639 1640config SYS_SUPPORTS_HUGETLBFS 1641 def_bool y 1642 depends on ARM_LPAE 1643 1644config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1645 def_bool y 1646 depends on ARM_LPAE 1647 1648config ARCH_WANT_GENERAL_HUGETLB 1649 def_bool y 1650 1651config ARM_MODULE_PLTS 1652 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1653 depends on MODULES 1654 help 1655 Allocate PLTs when loading modules so that jumps and calls whose 1656 targets are too far away for their relative offsets to be encoded 1657 in the instructions themselves can be bounced via veneers in the 1658 module's PLT. This allows modules to be allocated in the generic 1659 vmalloc area after the dedicated module memory area has been 1660 exhausted. The modules will use slightly more memory, but after 1661 rounding up to page size, the actual memory footprint is usually 1662 the same. 1663 1664 Say y if you are getting out of memory errors while loading modules 1665 1666source "mm/Kconfig" 1667 1668config FORCE_MAX_ZONEORDER 1669 int "Maximum zone order" 1670 default "12" if SOC_AM33XX 1671 default "9" if SA1111 || ARCH_EFM32 1672 default "11" 1673 help 1674 The kernel memory allocator divides physically contiguous memory 1675 blocks into "zones", where each zone is a power of two number of 1676 pages. This option selects the largest power of two that the kernel 1677 keeps in the memory allocator. If you need to allocate very large 1678 blocks of physically contiguous memory, then you may need to 1679 increase this value. 1680 1681 This config option is actually maximum order plus one. For example, 1682 a value of 11 means that the largest free memory block is 2^10 pages. 1683 1684config ALIGNMENT_TRAP 1685 bool 1686 depends on CPU_CP15_MMU 1687 default y if !ARCH_EBSA110 1688 select HAVE_PROC_CPU if PROC_FS 1689 help 1690 ARM processors cannot fetch/store information which is not 1691 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1692 address divisible by 4. On 32-bit ARM processors, these non-aligned 1693 fetch/store instructions will be emulated in software if you say 1694 here, which has a severe performance impact. This is necessary for 1695 correct operation of some network protocols. With an IP-only 1696 configuration it is safe to say N, otherwise say Y. 1697 1698config UACCESS_WITH_MEMCPY 1699 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1700 depends on MMU 1701 default y if CPU_FEROCEON 1702 help 1703 Implement faster copy_to_user and clear_user methods for CPU 1704 cores where a 8-word STM instruction give significantly higher 1705 memory write throughput than a sequence of individual 32bit stores. 1706 1707 A possible side effect is a slight increase in scheduling latency 1708 between threads sharing the same address space if they invoke 1709 such copy operations with large buffers. 1710 1711 However, if the CPU data cache is using a write-allocate mode, 1712 this option is unlikely to provide any performance gain. 1713 1714config SECCOMP 1715 bool 1716 prompt "Enable seccomp to safely compute untrusted bytecode" 1717 ---help--- 1718 This kernel feature is useful for number crunching applications 1719 that may need to compute untrusted bytecode during their 1720 execution. By using pipes or other transports made available to 1721 the process as file descriptors supporting the read/write 1722 syscalls, it's possible to isolate those applications in 1723 their own address space using seccomp. Once seccomp is 1724 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1725 and the task is only allowed to execute a few safe syscalls 1726 defined by each seccomp mode. 1727 1728config SWIOTLB 1729 def_bool y 1730 1731config IOMMU_HELPER 1732 def_bool SWIOTLB 1733 1734config PARAVIRT 1735 bool "Enable paravirtualization code" 1736 help 1737 This changes the kernel so it can modify itself when it is run 1738 under a hypervisor, potentially improving performance significantly 1739 over full virtualization. 1740 1741config PARAVIRT_TIME_ACCOUNTING 1742 bool "Paravirtual steal time accounting" 1743 select PARAVIRT 1744 default n 1745 help 1746 Select this option to enable fine granularity task steal time 1747 accounting. Time spent executing other tasks in parallel with 1748 the current vCPU is discounted from the vCPU power. To account for 1749 that, there can be a small performance impact. 1750 1751 If in doubt, say N here. 1752 1753config XEN_DOM0 1754 def_bool y 1755 depends on XEN 1756 1757config XEN 1758 bool "Xen guest support on ARM" 1759 depends on ARM && AEABI && OF 1760 depends on CPU_V7 && !CPU_V6 1761 depends on !GENERIC_ATOMIC64 1762 depends on MMU 1763 select ARCH_DMA_ADDR_T_64BIT 1764 select ARM_PSCI 1765 select SWIOTLB_XEN 1766 select PARAVIRT 1767 help 1768 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1769 1770endmenu 1771 1772menu "Boot options" 1773 1774config USE_OF 1775 bool "Flattened Device Tree support" 1776 select IRQ_DOMAIN 1777 select OF 1778 help 1779 Include support for flattened device tree machine descriptions. 1780 1781config ATAGS 1782 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1783 default y 1784 help 1785 This is the traditional way of passing data to the kernel at boot 1786 time. If you are solely relying on the flattened device tree (or 1787 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1788 to remove ATAGS support from your kernel binary. If unsure, 1789 leave this to y. 1790 1791config DEPRECATED_PARAM_STRUCT 1792 bool "Provide old way to pass kernel parameters" 1793 depends on ATAGS 1794 help 1795 This was deprecated in 2001 and announced to live on for 5 years. 1796 Some old boot loaders still use this way. 1797 1798# Compressed boot loader in ROM. Yes, we really want to ask about 1799# TEXT and BSS so we preserve their values in the config files. 1800config ZBOOT_ROM_TEXT 1801 hex "Compressed ROM boot loader base address" 1802 default "0" 1803 help 1804 The physical address at which the ROM-able zImage is to be 1805 placed in the target. Platforms which normally make use of 1806 ROM-able zImage formats normally set this to a suitable 1807 value in their defconfig file. 1808 1809 If ZBOOT_ROM is not enabled, this has no effect. 1810 1811config ZBOOT_ROM_BSS 1812 hex "Compressed ROM boot loader BSS address" 1813 default "0" 1814 help 1815 The base address of an area of read/write memory in the target 1816 for the ROM-able zImage which must be available while the 1817 decompressor is running. It must be large enough to hold the 1818 entire decompressed kernel plus an additional 128 KiB. 1819 Platforms which normally make use of ROM-able zImage formats 1820 normally set this to a suitable value in their defconfig file. 1821 1822 If ZBOOT_ROM is not enabled, this has no effect. 1823 1824config ZBOOT_ROM 1825 bool "Compressed boot loader in ROM/flash" 1826 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1827 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1828 help 1829 Say Y here if you intend to execute your compressed kernel image 1830 (zImage) directly from ROM or flash. If unsure, say N. 1831 1832config ARM_APPENDED_DTB 1833 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1834 depends on OF 1835 help 1836 With this option, the boot code will look for a device tree binary 1837 (DTB) appended to zImage 1838 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1839 1840 This is meant as a backward compatibility convenience for those 1841 systems with a bootloader that can't be upgraded to accommodate 1842 the documented boot protocol using a device tree. 1843 1844 Beware that there is very little in terms of protection against 1845 this option being confused by leftover garbage in memory that might 1846 look like a DTB header after a reboot if no actual DTB is appended 1847 to zImage. Do not leave this option active in a production kernel 1848 if you don't intend to always append a DTB. Proper passing of the 1849 location into r2 of a bootloader provided DTB is always preferable 1850 to this option. 1851 1852config ARM_ATAG_DTB_COMPAT 1853 bool "Supplement the appended DTB with traditional ATAG information" 1854 depends on ARM_APPENDED_DTB 1855 help 1856 Some old bootloaders can't be updated to a DTB capable one, yet 1857 they provide ATAGs with memory configuration, the ramdisk address, 1858 the kernel cmdline string, etc. Such information is dynamically 1859 provided by the bootloader and can't always be stored in a static 1860 DTB. To allow a device tree enabled kernel to be used with such 1861 bootloaders, this option allows zImage to extract the information 1862 from the ATAG list and store it at run time into the appended DTB. 1863 1864choice 1865 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1866 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1867 1868config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1869 bool "Use bootloader kernel arguments if available" 1870 help 1871 Uses the command-line options passed by the boot loader instead of 1872 the device tree bootargs property. If the boot loader doesn't provide 1873 any, the device tree bootargs property will be used. 1874 1875config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1876 bool "Extend with bootloader kernel arguments" 1877 help 1878 The command-line arguments provided by the boot loader will be 1879 appended to the the device tree bootargs property. 1880 1881endchoice 1882 1883config CMDLINE 1884 string "Default kernel command string" 1885 default "" 1886 help 1887 On some architectures (EBSA110 and CATS), there is currently no way 1888 for the boot loader to pass arguments to the kernel. For these 1889 architectures, you should supply some command-line options at build 1890 time by entering them here. As a minimum, you should specify the 1891 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1892 1893choice 1894 prompt "Kernel command line type" if CMDLINE != "" 1895 default CMDLINE_FROM_BOOTLOADER 1896 depends on ATAGS 1897 1898config CMDLINE_FROM_BOOTLOADER 1899 bool "Use bootloader kernel arguments if available" 1900 help 1901 Uses the command-line options passed by the boot loader. If 1902 the boot loader doesn't provide any, the default kernel command 1903 string provided in CMDLINE will be used. 1904 1905config CMDLINE_EXTEND 1906 bool "Extend bootloader kernel arguments" 1907 help 1908 The command-line arguments provided by the boot loader will be 1909 appended to the default kernel command string. 1910 1911config CMDLINE_FORCE 1912 bool "Always use the default kernel command string" 1913 help 1914 Always use the default kernel command string, even if the boot 1915 loader passes other arguments to the kernel. 1916 This is useful if you cannot or don't want to change the 1917 command-line options your boot loader passes to the kernel. 1918endchoice 1919 1920config XIP_KERNEL 1921 bool "Kernel Execute-In-Place from ROM" 1922 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1923 help 1924 Execute-In-Place allows the kernel to run from non-volatile storage 1925 directly addressable by the CPU, such as NOR flash. This saves RAM 1926 space since the text section of the kernel is not loaded from flash 1927 to RAM. Read-write sections, such as the data section and stack, 1928 are still copied to RAM. The XIP kernel is not compressed since 1929 it has to run directly from flash, so it will take more space to 1930 store it. The flash address used to link the kernel object files, 1931 and for storing it, is configuration dependent. Therefore, if you 1932 say Y here, you must know the proper physical address where to 1933 store the kernel image depending on your own flash memory usage. 1934 1935 Also note that the make target becomes "make xipImage" rather than 1936 "make zImage" or "make Image". The final kernel binary to put in 1937 ROM memory will be arch/arm/boot/xipImage. 1938 1939 If unsure, say N. 1940 1941config XIP_PHYS_ADDR 1942 hex "XIP Kernel Physical Location" 1943 depends on XIP_KERNEL 1944 default "0x00080000" 1945 help 1946 This is the physical address in your flash memory the kernel will 1947 be linked for and stored to. This address is dependent on your 1948 own flash usage. 1949 1950config KEXEC 1951 bool "Kexec system call (EXPERIMENTAL)" 1952 depends on (!SMP || PM_SLEEP_SMP) 1953 depends on !CPU_V7M 1954 select KEXEC_CORE 1955 help 1956 kexec is a system call that implements the ability to shutdown your 1957 current kernel, and to start another kernel. It is like a reboot 1958 but it is independent of the system firmware. And like a reboot 1959 you can start any kernel with it, not just Linux. 1960 1961 It is an ongoing process to be certain the hardware in a machine 1962 is properly shutdown, so do not be surprised if this code does not 1963 initially work for you. 1964 1965config ATAGS_PROC 1966 bool "Export atags in procfs" 1967 depends on ATAGS && KEXEC 1968 default y 1969 help 1970 Should the atags used to boot the kernel be exported in an "atags" 1971 file in procfs. Useful with kexec. 1972 1973config CRASH_DUMP 1974 bool "Build kdump crash kernel (EXPERIMENTAL)" 1975 help 1976 Generate crash dump after being started by kexec. This should 1977 be normally only set in special crash dump kernels which are 1978 loaded in the main kernel with kexec-tools into a specially 1979 reserved region and then later executed after a crash by 1980 kdump/kexec. The crash dump kernel must be compiled to a 1981 memory address not used by the main kernel 1982 1983 For more details see Documentation/kdump/kdump.txt 1984 1985config AUTO_ZRELADDR 1986 bool "Auto calculation of the decompressed kernel image address" 1987 help 1988 ZRELADDR is the physical address where the decompressed kernel 1989 image will be placed. If AUTO_ZRELADDR is selected, the address 1990 will be determined at run-time by masking the current IP with 1991 0xf8000000. This assumes the zImage being placed in the first 128MB 1992 from start of memory. 1993 1994config EFI_STUB 1995 bool 1996 1997config EFI 1998 bool "UEFI runtime support" 1999 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2000 select UCS2_STRING 2001 select EFI_PARAMS_FROM_FDT 2002 select EFI_STUB 2003 select EFI_ARMSTUB 2004 select EFI_RUNTIME_WRAPPERS 2005 ---help--- 2006 This option provides support for runtime services provided 2007 by UEFI firmware (such as non-volatile variables, realtime 2008 clock, and platform reset). A UEFI stub is also provided to 2009 allow the kernel to be booted as an EFI application. This 2010 is only useful for kernels that may run on systems that have 2011 UEFI firmware. 2012 2013endmenu 2014 2015menu "CPU Power Management" 2016 2017source "drivers/cpufreq/Kconfig" 2018 2019source "drivers/cpuidle/Kconfig" 2020 2021endmenu 2022 2023menu "Floating point emulation" 2024 2025comment "At least one emulation must be selected" 2026 2027config FPE_NWFPE 2028 bool "NWFPE math emulation" 2029 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2030 ---help--- 2031 Say Y to include the NWFPE floating point emulator in the kernel. 2032 This is necessary to run most binaries. Linux does not currently 2033 support floating point hardware so you need to say Y here even if 2034 your machine has an FPA or floating point co-processor podule. 2035 2036 You may say N here if you are going to load the Acorn FPEmulator 2037 early in the bootup. 2038 2039config FPE_NWFPE_XP 2040 bool "Support extended precision" 2041 depends on FPE_NWFPE 2042 help 2043 Say Y to include 80-bit support in the kernel floating-point 2044 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2045 Note that gcc does not generate 80-bit operations by default, 2046 so in most cases this option only enlarges the size of the 2047 floating point emulator without any good reason. 2048 2049 You almost surely want to say N here. 2050 2051config FPE_FASTFPE 2052 bool "FastFPE math emulation (EXPERIMENTAL)" 2053 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2054 ---help--- 2055 Say Y here to include the FAST floating point emulator in the kernel. 2056 This is an experimental much faster emulator which now also has full 2057 precision for the mantissa. It does not support any exceptions. 2058 It is very simple, and approximately 3-6 times faster than NWFPE. 2059 2060 It should be sufficient for most programs. It may be not suitable 2061 for scientific calculations, but you have to check this for yourself. 2062 If you do not feel you need a faster FP emulation you should better 2063 choose NWFPE. 2064 2065config VFP 2066 bool "VFP-format floating point maths" 2067 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2068 help 2069 Say Y to include VFP support code in the kernel. This is needed 2070 if your hardware includes a VFP unit. 2071 2072 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2073 release notes and additional status information. 2074 2075 Say N if your target does not have VFP hardware. 2076 2077config VFPv3 2078 bool 2079 depends on VFP 2080 default y if CPU_V7 2081 2082config NEON 2083 bool "Advanced SIMD (NEON) Extension support" 2084 depends on VFPv3 && CPU_V7 2085 help 2086 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2087 Extension. 2088 2089config KERNEL_MODE_NEON 2090 bool "Support for NEON in kernel mode" 2091 depends on NEON && AEABI 2092 help 2093 Say Y to include support for NEON in kernel mode. 2094 2095endmenu 2096 2097menu "Userspace binary formats" 2098 2099source "fs/Kconfig.binfmt" 2100 2101endmenu 2102 2103menu "Power management options" 2104 2105source "kernel/power/Kconfig" 2106 2107config ARCH_SUSPEND_POSSIBLE 2108 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2109 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2110 def_bool y 2111 2112config ARM_CPU_SUSPEND 2113 def_bool PM_SLEEP 2114 2115config ARCH_HIBERNATION_POSSIBLE 2116 bool 2117 depends on MMU 2118 default y if ARCH_SUSPEND_POSSIBLE 2119 2120endmenu 2121 2122source "net/Kconfig" 2123 2124source "drivers/Kconfig" 2125 2126source "drivers/firmware/Kconfig" 2127 2128source "fs/Kconfig" 2129 2130source "arch/arm/Kconfig.debug" 2131 2132source "security/Kconfig" 2133 2134source "crypto/Kconfig" 2135if CRYPTO 2136source "arch/arm/crypto/Kconfig" 2137endif 2138 2139source "lib/Kconfig" 2140 2141source "arch/arm/kvm/Kconfig" 2142