1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4 */ 5 6 #include <linux/seq_file.h> 7 #include <linux/fs.h> 8 #include <linux/delay.h> 9 #include <linux/root_dev.h> 10 #include <linux/clk.h> 11 #include <linux/clocksource.h> 12 #include <linux/console.h> 13 #include <linux/module.h> 14 #include <linux/sizes.h> 15 #include <linux/cpu.h> 16 #include <linux/of_clk.h> 17 #include <linux/of_fdt.h> 18 #include <linux/of.h> 19 #include <linux/cache.h> 20 #include <uapi/linux/mount.h> 21 #include <asm/sections.h> 22 #include <asm/arcregs.h> 23 #include <asm/asserts.h> 24 #include <asm/tlb.h> 25 #include <asm/setup.h> 26 #include <asm/page.h> 27 #include <asm/irq.h> 28 #include <asm/unwind.h> 29 #include <asm/mach_desc.h> 30 #include <asm/smp.h> 31 #include <asm/dsp-impl.h> 32 33 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 34 35 unsigned int intr_to_DE_cnt; 36 37 /* Part of U-boot ABI: see head.S */ 38 int __initdata uboot_tag; 39 int __initdata uboot_magic; 40 char __initdata *uboot_arg; 41 42 const struct machine_desc *machine_desc; 43 44 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 45 46 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 47 48 static const struct id_to_str arc_legacy_rel[] = { 49 /* ID.ARCVER, Release */ 50 #ifdef CONFIG_ISA_ARCOMPACT 51 { 0x34, "R4.10"}, 52 { 0x35, "R4.11"}, 53 #else 54 { 0x51, "R2.0" }, 55 { 0x52, "R2.1" }, 56 { 0x53, "R3.0" }, 57 #endif 58 { 0x00, NULL } 59 }; 60 61 static const struct id_to_str arc_cpu_rel[] = { 62 /* UARCH.MAJOR, Release */ 63 { 0, "R3.10a"}, 64 { 1, "R3.50a"}, 65 { 0xFF, NULL } 66 }; 67 68 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 69 { 70 if (is_isa_arcompact()) { 71 struct bcr_iccm_arcompact iccm; 72 struct bcr_dccm_arcompact dccm; 73 74 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 75 if (iccm.ver) { 76 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ 77 cpu->iccm.base_addr = iccm.base << 16; 78 } 79 80 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 81 if (dccm.ver) { 82 unsigned long base; 83 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ 84 85 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); 86 cpu->dccm.base_addr = base & ~0xF; 87 } 88 } else { 89 struct bcr_iccm_arcv2 iccm; 90 struct bcr_dccm_arcv2 dccm; 91 unsigned long region; 92 93 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 94 if (iccm.ver) { 95 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ 96 if (iccm.sz00 == 0xF && iccm.sz01 > 0) 97 cpu->iccm.sz <<= iccm.sz01; 98 99 region = read_aux_reg(ARC_REG_AUX_ICCM); 100 cpu->iccm.base_addr = region & 0xF0000000; 101 } 102 103 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 104 if (dccm.ver) { 105 cpu->dccm.sz = 256 << dccm.sz0; 106 if (dccm.sz0 == 0xF && dccm.sz1 > 0) 107 cpu->dccm.sz <<= dccm.sz1; 108 109 region = read_aux_reg(ARC_REG_AUX_DCCM); 110 cpu->dccm.base_addr = region & 0xF0000000; 111 } 112 } 113 } 114 115 static void decode_arc_core(struct cpuinfo_arc *cpu) 116 { 117 struct bcr_uarch_build_arcv2 uarch; 118 const struct id_to_str *tbl; 119 120 /* 121 * Up until (including) the first core4 release (0x54) things were 122 * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family 123 * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue) 124 */ 125 126 if (cpu->core.family < 0x54) { /* includes arc700 */ 127 128 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) { 129 if (cpu->core.family == tbl->id) { 130 cpu->release = tbl->str; 131 break; 132 } 133 } 134 135 if (is_isa_arcompact()) 136 cpu->name = "ARC700"; 137 else if (tbl->str) 138 cpu->name = "HS38"; 139 else 140 cpu->name = cpu->release = "Unknown"; 141 142 return; 143 } 144 145 /* 146 * However the subsequent HS release (same 0x54) allow HS38 or HS48 147 * configurations and encode this info in a different BCR. 148 * The BCR was introduced in 0x54 so can't be read unconditionally. 149 */ 150 151 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); 152 153 if (uarch.prod == 4) { 154 cpu->name = "HS48"; 155 cpu->extn.dual = 1; 156 157 } else { 158 cpu->name = "HS38"; 159 } 160 161 for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) { 162 if (uarch.maj == tbl->id) { 163 cpu->release = tbl->str; 164 break; 165 } 166 } 167 } 168 169 static void read_arc_build_cfg_regs(void) 170 { 171 struct bcr_timer timer; 172 struct bcr_generic bcr; 173 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 174 struct bcr_isa_arcv2 isa; 175 struct bcr_actionpoint ap; 176 177 FIX_PTR(cpu); 178 179 READ_BCR(AUX_IDENTITY, cpu->core); 180 decode_arc_core(cpu); 181 182 READ_BCR(ARC_REG_TIMERS_BCR, timer); 183 cpu->extn.timer0 = timer.t0; 184 cpu->extn.timer1 = timer.t1; 185 cpu->extn.rtc = timer.rtc; 186 187 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 188 189 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 190 191 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 192 read_decode_ccm_bcr(cpu); 193 194 read_decode_mmu_bcr(); 195 read_decode_cache_bcr(); 196 197 if (is_isa_arcompact()) { 198 struct bcr_fp_arcompact sp, dp; 199 struct bcr_bpu_arcompact bpu; 200 201 READ_BCR(ARC_REG_FP_BCR, sp); 202 READ_BCR(ARC_REG_DPFP_BCR, dp); 203 cpu->extn.fpu_sp = sp.ver ? 1 : 0; 204 cpu->extn.fpu_dp = dp.ver ? 1 : 0; 205 206 READ_BCR(ARC_REG_BPU_BCR, bpu); 207 cpu->bpu.ver = bpu.ver; 208 cpu->bpu.full = bpu.fam ? 1 : 0; 209 if (bpu.ent) { 210 cpu->bpu.num_cache = 256 << (bpu.ent - 1); 211 cpu->bpu.num_pred = 256 << (bpu.ent - 1); 212 } 213 } else { 214 struct bcr_fp_arcv2 spdp; 215 struct bcr_bpu_arcv2 bpu; 216 217 READ_BCR(ARC_REG_FP_V2_BCR, spdp); 218 cpu->extn.fpu_sp = spdp.sp ? 1 : 0; 219 cpu->extn.fpu_dp = spdp.dp ? 1 : 0; 220 221 READ_BCR(ARC_REG_BPU_BCR, bpu); 222 cpu->bpu.ver = bpu.ver; 223 cpu->bpu.full = bpu.ft; 224 cpu->bpu.num_cache = 256 << bpu.bce; 225 cpu->bpu.num_pred = 2048 << bpu.pte; 226 cpu->bpu.ret_stk = 4 << bpu.rse; 227 228 /* if dual issue hardware, is it enabled ? */ 229 if (cpu->extn.dual) { 230 unsigned int exec_ctrl; 231 232 READ_BCR(AUX_EXEC_CTRL, exec_ctrl); 233 cpu->extn.dual_enb = !(exec_ctrl & 1); 234 } 235 } 236 237 READ_BCR(ARC_REG_AP_BCR, ap); 238 if (ap.ver) { 239 cpu->extn.ap_num = 2 << ap.num; 240 cpu->extn.ap_full = !ap.min; 241 } 242 243 READ_BCR(ARC_REG_SMART_BCR, bcr); 244 cpu->extn.smart = bcr.ver ? 1 : 0; 245 246 READ_BCR(ARC_REG_RTT_BCR, bcr); 247 cpu->extn.rtt = bcr.ver ? 1 : 0; 248 249 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); 250 251 /* some hacks for lack of feature BCR info in old ARC700 cores */ 252 if (is_isa_arcompact()) { 253 if (!isa.ver) /* ISA BCR absent, use Kconfig info */ 254 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); 255 else { 256 /* ARC700_BUILD only has 2 bits of isa info */ 257 struct bcr_generic bcr = *(struct bcr_generic *)&isa; 258 cpu->isa.atomic = bcr.info & 1; 259 } 260 261 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); 262 263 /* there's no direct way to distinguish 750 vs. 770 */ 264 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) 265 cpu->name = "ARC750"; 266 } else { 267 cpu->isa = isa; 268 } 269 } 270 271 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 272 { 273 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 274 struct bcr_identity *core = &cpu->core; 275 char mpy_opt[16]; 276 int n = 0; 277 278 FIX_PTR(cpu); 279 280 n += scnprintf(buf + n, len - n, 281 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", 282 core->family, core->cpu_id, core->chip_id); 283 284 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", 285 cpu_id, cpu->name, cpu->release, 286 is_isa_arcompact() ? "ARCompact" : "ARCv2", 287 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), 288 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); 289 290 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", 291 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), 292 IS_AVAIL1(cpu->extn.timer1, "Timer1 "), 293 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), 294 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); 295 296 if (cpu->extn_mpy.ver) { 297 if (is_isa_arcompact()) { 298 scnprintf(mpy_opt, 16, "mpy"); 299 } else { 300 301 int opt = 2; /* stock MPY/MPYH */ 302 303 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 304 opt = cpu->extn_mpy.dsp + 6; 305 306 scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt); 307 } 308 } 309 310 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 311 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), 312 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), 313 IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS), 314 IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt), 315 IS_AVAIL1(cpu->isa.div_rem, "div_rem ")); 316 317 if (cpu->bpu.ver) { 318 n += scnprintf(buf + n, len - n, 319 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", 320 IS_AVAIL1(cpu->bpu.full, "full"), 321 IS_AVAIL1(!cpu->bpu.full, "partial"), 322 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); 323 324 if (is_isa_arcv2()) { 325 struct bcr_lpb lpb; 326 327 READ_BCR(ARC_REG_LPB_BUILD, lpb); 328 if (lpb.ver) { 329 unsigned int ctl; 330 ctl = read_aux_reg(ARC_REG_LPB_CTRL); 331 332 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", 333 lpb.entries, 334 IS_DISABLED_RUN(!ctl)); 335 } 336 } 337 n += scnprintf(buf + n, len - n, "\n"); 338 } 339 340 return buf; 341 } 342 343 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 344 { 345 int n = 0; 346 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 347 348 FIX_PTR(cpu); 349 350 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); 351 352 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) 353 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", 354 IS_AVAIL1(cpu->extn.fpu_sp, "SP "), 355 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); 356 357 if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) { 358 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s", 359 IS_AVAIL1(cpu->extn.smart, "smaRT "), 360 IS_AVAIL1(cpu->extn.rtt, "RTT ")); 361 if (cpu->extn.ap_num) { 362 n += scnprintf(buf + n, len - n, "ActionPoint %d/%s", 363 cpu->extn.ap_num, 364 cpu->extn.ap_full ? "full":"min"); 365 } 366 n += scnprintf(buf + n, len - n, "\n"); 367 } 368 369 if (cpu->dccm.sz || cpu->iccm.sz) 370 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", 371 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), 372 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 373 374 if (is_isa_arcv2()) { 375 376 /* Error Protection: ECC/Parity */ 377 struct bcr_erp erp; 378 READ_BCR(ARC_REG_ERP_BUILD, erp); 379 380 if (erp.ver) { 381 struct ctl_erp ctl; 382 READ_BCR(ARC_REG_ERP_CTRL, ctl); 383 384 /* inverted bits: 0 means enabled */ 385 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", 386 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), 387 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), 388 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); 389 } 390 } 391 392 return buf; 393 } 394 395 void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena) 396 { 397 if (hw_exists && !opt_ena) 398 pr_warn(" ! Enable %s for working apps\n", opt_name); 399 else if (!hw_exists && opt_ena) 400 panic("Disable %s, hardware NOT present\n", opt_name); 401 } 402 403 void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena) 404 { 405 if (!hw_exists && opt_ena) 406 panic("Disable %s, hardware NOT present\n", opt_name); 407 } 408 409 static void arc_chk_core_config(void) 410 { 411 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 412 int present = 0; 413 414 if (!cpu->extn.timer0) 415 panic("Timer0 is not present!\n"); 416 417 if (!cpu->extn.timer1) 418 panic("Timer1 is not present!\n"); 419 420 #ifdef CONFIG_ARC_HAS_DCCM 421 /* 422 * DCCM can be arbit placed in hardware. 423 * Make sure it's placement/sz matches what Linux is built with 424 */ 425 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) 426 panic("Linux built with incorrect DCCM Base address\n"); 427 428 if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz) 429 panic("Linux built with incorrect DCCM Size\n"); 430 #endif 431 432 #ifdef CONFIG_ARC_HAS_ICCM 433 if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz) 434 panic("Linux built with incorrect ICCM Size\n"); 435 #endif 436 437 /* 438 * FP hardware/software config sanity 439 * -If hardware present, kernel needs to save/restore FPU state 440 * -If not, it will crash trying to save/restore the non-existant regs 441 */ 442 443 if (is_isa_arcompact()) { 444 /* only DPDP checked since SP has no arch visible regs */ 445 present = cpu->extn.fpu_dp; 446 CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present); 447 } else { 448 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ 449 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; 450 CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present); 451 452 dsp_config_check(); 453 } 454 } 455 456 /* 457 * Initialize and setup the processor core 458 * This is called by all the CPUs thus should not do special case stuff 459 * such as only for boot CPU etc 460 */ 461 462 void setup_processor(void) 463 { 464 char str[512]; 465 int cpu_id = smp_processor_id(); 466 467 read_arc_build_cfg_regs(); 468 arc_init_IRQ(); 469 470 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); 471 472 arc_mmu_init(); 473 arc_cache_init(); 474 475 pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 476 pr_info("%s", arc_platform_smp_cpuinfo()); 477 478 arc_chk_core_config(); 479 } 480 481 static inline bool uboot_arg_invalid(unsigned long addr) 482 { 483 /* 484 * Check that it is a untranslated address (although MMU is not enabled 485 * yet, it being a high address ensures this is not by fluke) 486 */ 487 if (addr < PAGE_OFFSET) 488 return true; 489 490 /* Check that address doesn't clobber resident kernel image */ 491 return addr >= (unsigned long)_stext && addr <= (unsigned long)_end; 492 } 493 494 #define IGNORE_ARGS "Ignore U-boot args: " 495 496 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */ 497 #define UBOOT_TAG_NONE 0 498 #define UBOOT_TAG_CMDLINE 1 499 #define UBOOT_TAG_DTB 2 500 /* We always pass 0 as magic from U-boot */ 501 #define UBOOT_MAGIC_VALUE 0 502 503 void __init handle_uboot_args(void) 504 { 505 bool use_embedded_dtb = true; 506 bool append_cmdline = false; 507 508 /* check that we know this tag */ 509 if (uboot_tag != UBOOT_TAG_NONE && 510 uboot_tag != UBOOT_TAG_CMDLINE && 511 uboot_tag != UBOOT_TAG_DTB) { 512 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag); 513 goto ignore_uboot_args; 514 } 515 516 if (uboot_magic != UBOOT_MAGIC_VALUE) { 517 pr_warn(IGNORE_ARGS "non zero uboot magic\n"); 518 goto ignore_uboot_args; 519 } 520 521 if (uboot_tag != UBOOT_TAG_NONE && 522 uboot_arg_invalid((unsigned long)uboot_arg)) { 523 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg); 524 goto ignore_uboot_args; 525 } 526 527 /* see if U-boot passed an external Device Tree blob */ 528 if (uboot_tag == UBOOT_TAG_DTB) { 529 machine_desc = setup_machine_fdt((void *)uboot_arg); 530 531 /* external Device Tree blob is invalid - use embedded one */ 532 use_embedded_dtb = !machine_desc; 533 } 534 535 if (uboot_tag == UBOOT_TAG_CMDLINE) 536 append_cmdline = true; 537 538 ignore_uboot_args: 539 540 if (use_embedded_dtb) { 541 machine_desc = setup_machine_fdt(__dtb_start); 542 if (!machine_desc) 543 panic("Embedded DT invalid\n"); 544 } 545 546 /* 547 * NOTE: @boot_command_line is populated by setup_machine_fdt() so this 548 * append processing can only happen after. 549 */ 550 if (append_cmdline) { 551 /* Ensure a whitespace between the 2 cmdlines */ 552 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); 553 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE); 554 } 555 } 556 557 void __init setup_arch(char **cmdline_p) 558 { 559 handle_uboot_args(); 560 561 /* Save unparsed command line copy for /proc/cmdline */ 562 *cmdline_p = boot_command_line; 563 564 /* To force early parsing of things like mem=xxx */ 565 parse_early_param(); 566 567 /* Platform/board specific: e.g. early console registration */ 568 if (machine_desc->init_early) 569 machine_desc->init_early(); 570 571 smp_init_cpus(); 572 573 setup_processor(); 574 setup_arch_memory(); 575 576 /* copy flat DT out of .init and then unflatten it */ 577 unflatten_and_copy_device_tree(); 578 579 /* Can be issue if someone passes cmd line arg "ro" 580 * But that is unlikely so keeping it as it is 581 */ 582 root_mountflags &= ~MS_RDONLY; 583 584 arc_unwind_init(); 585 } 586 587 /* 588 * Called from start_kernel() - boot CPU only 589 */ 590 void __init time_init(void) 591 { 592 of_clk_init(NULL); 593 timer_probe(); 594 } 595 596 static int __init customize_machine(void) 597 { 598 if (machine_desc->init_machine) 599 machine_desc->init_machine(); 600 601 return 0; 602 } 603 arch_initcall(customize_machine); 604 605 static int __init init_late_machine(void) 606 { 607 if (machine_desc->init_late) 608 machine_desc->init_late(); 609 610 return 0; 611 } 612 late_initcall(init_late_machine); 613 /* 614 * Get CPU information for use by the procfs. 615 */ 616 617 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) 618 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) 619 620 static int show_cpuinfo(struct seq_file *m, void *v) 621 { 622 char *str; 623 int cpu_id = ptr_to_cpu(v); 624 struct device *cpu_dev = get_cpu_device(cpu_id); 625 struct clk *cpu_clk; 626 unsigned long freq = 0; 627 628 if (!cpu_online(cpu_id)) { 629 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); 630 goto done; 631 } 632 633 str = (char *)__get_free_page(GFP_KERNEL); 634 if (!str) 635 goto done; 636 637 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 638 639 cpu_clk = clk_get(cpu_dev, NULL); 640 if (IS_ERR(cpu_clk)) { 641 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", 642 cpu_id); 643 } else { 644 freq = clk_get_rate(cpu_clk); 645 } 646 if (freq) 647 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", 648 freq / 1000000, (freq / 10000) % 100); 649 650 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", 651 loops_per_jiffy / (500000 / HZ), 652 (loops_per_jiffy / (5000 / HZ)) % 100); 653 654 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 655 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 656 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 657 seq_printf(m, arc_platform_smp_cpuinfo()); 658 659 free_page((unsigned long)str); 660 done: 661 seq_printf(m, "\n"); 662 663 return 0; 664 } 665 666 static void *c_start(struct seq_file *m, loff_t *pos) 667 { 668 /* 669 * Callback returns cpu-id to iterator for show routine, NULL to stop. 670 * However since NULL is also a valid cpu-id (0), we use a round-about 671 * way to pass it w/o having to kmalloc/free a 2 byte string. 672 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. 673 */ 674 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; 675 } 676 677 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 678 { 679 ++*pos; 680 return c_start(m, pos); 681 } 682 683 static void c_stop(struct seq_file *m, void *v) 684 { 685 } 686 687 const struct seq_operations cpuinfo_op = { 688 .start = c_start, 689 .next = c_next, 690 .stop = c_stop, 691 .show = show_cpuinfo 692 }; 693 694 static DEFINE_PER_CPU(struct cpu, cpu_topology); 695 696 static int __init topology_init(void) 697 { 698 int cpu; 699 700 for_each_present_cpu(cpu) 701 register_cpu(&per_cpu(cpu_topology, cpu), cpu); 702 703 return 0; 704 } 705 706 subsys_initcall(topology_init); 707