1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2bf90e1eaSVineet Gupta/* 3bf90e1eaSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4bf90e1eaSVineet Gupta * 5bf90e1eaSVineet Gupta * Vineetg: Aug 2009 6bf90e1eaSVineet Gupta * -Moved core context switch macro out of entry.S into this file. 7bf90e1eaSVineet Gupta * -This is the more "natural" hand written assembler 8bf90e1eaSVineet Gupta */ 9bf90e1eaSVineet Gupta 10ba25915fSVineet Gupta#include <linux/linkage.h> 11bf90e1eaSVineet Gupta#include <asm/entry.h> /* For the SAVE_* macros */ 12bf90e1eaSVineet Gupta#include <asm/asm-offsets.h> 13bf90e1eaSVineet Gupta 14b060b7d0SVineet Gupta; IN 15b060b7d0SVineet Gupta; - r0: prev task (also current) 16b060b7d0SVineet Gupta; - r1: next task 17b060b7d0SVineet Gupta; OUT 18b060b7d0SVineet Gupta; - r0: prev task (so r0 not touched) 19bf90e1eaSVineet Gupta 20bf90e1eaSVineet Gupta .section .sched.text,"ax",@progbits 21b060b7d0SVineet GuptaENTRY_CFI(__switch_to) 22bf90e1eaSVineet Gupta 23b060b7d0SVineet Gupta /* save kernel stack frame regs of @prev task */ 24b060b7d0SVineet Gupta push blink 25b060b7d0SVineet Gupta CFI_DEF_CFA_OFFSET 4 26b060b7d0SVineet Gupta CFI_OFFSET r31, -4 27b060b7d0SVineet Gupta 28b060b7d0SVineet Gupta push fp 29b060b7d0SVineet Gupta CFI_DEF_CFA_OFFSET 8 30b060b7d0SVineet Gupta CFI_OFFSET r27, -8 31b060b7d0SVineet Gupta 32b060b7d0SVineet Gupta mov fp, sp 33b060b7d0SVineet Gupta CFI_DEF_CFA_REGISTER r27 34b060b7d0SVineet Gupta 35b060b7d0SVineet Gupta /* kernel mode callee regs of @prev */ 36bf90e1eaSVineet Gupta SAVE_CALLEE_SAVED_KERNEL 37bf90e1eaSVineet Gupta 38*fd476197SVineet Gupta /* 39*fd476197SVineet Gupta * save final SP to @prev->thread_info.ksp 40*fd476197SVineet Gupta * @prev is "current" so thread_info derived from SP 41*fd476197SVineet Gupta */ 42*fd476197SVineet Gupta GET_CURR_THR_INFO_FROM_SP r10 43*fd476197SVineet Gupta st sp, [r10, THREAD_INFO_KSP] 44*fd476197SVineet Gupta 45b060b7d0SVineet Gupta /* update @next in _current_task[] and GP register caching it */ 46b060b7d0SVineet Gupta SET_CURR_TASK_ON_CPU r1, r10 47bf90e1eaSVineet Gupta 48*fd476197SVineet Gupta /* load SP from @next->thread_info.ksp */ 49*fd476197SVineet Gupta ld r10, [r1, TASK_THREAD_INFO] 50*fd476197SVineet Gupta ld sp, [r10, THREAD_INFO_KSP] 51bf90e1eaSVineet Gupta 52b060b7d0SVineet Gupta /* restore callee regs, stack frame regs of @next */ 53bf90e1eaSVineet Gupta RESTORE_CALLEE_SAVED_KERNEL 54bf90e1eaSVineet Gupta 55b060b7d0SVineet Gupta pop fp 56b060b7d0SVineet Gupta CFI_RESTORE r27 57b060b7d0SVineet Gupta CFI_DEF_CFA r28, 4 58b060b7d0SVineet Gupta 59b060b7d0SVineet Gupta pop blink 60b060b7d0SVineet Gupta CFI_RESTORE r31 61b060b7d0SVineet Gupta CFI_DEF_CFA_OFFSET 0 62b060b7d0SVineet Gupta 63b060b7d0SVineet Gupta j [blink] 6486effd0dSVineet GuptaEND_CFI(__switch_to) 65