1*d524dac9SGrant Likely* Power Management Controller 2*d524dac9SGrant Likely 3*d524dac9SGrant LikelyProperties: 4*d524dac9SGrant Likely- compatible: "fsl,<chip>-pmc". 5*d524dac9SGrant Likely 6*d524dac9SGrant Likely "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 7*d524dac9SGrant Likely compatible. "fsl,mpc8313-pmc" should also be listed for any chip 8*d524dac9SGrant Likely whose PMC is compatible, and implies deep-sleep capability. 9*d524dac9SGrant Likely 10*d524dac9SGrant Likely "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 11*d524dac9SGrant Likely compatible. "fsl,mpc8536-pmc" should also be listed for any chip 12*d524dac9SGrant Likely whose PMC is compatible, and implies deep-sleep capability. 13*d524dac9SGrant Likely 14*d524dac9SGrant Likely "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 15*d524dac9SGrant Likely compatible; all statements below that apply to "fsl,mpc8548-pmc" also 16*d524dac9SGrant Likely apply to "fsl,mpc8641d-pmc". 17*d524dac9SGrant Likely 18*d524dac9SGrant Likely Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 19*d524dac9SGrant Likely bit assignments are indicated via the sleep specifier in each device's 20*d524dac9SGrant Likely sleep property. 21*d524dac9SGrant Likely 22*d524dac9SGrant Likely- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource 23*d524dac9SGrant Likely is the PMC block, and the second resource is the Clock Configuration 24*d524dac9SGrant Likely block. 25*d524dac9SGrant Likely 26*d524dac9SGrant Likely For devices compatible with "fsl,mpc8548-pmc", the first resource 27*d524dac9SGrant Likely is a 32-byte block beginning with DEVDISR. 28*d524dac9SGrant Likely 29*d524dac9SGrant Likely- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first 30*d524dac9SGrant Likely resource is the PMC block interrupt. 31*d524dac9SGrant Likely 32*d524dac9SGrant Likely- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, 33*d524dac9SGrant Likely this is a phandle to an "fsl,gtm" node on which timer 4 can be used as 34*d524dac9SGrant Likely a wakeup source from deep sleep. 35*d524dac9SGrant Likely 36*d524dac9SGrant LikelySleep specifiers: 37*d524dac9SGrant Likely 38*d524dac9SGrant Likely fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit 39*d524dac9SGrant Likely that is set in the cell, the corresponding bit in SCCR will be saved 40*d524dac9SGrant Likely and cleared on suspend, and restored on resume. This sleep controller 41*d524dac9SGrant Likely supports disabling and resuming devices at any time. 42*d524dac9SGrant Likely 43*d524dac9SGrant Likely fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of 44*d524dac9SGrant Likely which will be ORed into PMCDR upon suspend, and cleared from PMCDR 45*d524dac9SGrant Likely upon resume. The first two cells are as described for fsl,mpc8578-pmc. 46*d524dac9SGrant Likely This sleep controller only supports disabling devices during system 47*d524dac9SGrant Likely sleep, or permanently. 48*d524dac9SGrant Likely 49*d524dac9SGrant Likely fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the 50*d524dac9SGrant Likely first of which will be ORed into DEVDISR (and the second into 51*d524dac9SGrant Likely DEVDISR2, if present -- this cell should be zero or absent if the 52*d524dac9SGrant Likely hardware does not have DEVDISR2) upon a request for permanent device 53*d524dac9SGrant Likely disabling. This sleep controller does not support configuring devices 54*d524dac9SGrant Likely to disable during system sleep (unless supported by another compatible 55*d524dac9SGrant Likely match), or dynamically. 56*d524dac9SGrant Likely 57*d524dac9SGrant LikelyExample: 58*d524dac9SGrant Likely 59*d524dac9SGrant Likely power@b00 { 60*d524dac9SGrant Likely compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 61*d524dac9SGrant Likely reg = <0xb00 0x100 0xa00 0x100>; 62*d524dac9SGrant Likely interrupts = <80 8>; 63*d524dac9SGrant Likely }; 64