1*52052875SStuart Yoder===================================================================== 2*52052875SStuart YoderFreescale MPIC Interrupt Controller Node 3*52052875SStuart YoderCopyright (C) 2010,2011 Freescale Semiconductor Inc. 4*52052875SStuart Yoder===================================================================== 5d524dac9SGrant Likely 6*52052875SStuart YoderThe Freescale MPIC interrupt controller is found on all PowerQUICC 7*52052875SStuart Yoderand QorIQ processors and is compatible with the Open PIC. The 8*52052875SStuart Yodernotable difference from Open PIC binding is the addition of 2 9*52052875SStuart Yoderadditional cells in the interrupt specifier defining interrupt type 10*52052875SStuart Yoderinformation. 11d524dac9SGrant Likely 12*52052875SStuart YoderPROPERTIES 13d524dac9SGrant Likely 14*52052875SStuart Yoder - compatible 15*52052875SStuart Yoder Usage: required 16*52052875SStuart Yoder Value type: <string> 17*52052875SStuart Yoder Definition: Shall include "fsl,mpic". Freescale MPIC 18*52052875SStuart Yoder controllers compatible with this binding have Block 19*52052875SStuart Yoder Revision Registers BRR1 and BRR2 at offset 0x0 and 20*52052875SStuart Yoder 0x10 in the MPIC. 21d524dac9SGrant Likely 22*52052875SStuart Yoder - reg 23*52052875SStuart Yoder Usage: required 24*52052875SStuart Yoder Value type: <prop-encoded-array> 25*52052875SStuart Yoder Definition: A standard property. Specifies the physical 26*52052875SStuart Yoder offset and length of the device's registers within the 27*52052875SStuart Yoder CCSR address space. 28d524dac9SGrant Likely 29*52052875SStuart Yoder - interrupt-controller 30*52052875SStuart Yoder Usage: required 31*52052875SStuart Yoder Value type: <empty> 32*52052875SStuart Yoder Definition: Specifies that this node is an interrupt 33*52052875SStuart Yoder controller 34d524dac9SGrant Likely 35*52052875SStuart Yoder - #interrupt-cells 36*52052875SStuart Yoder Usage: required 37*52052875SStuart Yoder Value type: <u32> 38*52052875SStuart Yoder Definition: Shall be 2 or 4. A value of 2 means that interrupt 39*52052875SStuart Yoder specifiers do not contain the interrupt-type or type-specific 40*52052875SStuart Yoder information cells. 41*52052875SStuart Yoder 42*52052875SStuart Yoder - #address-cells 43*52052875SStuart Yoder Usage: required 44*52052875SStuart Yoder Value type: <u32> 45*52052875SStuart Yoder Definition: Shall be 0. 46*52052875SStuart Yoder 47*52052875SStuart Yoder - pic-no-reset 48*52052875SStuart Yoder Usage: optional 49*52052875SStuart Yoder Value type: <empty> 50*52052875SStuart Yoder Definition: The presence of this property specifies that the 51*52052875SStuart Yoder MPIC must not be reset by the client program, and that 52*52052875SStuart Yoder the boot program has initialized all interrupt source 53*52052875SStuart Yoder configuration registers to a sane state-- masked or 54*52052875SStuart Yoder directed at other cores. This ensures that the client 55*52052875SStuart Yoder program will not receive interrupts for sources not belonging 56*52052875SStuart Yoder to the client. The presence of this property also mandates 57*52052875SStuart Yoder that any initialization related to interrupt sources shall 58*52052875SStuart Yoder be limited to sources explicitly referenced in the device tree. 59*52052875SStuart Yoder 60*52052875SStuart YoderINTERRUPT SPECIFIER DEFINITION 61*52052875SStuart Yoder 62*52052875SStuart Yoder Interrupt specifiers consists of 4 cells encoded as 63*52052875SStuart Yoder follows: 64*52052875SStuart Yoder 65*52052875SStuart Yoder <1st-cell> interrupt-number 66*52052875SStuart Yoder 67*52052875SStuart Yoder Identifies the interrupt source. The meaning 68*52052875SStuart Yoder depends on the type of interrupt. 69*52052875SStuart Yoder 70*52052875SStuart Yoder Note: If the interrupt-type cell is undefined 71*52052875SStuart Yoder (i.e. #interrupt-cells = 2), this cell 72*52052875SStuart Yoder should be interpreted the same as for 73*52052875SStuart Yoder interrupt-type 0-- i.e. an external or 74*52052875SStuart Yoder normal SoC device interrupt. 75*52052875SStuart Yoder 76*52052875SStuart Yoder <2nd-cell> level-sense information, encoded as follows: 77*52052875SStuart Yoder 0 = low-to-high edge triggered 78*52052875SStuart Yoder 1 = active low level-sensitive 79*52052875SStuart Yoder 2 = active high level-sensitive 80*52052875SStuart Yoder 3 = high-to-low edge triggered 81*52052875SStuart Yoder 82*52052875SStuart Yoder <3rd-cell> interrupt-type 83*52052875SStuart Yoder 84*52052875SStuart Yoder The following types are supported: 85*52052875SStuart Yoder 86*52052875SStuart Yoder 0 = external or normal SoC device interrupt 87*52052875SStuart Yoder 88*52052875SStuart Yoder The interrupt-number cell contains 89*52052875SStuart Yoder the SoC device interrupt number. The 90*52052875SStuart Yoder type-specific cell is undefined. The 91*52052875SStuart Yoder interrupt-number is derived from the 92*52052875SStuart Yoder MPIC a block of registers referred to as 93*52052875SStuart Yoder the "Interrupt Source Configuration Registers". 94*52052875SStuart Yoder Each source has 32-bytes of registers 95*52052875SStuart Yoder (vector/priority and destination) in this 96*52052875SStuart Yoder region. So interrupt 0 is at offset 0x0, 97*52052875SStuart Yoder interrupt 1 is at offset 0x20, and so on. 98*52052875SStuart Yoder 99*52052875SStuart Yoder 1 = error interrupt 100*52052875SStuart Yoder 101*52052875SStuart Yoder The interrupt-number cell contains 102*52052875SStuart Yoder the SoC device interrupt number for 103*52052875SStuart Yoder the error interrupt. The type-specific 104*52052875SStuart Yoder cell identifies the specific error 105*52052875SStuart Yoder interrupt number. 106*52052875SStuart Yoder 107*52052875SStuart Yoder 2 = MPIC inter-processor interrupt (IPI) 108*52052875SStuart Yoder 109*52052875SStuart Yoder The interrupt-number cell identifies 110*52052875SStuart Yoder the MPIC IPI number. The type-specific 111*52052875SStuart Yoder cell is undefined. 112*52052875SStuart Yoder 113*52052875SStuart Yoder 3 = MPIC timer interrupt 114*52052875SStuart Yoder 115*52052875SStuart Yoder The interrupt-number cell identifies 116*52052875SStuart Yoder the MPIC timer number. The type-specific 117*52052875SStuart Yoder cell is undefined. 118*52052875SStuart Yoder 119*52052875SStuart Yoder <4th-cell> type-specific information 120*52052875SStuart Yoder 121*52052875SStuart Yoder The type-specific cell is encoded as follows: 122*52052875SStuart Yoder 123*52052875SStuart Yoder - For interrupt-type 1 (error interrupt), 124*52052875SStuart Yoder the type-specific cell contains the 125*52052875SStuart Yoder bit number of the error interrupt in the 126*52052875SStuart Yoder Error Interrupt Summary Register. 127*52052875SStuart Yoder 128*52052875SStuart YoderEXAMPLE 1 129*52052875SStuart Yoder /* 130*52052875SStuart Yoder * mpic interrupt controller with 4 cells per specifier 131*52052875SStuart Yoder */ 132*52052875SStuart Yoder mpic: pic@40000 { 133*52052875SStuart Yoder compatible = "fsl,mpic"; 134*52052875SStuart Yoder interrupt-controller; 135*52052875SStuart Yoder #interrupt-cells = <4>; 136*52052875SStuart Yoder #address-cells = <0>; 137*52052875SStuart Yoder reg = <0x40000 0x40000>; 138*52052875SStuart Yoder }; 139*52052875SStuart Yoder 140*52052875SStuart YoderEXAMPLE 2 141*52052875SStuart Yoder /* 142*52052875SStuart Yoder * The MPC8544 I2C controller node has an internal 143*52052875SStuart Yoder * interrupt number of 27. As per the reference manual 144*52052875SStuart Yoder * this corresponds to interrupt source configuration 145*52052875SStuart Yoder * registers at 0x5_0560. 146*52052875SStuart Yoder * 147*52052875SStuart Yoder * The interrupt source configuration registers begin 148*52052875SStuart Yoder * at 0x5_0000. 149*52052875SStuart Yoder * 150*52052875SStuart Yoder * To compute the interrupt specifier interrupt number 151*52052875SStuart Yoder * 152*52052875SStuart Yoder * 0x560 >> 5 = 43 153*52052875SStuart Yoder * 154*52052875SStuart Yoder * The interrupt source configuration registers begin 155*52052875SStuart Yoder * at 0x5_0000, and so the i2c vector/priority registers 156*52052875SStuart Yoder * are at 0x5_0560. 157*52052875SStuart Yoder */ 158*52052875SStuart Yoder i2c@3000 { 159*52052875SStuart Yoder #address-cells = <1>; 160*52052875SStuart Yoder #size-cells = <0>; 161*52052875SStuart Yoder cell-index = <0>; 162*52052875SStuart Yoder compatible = "fsl-i2c"; 163*52052875SStuart Yoder reg = <0x3000 0x100>; 164*52052875SStuart Yoder interrupts = <43 2>; 165*52052875SStuart Yoder interrupt-parent = <&mpic>; 166*52052875SStuart Yoder dfsrr; 167*52052875SStuart Yoder }; 168*52052875SStuart Yoder 169*52052875SStuart Yoder 170*52052875SStuart YoderEXAMPLE 3 171*52052875SStuart Yoder /* 172*52052875SStuart Yoder * Definition of a node defining the 4 173*52052875SStuart Yoder * MPIC IPI interrupts. Note the interrupt 174*52052875SStuart Yoder * type of 2. 175*52052875SStuart Yoder */ 176*52052875SStuart Yoder ipi@410a0 { 177*52052875SStuart Yoder compatible = "fsl,mpic-ipi"; 178*52052875SStuart Yoder reg = <0x40040 0x10>; 179*52052875SStuart Yoder interrupts = <0 0 2 0 180*52052875SStuart Yoder 1 0 2 0 181*52052875SStuart Yoder 2 0 2 0 182*52052875SStuart Yoder 3 0 2 0>; 183*52052875SStuart Yoder }; 184*52052875SStuart Yoder 185*52052875SStuart YoderEXAMPLE 4 186*52052875SStuart Yoder /* 187*52052875SStuart Yoder * Definition of a node defining the MPIC 188*52052875SStuart Yoder * global timers. Note the interrupt 189*52052875SStuart Yoder * type of 3. 190*52052875SStuart Yoder */ 191*52052875SStuart Yoder timer0: timer@41100 { 192*52052875SStuart Yoder compatible = "fsl,mpic-global-timer"; 193*52052875SStuart Yoder reg = <0x41100 0x100>; 194*52052875SStuart Yoder interrupts = <0 0 3 0 195*52052875SStuart Yoder 1 0 3 0 196*52052875SStuart Yoder 2 0 3 0 197*52052875SStuart Yoder 3 0 3 0>; 198*52052875SStuart Yoder }; 199*52052875SStuart Yoder 200*52052875SStuart YoderEXAMPLE 5 201*52052875SStuart Yoder /* 202*52052875SStuart Yoder * Definition of an error interrupt (interupt type 1). 203*52052875SStuart Yoder * SoC interrupt number is 16 and the specific error 204*52052875SStuart Yoder * interrupt bit in the error interrupt summary register 205*52052875SStuart Yoder * is 23. 206*52052875SStuart Yoder */ 207*52052875SStuart Yoder memory-controller@8000 { 208*52052875SStuart Yoder compatible = "fsl,p4080-memory-controller"; 209*52052875SStuart Yoder reg = <0x8000 0x1000>; 210*52052875SStuart Yoder interrupts = <16 2 1 23>; 211*52052875SStuart Yoder }; 212