15398b2faSGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 25398b2faSGeert Uytterhoeven%YAML 1.2 35398b2faSGeert Uytterhoeven--- 45398b2faSGeert Uytterhoeven$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# 55398b2faSGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml# 65398b2faSGeert Uytterhoeven 75398b2faSGeert Uytterhoeventitle: Renesas RZ/A1 combined Pin and GPIO controller 85398b2faSGeert Uytterhoeven 95398b2faSGeert Uytterhoevenmaintainers: 105398b2faSGeert Uytterhoeven - Jacopo Mondi <jacopo+renesas@jmondi.org> 115398b2faSGeert Uytterhoeven - Geert Uytterhoeven <geert+renesas@glider.be> 125398b2faSGeert Uytterhoeven 135398b2faSGeert Uytterhoevendescription: 145398b2faSGeert Uytterhoeven The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO 155398b2faSGeert Uytterhoeven controller, named "Ports" in the hardware reference manual. 165398b2faSGeert Uytterhoeven Pin multiplexing and GPIO configuration is performed on a per-pin basis 175398b2faSGeert Uytterhoeven writing configuration values to per-port register sets. 185398b2faSGeert Uytterhoeven Each "port" features up to 16 pins, each of them configurable for GPIO 195398b2faSGeert Uytterhoeven function (port mode) or in alternate function mode. 205398b2faSGeert Uytterhoeven Up to 8 different alternate function modes exist for each single pin. 215398b2faSGeert Uytterhoeven 225398b2faSGeert Uytterhoevenproperties: 235398b2faSGeert Uytterhoeven compatible: 245398b2faSGeert Uytterhoeven oneOf: 255398b2faSGeert Uytterhoeven - const: renesas,r7s72100-ports # RZ/A1H 265398b2faSGeert Uytterhoeven - items: 275398b2faSGeert Uytterhoeven - const: renesas,r7s72101-ports # RZ/A1M 285398b2faSGeert Uytterhoeven - const: renesas,r7s72100-ports # fallback 295398b2faSGeert Uytterhoeven - const: renesas,r7s72102-ports # RZ/A1L 305398b2faSGeert Uytterhoeven 315398b2faSGeert Uytterhoeven reg: 325398b2faSGeert Uytterhoeven maxItems: 1 335398b2faSGeert Uytterhoeven 34c09acbc4SRafał MiłeckiallOf: 35*49cd1dd1SRob Herring - $ref: pinctrl.yaml# 36c09acbc4SRafał Miłecki 375398b2faSGeert Uytterhoevenrequired: 385398b2faSGeert Uytterhoeven - compatible 395398b2faSGeert Uytterhoeven - reg 405398b2faSGeert Uytterhoeven 415398b2faSGeert UytterhoevenpatternProperties: 425398b2faSGeert Uytterhoeven "^gpio-[0-9]*$": 435398b2faSGeert Uytterhoeven type: object 449194e0f8SRob Herring additionalProperties: false 455398b2faSGeert Uytterhoeven 465398b2faSGeert Uytterhoeven description: 475398b2faSGeert Uytterhoeven Each port of the r7s72100 pin controller hardware is itself a GPIO 485398b2faSGeert Uytterhoeven controller. 495398b2faSGeert Uytterhoeven Different SoCs have different numbers of available pins per port, but 505398b2faSGeert Uytterhoeven generally speaking, each of them can be configured in GPIO ("port") mode 515398b2faSGeert Uytterhoeven on this hardware. 525398b2faSGeert Uytterhoeven Describe GPIO controllers using sub-nodes with the following properties. 535398b2faSGeert Uytterhoeven 545398b2faSGeert Uytterhoeven properties: 555398b2faSGeert Uytterhoeven gpio-controller: true 565398b2faSGeert Uytterhoeven 575398b2faSGeert Uytterhoeven '#gpio-cells': 585398b2faSGeert Uytterhoeven const: 2 595398b2faSGeert Uytterhoeven 605398b2faSGeert Uytterhoeven gpio-ranges: 615398b2faSGeert Uytterhoeven maxItems: 1 625398b2faSGeert Uytterhoeven 635398b2faSGeert Uytterhoeven required: 645398b2faSGeert Uytterhoeven - gpio-controller 655398b2faSGeert Uytterhoeven - '#gpio-cells' 665398b2faSGeert Uytterhoeven - gpio-ranges 675398b2faSGeert Uytterhoeven 685398b2faSGeert Uytterhoeven 695398b2faSGeert UytterhoevenadditionalProperties: 705398b2faSGeert Uytterhoeven anyOf: 715398b2faSGeert Uytterhoeven - type: object 725398b2faSGeert Uytterhoeven allOf: 735398b2faSGeert Uytterhoeven - $ref: pincfg-node.yaml# 745398b2faSGeert Uytterhoeven - $ref: pinmux-node.yaml# 755398b2faSGeert Uytterhoeven 765398b2faSGeert Uytterhoeven description: 775398b2faSGeert Uytterhoeven A pin multiplexing sub-node describes how to configure a set of (or a 785398b2faSGeert Uytterhoeven single) pin in some desired alternate function mode. 795398b2faSGeert Uytterhoeven A single sub-node may define several pin configurations. 805398b2faSGeert Uytterhoeven A few alternate function require special pin configuration flags to be 815398b2faSGeert Uytterhoeven supplied along with the alternate function configuration number. 825398b2faSGeert Uytterhoeven The hardware reference manual specifies when a pin function requires 835398b2faSGeert Uytterhoeven "software IO driven" mode to be specified. To do so use the generic 845398b2faSGeert Uytterhoeven properties from the <include/linux/pinctrl/pinconf_generic.h> header 855398b2faSGeert Uytterhoeven file to instruct the pin controller to perform the desired pin 865398b2faSGeert Uytterhoeven configuration operation. 875398b2faSGeert Uytterhoeven The hardware reference manual specifies when a pin has to be configured 885398b2faSGeert Uytterhoeven to work in bi-directional mode and when the IO direction has to be 895398b2faSGeert Uytterhoeven specified by software. Bi-directional pins must be managed by the pin 905398b2faSGeert Uytterhoeven controller driver internally, while software driven IO direction has to 915398b2faSGeert Uytterhoeven be explicitly selected when multiple options are available. 925398b2faSGeert Uytterhoeven 935398b2faSGeert Uytterhoeven properties: 945398b2faSGeert Uytterhoeven pinmux: 955398b2faSGeert Uytterhoeven description: | 965398b2faSGeert Uytterhoeven Integer array representing pin number and pin multiplexing 975398b2faSGeert Uytterhoeven configuration. 985398b2faSGeert Uytterhoeven When a pin has to be configured in alternate function mode, use 995398b2faSGeert Uytterhoeven this property to identify the pin by its global index, and provide 1005398b2faSGeert Uytterhoeven its alternate function configuration number along with it. 1015398b2faSGeert Uytterhoeven When multiple pins are required to be configured as part of the 1025398b2faSGeert Uytterhoeven same alternate function they shall be specified as members of the 1035398b2faSGeert Uytterhoeven same argument list of a single "pinmux" property. 1045398b2faSGeert Uytterhoeven Helper macros to ease assembling the pin index from its position 1055398b2faSGeert Uytterhoeven (port where it sits on and pin number) and alternate function 1065398b2faSGeert Uytterhoeven identifier are provided by the pin controller header file at: 1075398b2faSGeert Uytterhoeven <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> 1085398b2faSGeert Uytterhoeven Integers values in "pinmux" argument list are assembled as: 1095398b2faSGeert Uytterhoeven ((PORT * 16 + PIN) | MUX_FUNC << 16) 1105398b2faSGeert Uytterhoeven 1115398b2faSGeert Uytterhoeven input-enable: true 1125398b2faSGeert Uytterhoeven output-enable: true 1135398b2faSGeert Uytterhoeven 1145398b2faSGeert Uytterhoeven required: 1155398b2faSGeert Uytterhoeven - pinmux 1165398b2faSGeert Uytterhoeven 1175398b2faSGeert Uytterhoeven additionalProperties: false 1185398b2faSGeert Uytterhoeven 1195398b2faSGeert Uytterhoeven - type: object 1205398b2faSGeert Uytterhoeven additionalProperties: 1215398b2faSGeert Uytterhoeven $ref: "#/additionalProperties/anyOf/0" 1225398b2faSGeert Uytterhoeven 1235398b2faSGeert Uytterhoevenexamples: 1245398b2faSGeert Uytterhoeven - | 1255398b2faSGeert Uytterhoeven #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 1265398b2faSGeert Uytterhoeven pinctrl: pinctrl@fcfe3000 { 1275398b2faSGeert Uytterhoeven compatible = "renesas,r7s72100-ports"; 1285398b2faSGeert Uytterhoeven 1295398b2faSGeert Uytterhoeven reg = <0xfcfe3000 0x4230>; 1305398b2faSGeert Uytterhoeven 1315398b2faSGeert Uytterhoeven /* 1325398b2faSGeert Uytterhoeven * A GPIO controller node, controlling 16 pins indexed from 0. 1335398b2faSGeert Uytterhoeven * The GPIO controller base in the global pin indexing space is pin 1345398b2faSGeert Uytterhoeven * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] 1355398b2faSGeert Uytterhoeven * in the global pin indexing space. 1365398b2faSGeert Uytterhoeven */ 1375398b2faSGeert Uytterhoeven port3: gpio-3 { 1385398b2faSGeert Uytterhoeven gpio-controller; 1395398b2faSGeert Uytterhoeven #gpio-cells = <2>; 1405398b2faSGeert Uytterhoeven gpio-ranges = <&pinctrl 0 48 16>; 1415398b2faSGeert Uytterhoeven }; 1425398b2faSGeert Uytterhoeven 1435398b2faSGeert Uytterhoeven /* 1445398b2faSGeert Uytterhoeven * A serial communication interface with a TX output pin and an RX 1455398b2faSGeert Uytterhoeven * input pin. 1465398b2faSGeert Uytterhoeven * Pin #0 on port #3 is configured as alternate function #6. 1475398b2faSGeert Uytterhoeven * Pin #2 on port #3 is configured as alternate function #4. 1485398b2faSGeert Uytterhoeven */ 1495398b2faSGeert Uytterhoeven scif2_pins: serial2 { 1505398b2faSGeert Uytterhoeven pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 1515398b2faSGeert Uytterhoeven }; 1525398b2faSGeert Uytterhoeven 1535398b2faSGeert Uytterhoeven 1545398b2faSGeert Uytterhoeven /* 1555398b2faSGeert Uytterhoeven * I2c master: both SDA and SCL pins need bi-directional operations 1565398b2faSGeert Uytterhoeven * Pin #4 on port #1 is configured as alternate function #1. 1575398b2faSGeert Uytterhoeven * Pin #5 on port #1 is configured as alternate function #1. 1585398b2faSGeert Uytterhoeven * Both need to work in bi-directional mode, the driver must manage 1595398b2faSGeert Uytterhoeven * this internally. 1605398b2faSGeert Uytterhoeven */ 1615398b2faSGeert Uytterhoeven i2c2_pins: i2c2 { 1625398b2faSGeert Uytterhoeven pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; 1635398b2faSGeert Uytterhoeven }; 1645398b2faSGeert Uytterhoeven 1655398b2faSGeert Uytterhoeven 1665398b2faSGeert Uytterhoeven /* 1675398b2faSGeert Uytterhoeven * Multi-function timer input and output compare pins. 1685398b2faSGeert Uytterhoeven */ 1695398b2faSGeert Uytterhoeven tioc0_pins: tioc0 { 1705398b2faSGeert Uytterhoeven /* 1715398b2faSGeert Uytterhoeven * Configure TIOC0A as software driven input 1725398b2faSGeert Uytterhoeven * Pin #0 on port #4 is configured as alternate function #2 1735398b2faSGeert Uytterhoeven * with IO direction specified by software as input. 1745398b2faSGeert Uytterhoeven */ 1755398b2faSGeert Uytterhoeven tioc0_input_pins { 1765398b2faSGeert Uytterhoeven pinmux = <RZA1_PINMUX(4, 0, 2)>; 1775398b2faSGeert Uytterhoeven input-enable; 1785398b2faSGeert Uytterhoeven }; 1795398b2faSGeert Uytterhoeven 1805398b2faSGeert Uytterhoeven /* 1815398b2faSGeert Uytterhoeven * Configure TIOC0B as software driven output 1825398b2faSGeert Uytterhoeven * Pin #1 on port #4 is configured as alternate function #1 1835398b2faSGeert Uytterhoeven * with IO direction specified by software as output. 1845398b2faSGeert Uytterhoeven */ 1855398b2faSGeert Uytterhoeven tioc0_output_pins { 1865398b2faSGeert Uytterhoeven pinmux = <RZA1_PINMUX(4, 1, 1)>; 1875398b2faSGeert Uytterhoeven output-enable; 1885398b2faSGeert Uytterhoeven }; 1895398b2faSGeert Uytterhoeven }; 1905398b2faSGeert Uytterhoeven }; 191