xref: /linux/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml (revision 5398b2fa464722a3bb3cf4c264a19ac765974d98)
1*5398b2faSGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*5398b2faSGeert Uytterhoeven%YAML 1.2
3*5398b2faSGeert Uytterhoeven---
4*5398b2faSGeert Uytterhoeven$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5*5398b2faSGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml#
6*5398b2faSGeert Uytterhoeven
7*5398b2faSGeert Uytterhoeventitle: Renesas RZ/A1 combined Pin and GPIO controller
8*5398b2faSGeert Uytterhoeven
9*5398b2faSGeert Uytterhoevenmaintainers:
10*5398b2faSGeert Uytterhoeven  - Jacopo Mondi <jacopo+renesas@jmondi.org>
11*5398b2faSGeert Uytterhoeven  - Geert Uytterhoeven <geert+renesas@glider.be>
12*5398b2faSGeert Uytterhoeven
13*5398b2faSGeert Uytterhoevendescription:
14*5398b2faSGeert Uytterhoeven  The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
15*5398b2faSGeert Uytterhoeven  controller, named "Ports" in the hardware reference manual.
16*5398b2faSGeert Uytterhoeven  Pin multiplexing and GPIO configuration is performed on a per-pin basis
17*5398b2faSGeert Uytterhoeven  writing configuration values to per-port register sets.
18*5398b2faSGeert Uytterhoeven  Each "port" features up to 16 pins, each of them configurable for GPIO
19*5398b2faSGeert Uytterhoeven  function (port mode) or in alternate function mode.
20*5398b2faSGeert Uytterhoeven  Up to 8 different alternate function modes exist for each single pin.
21*5398b2faSGeert Uytterhoeven
22*5398b2faSGeert Uytterhoevenproperties:
23*5398b2faSGeert Uytterhoeven  compatible:
24*5398b2faSGeert Uytterhoeven    oneOf:
25*5398b2faSGeert Uytterhoeven      - const: renesas,r7s72100-ports     # RZ/A1H
26*5398b2faSGeert Uytterhoeven      - items:
27*5398b2faSGeert Uytterhoeven          - const: renesas,r7s72101-ports # RZ/A1M
28*5398b2faSGeert Uytterhoeven          - const: renesas,r7s72100-ports # fallback
29*5398b2faSGeert Uytterhoeven      - const: renesas,r7s72102-ports     # RZ/A1L
30*5398b2faSGeert Uytterhoeven
31*5398b2faSGeert Uytterhoeven  reg:
32*5398b2faSGeert Uytterhoeven    maxItems: 1
33*5398b2faSGeert Uytterhoeven
34*5398b2faSGeert Uytterhoevenrequired:
35*5398b2faSGeert Uytterhoeven  - compatible
36*5398b2faSGeert Uytterhoeven  - reg
37*5398b2faSGeert Uytterhoeven
38*5398b2faSGeert UytterhoevenpatternProperties:
39*5398b2faSGeert Uytterhoeven  "^gpio-[0-9]*$":
40*5398b2faSGeert Uytterhoeven    type: object
41*5398b2faSGeert Uytterhoeven
42*5398b2faSGeert Uytterhoeven    description:
43*5398b2faSGeert Uytterhoeven      Each port of the r7s72100 pin controller hardware is itself a GPIO
44*5398b2faSGeert Uytterhoeven      controller.
45*5398b2faSGeert Uytterhoeven      Different SoCs have different numbers of available pins per port, but
46*5398b2faSGeert Uytterhoeven      generally speaking, each of them can be configured in GPIO ("port") mode
47*5398b2faSGeert Uytterhoeven      on this hardware.
48*5398b2faSGeert Uytterhoeven      Describe GPIO controllers using sub-nodes with the following properties.
49*5398b2faSGeert Uytterhoeven
50*5398b2faSGeert Uytterhoeven    properties:
51*5398b2faSGeert Uytterhoeven      gpio-controller: true
52*5398b2faSGeert Uytterhoeven
53*5398b2faSGeert Uytterhoeven      '#gpio-cells':
54*5398b2faSGeert Uytterhoeven        const: 2
55*5398b2faSGeert Uytterhoeven
56*5398b2faSGeert Uytterhoeven      gpio-ranges:
57*5398b2faSGeert Uytterhoeven        maxItems: 1
58*5398b2faSGeert Uytterhoeven
59*5398b2faSGeert Uytterhoeven    required:
60*5398b2faSGeert Uytterhoeven      - gpio-controller
61*5398b2faSGeert Uytterhoeven      - '#gpio-cells'
62*5398b2faSGeert Uytterhoeven      - gpio-ranges
63*5398b2faSGeert Uytterhoeven
64*5398b2faSGeert Uytterhoeven
65*5398b2faSGeert UytterhoevenadditionalProperties:
66*5398b2faSGeert Uytterhoeven  anyOf:
67*5398b2faSGeert Uytterhoeven    - type: object
68*5398b2faSGeert Uytterhoeven      allOf:
69*5398b2faSGeert Uytterhoeven        - $ref: pincfg-node.yaml#
70*5398b2faSGeert Uytterhoeven        - $ref: pinmux-node.yaml#
71*5398b2faSGeert Uytterhoeven
72*5398b2faSGeert Uytterhoeven      description:
73*5398b2faSGeert Uytterhoeven        A pin multiplexing sub-node describes how to configure a set of (or a
74*5398b2faSGeert Uytterhoeven        single) pin in some desired alternate function mode.
75*5398b2faSGeert Uytterhoeven        A single sub-node may define several pin configurations.
76*5398b2faSGeert Uytterhoeven        A few alternate function require special pin configuration flags to be
77*5398b2faSGeert Uytterhoeven        supplied along with the alternate function configuration number.
78*5398b2faSGeert Uytterhoeven        The hardware reference manual specifies when a pin function requires
79*5398b2faSGeert Uytterhoeven        "software IO driven" mode to be specified. To do so use the generic
80*5398b2faSGeert Uytterhoeven        properties from the <include/linux/pinctrl/pinconf_generic.h> header
81*5398b2faSGeert Uytterhoeven        file to instruct the pin controller to perform the desired pin
82*5398b2faSGeert Uytterhoeven        configuration operation.
83*5398b2faSGeert Uytterhoeven        The hardware reference manual specifies when a pin has to be configured
84*5398b2faSGeert Uytterhoeven        to work in bi-directional mode and when the IO direction has to be
85*5398b2faSGeert Uytterhoeven        specified by software. Bi-directional pins must be managed by the pin
86*5398b2faSGeert Uytterhoeven        controller driver internally, while software driven IO direction has to
87*5398b2faSGeert Uytterhoeven        be explicitly selected when multiple options are available.
88*5398b2faSGeert Uytterhoeven
89*5398b2faSGeert Uytterhoeven      properties:
90*5398b2faSGeert Uytterhoeven        pinmux:
91*5398b2faSGeert Uytterhoeven          description: |
92*5398b2faSGeert Uytterhoeven            Integer array representing pin number and pin multiplexing
93*5398b2faSGeert Uytterhoeven            configuration.
94*5398b2faSGeert Uytterhoeven            When a pin has to be configured in alternate function mode, use
95*5398b2faSGeert Uytterhoeven            this property to identify the pin by its global index, and provide
96*5398b2faSGeert Uytterhoeven            its alternate function configuration number along with it.
97*5398b2faSGeert Uytterhoeven            When multiple pins are required to be configured as part of the
98*5398b2faSGeert Uytterhoeven            same alternate function they shall be specified as members of the
99*5398b2faSGeert Uytterhoeven            same argument list of a single "pinmux" property.
100*5398b2faSGeert Uytterhoeven            Helper macros to ease assembling the pin index from its position
101*5398b2faSGeert Uytterhoeven            (port where it sits on and pin number) and alternate function
102*5398b2faSGeert Uytterhoeven            identifier are provided by the pin controller header file at:
103*5398b2faSGeert Uytterhoeven            <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
104*5398b2faSGeert Uytterhoeven            Integers values in "pinmux" argument list are assembled as:
105*5398b2faSGeert Uytterhoeven            ((PORT * 16 + PIN) | MUX_FUNC << 16)
106*5398b2faSGeert Uytterhoeven
107*5398b2faSGeert Uytterhoeven        phandle: true
108*5398b2faSGeert Uytterhoeven        input-enable: true
109*5398b2faSGeert Uytterhoeven        output-enable: true
110*5398b2faSGeert Uytterhoeven
111*5398b2faSGeert Uytterhoeven      required:
112*5398b2faSGeert Uytterhoeven        - pinmux
113*5398b2faSGeert Uytterhoeven
114*5398b2faSGeert Uytterhoeven      additionalProperties: false
115*5398b2faSGeert Uytterhoeven
116*5398b2faSGeert Uytterhoeven    - type: object
117*5398b2faSGeert Uytterhoeven      properties:
118*5398b2faSGeert Uytterhoeven        phandle: true
119*5398b2faSGeert Uytterhoeven
120*5398b2faSGeert Uytterhoeven      additionalProperties:
121*5398b2faSGeert Uytterhoeven        $ref: "#/additionalProperties/anyOf/0"
122*5398b2faSGeert Uytterhoeven
123*5398b2faSGeert Uytterhoevenexamples:
124*5398b2faSGeert Uytterhoeven  - |
125*5398b2faSGeert Uytterhoeven    #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
126*5398b2faSGeert Uytterhoeven    pinctrl: pinctrl@fcfe3000 {
127*5398b2faSGeert Uytterhoeven            compatible = "renesas,r7s72100-ports";
128*5398b2faSGeert Uytterhoeven
129*5398b2faSGeert Uytterhoeven            reg = <0xfcfe3000 0x4230>;
130*5398b2faSGeert Uytterhoeven
131*5398b2faSGeert Uytterhoeven            /*
132*5398b2faSGeert Uytterhoeven             * A GPIO controller node, controlling 16 pins indexed from 0.
133*5398b2faSGeert Uytterhoeven             * The GPIO controller base in the global pin indexing space is pin
134*5398b2faSGeert Uytterhoeven             * 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
135*5398b2faSGeert Uytterhoeven             * in the global pin indexing space.
136*5398b2faSGeert Uytterhoeven             */
137*5398b2faSGeert Uytterhoeven            port3: gpio-3 {
138*5398b2faSGeert Uytterhoeven                    gpio-controller;
139*5398b2faSGeert Uytterhoeven                    #gpio-cells = <2>;
140*5398b2faSGeert Uytterhoeven                    gpio-ranges = <&pinctrl 0 48 16>;
141*5398b2faSGeert Uytterhoeven            };
142*5398b2faSGeert Uytterhoeven
143*5398b2faSGeert Uytterhoeven            /*
144*5398b2faSGeert Uytterhoeven             * A serial communication interface with a TX output pin and an RX
145*5398b2faSGeert Uytterhoeven             * input pin.
146*5398b2faSGeert Uytterhoeven             * Pin #0 on port #3 is configured as alternate function #6.
147*5398b2faSGeert Uytterhoeven             * Pin #2 on port #3 is configured as alternate function #4.
148*5398b2faSGeert Uytterhoeven             */
149*5398b2faSGeert Uytterhoeven            scif2_pins: serial2 {
150*5398b2faSGeert Uytterhoeven                    pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
151*5398b2faSGeert Uytterhoeven            };
152*5398b2faSGeert Uytterhoeven
153*5398b2faSGeert Uytterhoeven
154*5398b2faSGeert Uytterhoeven            /*
155*5398b2faSGeert Uytterhoeven             * I2c master: both SDA and SCL pins need bi-directional operations
156*5398b2faSGeert Uytterhoeven             * Pin #4 on port #1 is configured as alternate function #1.
157*5398b2faSGeert Uytterhoeven             * Pin #5 on port #1 is configured as alternate function #1.
158*5398b2faSGeert Uytterhoeven             * Both need to work in bi-directional mode, the driver must manage
159*5398b2faSGeert Uytterhoeven             * this internally.
160*5398b2faSGeert Uytterhoeven             */
161*5398b2faSGeert Uytterhoeven            i2c2_pins: i2c2 {
162*5398b2faSGeert Uytterhoeven                    pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
163*5398b2faSGeert Uytterhoeven            };
164*5398b2faSGeert Uytterhoeven
165*5398b2faSGeert Uytterhoeven
166*5398b2faSGeert Uytterhoeven            /*
167*5398b2faSGeert Uytterhoeven             * Multi-function timer input and output compare pins.
168*5398b2faSGeert Uytterhoeven             */
169*5398b2faSGeert Uytterhoeven            tioc0_pins: tioc0 {
170*5398b2faSGeert Uytterhoeven                    /*
171*5398b2faSGeert Uytterhoeven                     * Configure TIOC0A as software driven input
172*5398b2faSGeert Uytterhoeven                     * Pin #0 on port #4 is configured as alternate function #2
173*5398b2faSGeert Uytterhoeven                     * with IO direction specified by software as input.
174*5398b2faSGeert Uytterhoeven                     */
175*5398b2faSGeert Uytterhoeven                    tioc0_input_pins {
176*5398b2faSGeert Uytterhoeven                            pinmux = <RZA1_PINMUX(4, 0, 2)>;
177*5398b2faSGeert Uytterhoeven                            input-enable;
178*5398b2faSGeert Uytterhoeven                    };
179*5398b2faSGeert Uytterhoeven
180*5398b2faSGeert Uytterhoeven                    /*
181*5398b2faSGeert Uytterhoeven                     * Configure TIOC0B as software driven output
182*5398b2faSGeert Uytterhoeven                     * Pin #1 on port #4 is configured as alternate function #1
183*5398b2faSGeert Uytterhoeven                     * with IO direction specified by software as output.
184*5398b2faSGeert Uytterhoeven                     */
185*5398b2faSGeert Uytterhoeven                    tioc0_output_pins {
186*5398b2faSGeert Uytterhoeven                            pinmux = <RZA1_PINMUX(4, 1, 1)>;
187*5398b2faSGeert Uytterhoeven                            output-enable;
188*5398b2faSGeert Uytterhoeven                    };
189*5398b2faSGeert Uytterhoeven            };
190*5398b2faSGeert Uytterhoeven    };
191