xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml (revision f0b7a0d1d46625db5b0e631c05ae96d78eda6c70) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC8280XP SoC LPASS LPI TLMM
8
9maintainers:
10  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14  (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
15
16properties:
17  compatible:
18    const: qcom,sc8280xp-lpass-lpi-pinctrl
19
20  reg:
21    items:
22      - description: LPASS LPI TLMM Control and Status registers
23      - description: LPASS LPI MCC registers
24
25  clocks:
26    items:
27      - description: LPASS Core voting clock
28      - description: LPASS Audio voting clock
29
30  clock-names:
31    items:
32      - const: core
33      - const: audio
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-sc8280xp-lpass-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-sc8280xp-lpass-state"
42        additionalProperties: false
43
44$defs:
45  qcom-sc8280xp-lpass-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          pattern: "^gpio([0-9]|1[0-8])$"
60
61      function:
62        enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
63                dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
64                dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
65                qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
66                i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
67                wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
68                ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
69        description:
70          Specify the alternative function to be configured for the specified
71          pins.
72
73allOf:
74  - $ref: qcom,lpass-lpi-common.yaml#
75
76required:
77  - compatible
78  - reg
79  - clocks
80  - clock-names
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/sound/qcom,q6afe.h>
87    pinctrl@33c0000 {
88        compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
89        reg = <0x33c0000 0x20000>,
90              <0x3550000 0x10000>;
91        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
92                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
93        clock-names = "core", "audio";
94        gpio-controller;
95        #gpio-cells = <2>;
96        gpio-ranges = <&lpi_tlmm 0 0 19>;
97
98        dmic01-state {
99            dmic01-clk-pins {
100                pins = "gpio16";
101                function = "dmic1_clk";
102            };
103
104            dmic01-clk-sleep-pins {
105                pins = "gpio16";
106                function = "dmic1_clk";
107            };
108        };
109
110        tx-swr-data-sleep-state {
111            pins = "gpio0", "gpio1";
112            function = "swr_tx_data";
113        };
114    };
115