1b9ffc18cSHsin-Yi Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b9ffc18cSHsin-Yi Wang%YAML 1.2 3b9ffc18cSHsin-Yi Wang--- 4b9ffc18cSHsin-Yi Wang$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# 5b9ffc18cSHsin-Yi Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 6b9ffc18cSHsin-Yi Wang 7dd3cb467SAndrew Lunntitle: Mediatek MT8183 Pin Controller 8b9ffc18cSHsin-Yi Wang 9b9ffc18cSHsin-Yi Wangmaintainers: 10b9ffc18cSHsin-Yi Wang - Sean Wang <sean.wang@kernel.org> 11b9ffc18cSHsin-Yi Wang 12b9ffc18cSHsin-Yi Wangdescription: |+ 13b9ffc18cSHsin-Yi Wang The MediaTek's MT8183 Pin controller is used to control SoC pins. 14b9ffc18cSHsin-Yi Wang 15b9ffc18cSHsin-Yi Wangproperties: 16b9ffc18cSHsin-Yi Wang compatible: 17b9ffc18cSHsin-Yi Wang const: mediatek,mt8183-pinctrl 18b9ffc18cSHsin-Yi Wang 19b9ffc18cSHsin-Yi Wang reg: 20b9ffc18cSHsin-Yi Wang minItems: 10 21b9ffc18cSHsin-Yi Wang maxItems: 10 22b9ffc18cSHsin-Yi Wang 23b9ffc18cSHsin-Yi Wang reg-names: 24b9ffc18cSHsin-Yi Wang items: 25b9ffc18cSHsin-Yi Wang - const: iocfg0 26b9ffc18cSHsin-Yi Wang - const: iocfg1 27b9ffc18cSHsin-Yi Wang - const: iocfg2 28b9ffc18cSHsin-Yi Wang - const: iocfg3 29b9ffc18cSHsin-Yi Wang - const: iocfg4 30b9ffc18cSHsin-Yi Wang - const: iocfg5 31b9ffc18cSHsin-Yi Wang - const: iocfg6 32b9ffc18cSHsin-Yi Wang - const: iocfg7 33b9ffc18cSHsin-Yi Wang - const: iocfg8 34b9ffc18cSHsin-Yi Wang - const: eint 35b9ffc18cSHsin-Yi Wang 36b9ffc18cSHsin-Yi Wang gpio-controller: true 37b9ffc18cSHsin-Yi Wang 38b9ffc18cSHsin-Yi Wang "#gpio-cells": 39b9ffc18cSHsin-Yi Wang const: 2 40b9ffc18cSHsin-Yi Wang description: | 41b9ffc18cSHsin-Yi Wang Number of cells in GPIO specifier. Since the generic GPIO 42b9ffc18cSHsin-Yi Wang binding is used, the amount of cells must be specified as 2. See the below 43b9ffc18cSHsin-Yi Wang mentioned gpio binding representation for description of particular cells. 44b9ffc18cSHsin-Yi Wang 45b9ffc18cSHsin-Yi Wang gpio-ranges: 46b9ffc18cSHsin-Yi Wang minItems: 1 47b9ffc18cSHsin-Yi Wang maxItems: 5 48b9ffc18cSHsin-Yi Wang description: | 49b9ffc18cSHsin-Yi Wang GPIO valid number range. 50b9ffc18cSHsin-Yi Wang 51b9ffc18cSHsin-Yi Wang interrupt-controller: true 52b9ffc18cSHsin-Yi Wang 53b9ffc18cSHsin-Yi Wang interrupts: 54b9ffc18cSHsin-Yi Wang maxItems: 1 55b9ffc18cSHsin-Yi Wang 56b9ffc18cSHsin-Yi Wang "#interrupt-cells": 57b9ffc18cSHsin-Yi Wang const: 2 58b9ffc18cSHsin-Yi Wang 59c09acbc4SRafał MiłeckiallOf: 60c09acbc4SRafał Miłecki - $ref: "pinctrl.yaml#" 61c09acbc4SRafał Miłecki 62b9ffc18cSHsin-Yi Wangrequired: 63b9ffc18cSHsin-Yi Wang - compatible 64b9ffc18cSHsin-Yi Wang - reg 65b9ffc18cSHsin-Yi Wang - gpio-controller 66b9ffc18cSHsin-Yi Wang - "#gpio-cells" 67b9ffc18cSHsin-Yi Wang - gpio-ranges 68b9ffc18cSHsin-Yi Wang 69b9ffc18cSHsin-Yi WangpatternProperties: 70*6c488fbbSRob Herring '-pins(-[a-z]+)?$': 71b9ffc18cSHsin-Yi Wang type: object 72b9ffc18cSHsin-Yi Wang additionalProperties: false 73b9ffc18cSHsin-Yi Wang patternProperties: 74*6c488fbbSRob Herring '^pins': 75b9ffc18cSHsin-Yi Wang type: object 76b9ffc18cSHsin-Yi Wang additionalProperties: false 77b9ffc18cSHsin-Yi Wang description: | 78b9ffc18cSHsin-Yi Wang A pinctrl node should contain at least one subnodes representing the 79b9ffc18cSHsin-Yi Wang pinctrl groups available on the machine. Each subnode will list the 80b9ffc18cSHsin-Yi Wang pins it needs, and how they should be configured, with regard to muxer 81b9ffc18cSHsin-Yi Wang configuration, pullups, drive strength, input enable/disable and input 82b9ffc18cSHsin-Yi Wang schmitt. 83b9ffc18cSHsin-Yi Wang $ref: "/schemas/pinctrl/pincfg-node.yaml" 84b9ffc18cSHsin-Yi Wang 85b9ffc18cSHsin-Yi Wang properties: 86b9ffc18cSHsin-Yi Wang pinmux: 87b9ffc18cSHsin-Yi Wang description: 88b9ffc18cSHsin-Yi Wang integer array, represents gpio pin number and mux setting. 89b9ffc18cSHsin-Yi Wang Supported pin number and mux varies for different SoCs, and are 90b9ffc18cSHsin-Yi Wang defined as macros in <soc>-pinfunc.h directly. 91b9ffc18cSHsin-Yi Wang 92b9ffc18cSHsin-Yi Wang bias-disable: true 93b9ffc18cSHsin-Yi Wang 94b9ffc18cSHsin-Yi Wang bias-pull-up: true 95b9ffc18cSHsin-Yi Wang 96b9ffc18cSHsin-Yi Wang bias-pull-down: true 97b9ffc18cSHsin-Yi Wang 98b9ffc18cSHsin-Yi Wang input-enable: true 99b9ffc18cSHsin-Yi Wang 100b9ffc18cSHsin-Yi Wang input-disable: true 101b9ffc18cSHsin-Yi Wang 102b9ffc18cSHsin-Yi Wang output-low: true 103b9ffc18cSHsin-Yi Wang 104b9ffc18cSHsin-Yi Wang output-high: true 105b9ffc18cSHsin-Yi Wang 106b9ffc18cSHsin-Yi Wang input-schmitt-enable: true 107b9ffc18cSHsin-Yi Wang 108b9ffc18cSHsin-Yi Wang input-schmitt-disable: true 109b9ffc18cSHsin-Yi Wang 110b9ffc18cSHsin-Yi Wang drive-strength: 111b9ffc18cSHsin-Yi Wang enum: [2, 4, 6, 8, 10, 12, 14, 16] 112b9ffc18cSHsin-Yi Wang 113b9ffc18cSHsin-Yi Wang mediatek,drive-strength-adv: 114b9ffc18cSHsin-Yi Wang description: | 115b9ffc18cSHsin-Yi Wang Describe the specific driving setup property. 116b9ffc18cSHsin-Yi Wang For I2C pins, the existing generic driving setup can only support 117b9ffc18cSHsin-Yi Wang 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they 118b9ffc18cSHsin-Yi Wang can support 0.125/0.25/0.5/1mA adjustment. If we enable specific 119b9ffc18cSHsin-Yi Wang driving setup, the existing generic setup will be disabled. 120b9ffc18cSHsin-Yi Wang The specific driving setup is controlled by E1E0EN. 121b9ffc18cSHsin-Yi Wang When E1=0/E0=0, the strength is 0.125mA. 122b9ffc18cSHsin-Yi Wang When E1=0/E0=1, the strength is 0.25mA. 123b9ffc18cSHsin-Yi Wang When E1=1/E0=0, the strength is 0.5mA. 124b9ffc18cSHsin-Yi Wang When E1=1/E0=1, the strength is 1mA. 125b9ffc18cSHsin-Yi Wang EN is used to enable or disable the specific driving setup. 126b9ffc18cSHsin-Yi Wang Valid arguments are described as below: 127b9ffc18cSHsin-Yi Wang 0: (E1, E0, EN) = (0, 0, 0) 128b9ffc18cSHsin-Yi Wang 1: (E1, E0, EN) = (0, 0, 1) 129b9ffc18cSHsin-Yi Wang 2: (E1, E0, EN) = (0, 1, 0) 130b9ffc18cSHsin-Yi Wang 3: (E1, E0, EN) = (0, 1, 1) 131b9ffc18cSHsin-Yi Wang 4: (E1, E0, EN) = (1, 0, 0) 132b9ffc18cSHsin-Yi Wang 5: (E1, E0, EN) = (1, 0, 1) 133b9ffc18cSHsin-Yi Wang 6: (E1, E0, EN) = (1, 1, 0) 134b9ffc18cSHsin-Yi Wang 7: (E1, E0, EN) = (1, 1, 1) 135b9ffc18cSHsin-Yi Wang So the valid arguments are from 0 to 7. 136b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/uint32 137b9ffc18cSHsin-Yi Wang enum: [0, 1, 2, 3, 4, 5, 6, 7] 138b9ffc18cSHsin-Yi Wang 139b9ffc18cSHsin-Yi Wang mediatek,pull-up-adv: 140b9ffc18cSHsin-Yi Wang description: | 141b9ffc18cSHsin-Yi Wang Pull up setings for 2 pull resistors, R0 and R1. User can 142b9ffc18cSHsin-Yi Wang configure those special pins. Valid arguments are described as below: 143b9ffc18cSHsin-Yi Wang 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 144b9ffc18cSHsin-Yi Wang 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 145b9ffc18cSHsin-Yi Wang 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 146b9ffc18cSHsin-Yi Wang 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 147b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/uint32 148b9ffc18cSHsin-Yi Wang enum: [0, 1, 2, 3] 149b9ffc18cSHsin-Yi Wang 150b9ffc18cSHsin-Yi Wang mediatek,pull-down-adv: 151b9ffc18cSHsin-Yi Wang description: | 152b9ffc18cSHsin-Yi Wang Pull down settings for 2 pull resistors, R0 and R1. User can 153b9ffc18cSHsin-Yi Wang configure those special pins. Valid arguments are described as below: 154b9ffc18cSHsin-Yi Wang 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 155b9ffc18cSHsin-Yi Wang 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 156b9ffc18cSHsin-Yi Wang 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 157b9ffc18cSHsin-Yi Wang 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 158b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/uint32 159b9ffc18cSHsin-Yi Wang enum: [0, 1, 2, 3] 160b9ffc18cSHsin-Yi Wang 161b9ffc18cSHsin-Yi Wang mediatek,tdsel: 162b9ffc18cSHsin-Yi Wang description: | 163b9ffc18cSHsin-Yi Wang An integer describing the steps for output level shifter duty 164b9ffc18cSHsin-Yi Wang cycle when asserted (high pulse width adjustment). Valid arguments 165b9ffc18cSHsin-Yi Wang are from 0 to 15. 166b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/uint32 167b9ffc18cSHsin-Yi Wang 168b9ffc18cSHsin-Yi Wang mediatek,rdsel: 169b9ffc18cSHsin-Yi Wang description: | 170b9ffc18cSHsin-Yi Wang An integer describing the steps for input level shifter duty cycle 171b9ffc18cSHsin-Yi Wang when asserted (high pulse width adjustment). Valid arguments are 172b9ffc18cSHsin-Yi Wang from 0 to 63. 173b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/uint32 174b9ffc18cSHsin-Yi Wang 175b9ffc18cSHsin-Yi Wang required: 176b9ffc18cSHsin-Yi Wang - pinmux 177b9ffc18cSHsin-Yi Wang 178b9ffc18cSHsin-Yi WangadditionalProperties: false 179b9ffc18cSHsin-Yi Wang 180b9ffc18cSHsin-Yi Wangexamples: 181b9ffc18cSHsin-Yi Wang - | 182b9ffc18cSHsin-Yi Wang #include <dt-bindings/interrupt-controller/irq.h> 183b9ffc18cSHsin-Yi Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 184b9ffc18cSHsin-Yi Wang #include <dt-bindings/pinctrl/mt8183-pinfunc.h> 185b9ffc18cSHsin-Yi Wang 186b9ffc18cSHsin-Yi Wang soc { 187b9ffc18cSHsin-Yi Wang #address-cells = <2>; 188b9ffc18cSHsin-Yi Wang #size-cells = <2>; 189b9ffc18cSHsin-Yi Wang 190b9ffc18cSHsin-Yi Wang pio: pinctrl@10005000 { 191b9ffc18cSHsin-Yi Wang compatible = "mediatek,mt8183-pinctrl"; 192b9ffc18cSHsin-Yi Wang reg = <0 0x10005000 0 0x1000>, 193b9ffc18cSHsin-Yi Wang <0 0x11f20000 0 0x1000>, 194b9ffc18cSHsin-Yi Wang <0 0x11e80000 0 0x1000>, 195b9ffc18cSHsin-Yi Wang <0 0x11e70000 0 0x1000>, 196b9ffc18cSHsin-Yi Wang <0 0x11e90000 0 0x1000>, 197b9ffc18cSHsin-Yi Wang <0 0x11d30000 0 0x1000>, 198b9ffc18cSHsin-Yi Wang <0 0x11d20000 0 0x1000>, 199b9ffc18cSHsin-Yi Wang <0 0x11c50000 0 0x1000>, 200b9ffc18cSHsin-Yi Wang <0 0x11f30000 0 0x1000>, 201b9ffc18cSHsin-Yi Wang <0 0x1000b000 0 0x1000>; 202b9ffc18cSHsin-Yi Wang reg-names = "iocfg0", "iocfg1", "iocfg2", 203b9ffc18cSHsin-Yi Wang "iocfg3", "iocfg4", "iocfg5", 204b9ffc18cSHsin-Yi Wang "iocfg6", "iocfg7", "iocfg8", 205b9ffc18cSHsin-Yi Wang "eint"; 206b9ffc18cSHsin-Yi Wang gpio-controller; 207b9ffc18cSHsin-Yi Wang #gpio-cells = <2>; 208b9ffc18cSHsin-Yi Wang gpio-ranges = <&pio 0 0 192>; 209b9ffc18cSHsin-Yi Wang interrupt-controller; 210b9ffc18cSHsin-Yi Wang interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 211b9ffc18cSHsin-Yi Wang #interrupt-cells = <2>; 212b9ffc18cSHsin-Yi Wang 213*6c488fbbSRob Herring i2c0_pins_a: i2c0-pins { 214b9ffc18cSHsin-Yi Wang pins1 { 215b9ffc18cSHsin-Yi Wang pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 216b9ffc18cSHsin-Yi Wang <PINMUX_GPIO49__FUNC_SDA5>; 217b9ffc18cSHsin-Yi Wang mediatek,pull-up-adv = <3>; 218b9ffc18cSHsin-Yi Wang mediatek,drive-strength-adv = <7>; 219b9ffc18cSHsin-Yi Wang }; 220b9ffc18cSHsin-Yi Wang }; 221b9ffc18cSHsin-Yi Wang 222*6c488fbbSRob Herring i2c1_pins_a: i2c1-pins { 223b9ffc18cSHsin-Yi Wang pins { 224b9ffc18cSHsin-Yi Wang pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 225b9ffc18cSHsin-Yi Wang <PINMUX_GPIO51__FUNC_SDA3>; 226b9ffc18cSHsin-Yi Wang mediatek,pull-down-adv = <2>; 227b9ffc18cSHsin-Yi Wang mediatek,drive-strength-adv = <4>; 228b9ffc18cSHsin-Yi Wang }; 229b9ffc18cSHsin-Yi Wang }; 230b9ffc18cSHsin-Yi Wang }; 231b9ffc18cSHsin-Yi Wang }; 232