xref: /linux/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml (revision 0434cd276e7265d6db2bc389a021b795ec16fa69)
1*0434cd27SRahul Tanwar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*0434cd27SRahul Tanwar%YAML 1.2
3*0434cd27SRahul Tanwar---
4*0434cd27SRahul Tanwar$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-io.yaml#
5*0434cd27SRahul Tanwar$schema: http://devicetree.org/meta-schemas/core.yaml#
6*0434cd27SRahul Tanwar
7*0434cd27SRahul Tanwartitle: Intel Lightning Mountain SoC pinmux & GPIO controller binding
8*0434cd27SRahul Tanwar
9*0434cd27SRahul Tanwarmaintainers:
10*0434cd27SRahul Tanwar  - Rahul Tanwar <rahul.tanwar@linux.intel.com>
11*0434cd27SRahul Tanwar
12*0434cd27SRahul Tanwardescription: |
13*0434cd27SRahul Tanwar  Pinmux & GPIO controller controls pin multiplexing & configuration including
14*0434cd27SRahul Tanwar  GPIO function selection & GPIO attributes configuration.
15*0434cd27SRahul Tanwar
16*0434cd27SRahul TanwarallOf:
17*0434cd27SRahul Tanwar  - $ref: pincfg-node.yaml#
18*0434cd27SRahul Tanwar  - $ref: pinmux-node.yaml#
19*0434cd27SRahul Tanwar
20*0434cd27SRahul Tanwarproperties:
21*0434cd27SRahul Tanwar  compatible:
22*0434cd27SRahul Tanwar    const: intel,lgm-io
23*0434cd27SRahul Tanwar
24*0434cd27SRahul Tanwar  reg:
25*0434cd27SRahul Tanwar    maxItems: 1
26*0434cd27SRahul Tanwar
27*0434cd27SRahul Tanwar# Client device subnode's properties
28*0434cd27SRahul TanwarpatternProperties:
29*0434cd27SRahul Tanwar  '-pins$':
30*0434cd27SRahul Tanwar    type: object
31*0434cd27SRahul Tanwar    description:
32*0434cd27SRahul Tanwar      Pinctrl node's client devices use subnodes for desired pin configuration.
33*0434cd27SRahul Tanwar      Client device subnodes use below standard properties.
34*0434cd27SRahul Tanwar
35*0434cd27SRahul Tanwar    properties:
36*0434cd27SRahul Tanwar      function: true
37*0434cd27SRahul Tanwar      group: true
38*0434cd27SRahul Tanwar      pins: true
39*0434cd27SRahul Tanwar      pinmux: true
40*0434cd27SRahul Tanwar      bias-pull-up: true
41*0434cd27SRahul Tanwar      bias-pull-down: true
42*0434cd27SRahul Tanwar      drive-strength: true
43*0434cd27SRahul Tanwar      slew-rate: true
44*0434cd27SRahul Tanwar      drive-open-drain: true
45*0434cd27SRahul Tanwar      output-enable: true
46*0434cd27SRahul Tanwar
47*0434cd27SRahul Tanwar    required:
48*0434cd27SRahul Tanwar      - function
49*0434cd27SRahul Tanwar      - group
50*0434cd27SRahul Tanwar
51*0434cd27SRahul Tanwar    additionalProperties: false
52*0434cd27SRahul Tanwar
53*0434cd27SRahul Tanwarrequired:
54*0434cd27SRahul Tanwar  - compatible
55*0434cd27SRahul Tanwar  - reg
56*0434cd27SRahul Tanwar
57*0434cd27SRahul TanwaradditionalProperties: false
58*0434cd27SRahul Tanwar
59*0434cd27SRahul Tanwarexamples:
60*0434cd27SRahul Tanwar  # Pinmux controller node
61*0434cd27SRahul Tanwar  - |
62*0434cd27SRahul Tanwar    pinctrl: pinctrl@e2880000 {
63*0434cd27SRahul Tanwar        compatible = "intel,lgm-io";
64*0434cd27SRahul Tanwar        reg = <0xe2880000 0x100000>;
65*0434cd27SRahul Tanwar
66*0434cd27SRahul Tanwar        uart0-pins {
67*0434cd27SRahul Tanwar             pins = <64>, /* UART_RX0 */
68*0434cd27SRahul Tanwar                    <65>; /* UART_TX0 */
69*0434cd27SRahul Tanwar             function = "CONSOLE_UART0";
70*0434cd27SRahul Tanwar             pinmux = <1>,
71*0434cd27SRahul Tanwar                      <1>;
72*0434cd27SRahul Tanwar             groups = "CONSOLE_UART0";
73*0434cd27SRahul Tanwar          };
74*0434cd27SRahul Tanwar    };
75*0434cd27SRahul Tanwar
76*0434cd27SRahul Tanwar...
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