1*8dbb528bSFlorian Fainelli# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*8dbb528bSFlorian Fainelli%YAML 1.2 3*8dbb528bSFlorian Fainelli--- 4*8dbb528bSFlorian Fainelli$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml# 5*8dbb528bSFlorian Fainelli$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8dbb528bSFlorian Fainelli 7*8dbb528bSFlorian Fainellititle: Broadcom Cygnus PCIe PHY 8*8dbb528bSFlorian Fainelli 9*8dbb528bSFlorian Fainellimaintainers: 10*8dbb528bSFlorian Fainelli - Ray Jui <ray.jui@broadcom.com> 11*8dbb528bSFlorian Fainelli - Scott Branden <scott.branden@broadcom.com> 12*8dbb528bSFlorian Fainelli 13*8dbb528bSFlorian Fainelliproperties: 14*8dbb528bSFlorian Fainelli $nodename: 15*8dbb528bSFlorian Fainelli pattern: "^pcie[-|_]phy(@.*)?$" 16*8dbb528bSFlorian Fainelli 17*8dbb528bSFlorian Fainelli compatible: 18*8dbb528bSFlorian Fainelli items: 19*8dbb528bSFlorian Fainelli - const: brcm,cygnus-pcie-phy 20*8dbb528bSFlorian Fainelli 21*8dbb528bSFlorian Fainelli reg: 22*8dbb528bSFlorian Fainelli maxItems: 1 23*8dbb528bSFlorian Fainelli description: > 24*8dbb528bSFlorian Fainelli Base address and length of the PCIe PHY block 25*8dbb528bSFlorian Fainelli 26*8dbb528bSFlorian Fainelli "#address-cells": 27*8dbb528bSFlorian Fainelli const: 1 28*8dbb528bSFlorian Fainelli 29*8dbb528bSFlorian Fainelli "#size-cells": 30*8dbb528bSFlorian Fainelli const: 0 31*8dbb528bSFlorian Fainelli 32*8dbb528bSFlorian FainellipatternProperties: 33*8dbb528bSFlorian Fainelli "^pcie-phy@[0-9]+$": 34*8dbb528bSFlorian Fainelli type: object 35*8dbb528bSFlorian Fainelli description: > 36*8dbb528bSFlorian Fainelli PCIe PHY child nodes 37*8dbb528bSFlorian Fainelli 38*8dbb528bSFlorian Fainelli properties: 39*8dbb528bSFlorian Fainelli reg: 40*8dbb528bSFlorian Fainelli maxItems: 1 41*8dbb528bSFlorian Fainelli description: > 42*8dbb528bSFlorian Fainelli The PCIe PHY port number 43*8dbb528bSFlorian Fainelli 44*8dbb528bSFlorian Fainelli "#phy-cells": 45*8dbb528bSFlorian Fainelli const: 0 46*8dbb528bSFlorian Fainelli 47*8dbb528bSFlorian Fainelli required: 48*8dbb528bSFlorian Fainelli - reg 49*8dbb528bSFlorian Fainelli - "#phy-cells" 50*8dbb528bSFlorian Fainelli 51*8dbb528bSFlorian Fainellirequired: 52*8dbb528bSFlorian Fainelli - compatible 53*8dbb528bSFlorian Fainelli - reg 54*8dbb528bSFlorian Fainelli - "#address-cells" 55*8dbb528bSFlorian Fainelli - "#size-cells" 56*8dbb528bSFlorian Fainelli 57*8dbb528bSFlorian FainelliadditionalProperties: false 58*8dbb528bSFlorian Fainelli 59*8dbb528bSFlorian Fainelliexamples: 60*8dbb528bSFlorian Fainelli - | 61*8dbb528bSFlorian Fainelli pcie_phy: pcie_phy@301d0a0 { 62*8dbb528bSFlorian Fainelli compatible = "brcm,cygnus-pcie-phy"; 63*8dbb528bSFlorian Fainelli reg = <0x0301d0a0 0x14>; 64*8dbb528bSFlorian Fainelli #address-cells = <1>; 65*8dbb528bSFlorian Fainelli #size-cells = <0>; 66*8dbb528bSFlorian Fainelli 67*8dbb528bSFlorian Fainelli pcie0_phy: pcie-phy@0 { 68*8dbb528bSFlorian Fainelli reg = <0>; 69*8dbb528bSFlorian Fainelli #phy-cells = <0>; 70*8dbb528bSFlorian Fainelli }; 71*8dbb528bSFlorian Fainelli 72*8dbb528bSFlorian Fainelli pcie1_phy: pcie-phy@1 { 73*8dbb528bSFlorian Fainelli reg = <1>; 74*8dbb528bSFlorian Fainelli #phy-cells = <0>; 75*8dbb528bSFlorian Fainelli }; 76*8dbb528bSFlorian Fainelli }; 77