1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DWC PCIe RP/EP controller 8 9maintainers: 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12 13description: 14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller 15 properties. 16 17select: false 18 19properties: 20 reg: 21 description: 22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus 23 Interface - DBI. In accordance with the reference manual the register 24 configuration space belongs to the Configuration-Dependent Module (CDM) 25 and is split up into several sub-parts Standard PCIe configuration 26 space, Port Logic Registers (PL), Shadow Config-space Registers, 27 iATU/eDMA registers. The particular sub-space is selected by the 28 CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such 29 configuration provides a flexible interface for the system engineers to 30 either map the particular space at a desired MMIO address or just leave 31 them in a contiguous memory space if pure Native or AXI Bridge DBI access 32 is selected. Note the PCIe CFG-space, PL and Shadow registers are 33 specific for each activated function, while the rest of the sub-spaces 34 are common for all of them (if there are more than one). 35 minItems: 2 36 maxItems: 7 37 38 reg-names: 39 minItems: 2 40 maxItems: 7 41 42 interrupts: 43 description: 44 There are two main sub-blocks which are normally capable of 45 generating interrupts. It's System Information Interface and MSI 46 interface. While the former one has some common for the Host and 47 Endpoint controllers IRQ-signals, the later interface is obviously 48 Root Complex specific since it's responsible for the incoming MSI 49 messages signalling. The System Information IRQ signals are mainly 50 responsible for reporting the generic PCIe hierarchy and Root 51 Complex events like VPD IO request, general AER, PME, Hot-plug, link 52 bandwidth change, link equalization request, INTx asserted/deasserted 53 Message detection, embedded DMA Tx/Rx/Error. 54 minItems: 1 55 maxItems: 26 56 57 interrupt-names: 58 minItems: 1 59 maxItems: 26 60 61 clocks: 62 description: 63 DWC PCIe reference manual explicitly defines a set of the clocks required 64 to get the controller working correctly. In general all of them can 65 be divided into two groups':' application and core clocks. Note the 66 platforms may have some of the clock sources unspecified in case if the 67 corresponding domains are fed up from a common clock source. 68 minItems: 1 69 maxItems: 7 70 71 clock-names: 72 minItems: 1 73 maxItems: 7 74 items: 75 oneOf: 76 - description: 77 Data Bus Interface (DBI) clock. Clock signal for the AXI-bus 78 interface of the Configuration-Dependent Module, which is 79 basically the set of the controller CSRs. 80 const: dbi 81 - description: 82 Application AXI-bus Master interface clock. Basically this is 83 a clock for the controller DMA interface (PCI-to-CPU). 84 const: mstr 85 - description: 86 Application AXI-bus Slave interface clock. This is a clock for 87 the CPU-to-PCI memory IO interface. 88 const: slv 89 - description: 90 Controller Core-PCS PIPE interface clock. It's normally 91 supplied by an external PCS-PHY. 92 const: pipe 93 - description: 94 Controller Primary clock. It's assumed that all controller input 95 signals (except resets) are synchronous to this clock. 96 const: core 97 - description: 98 Auxiliary clock for the controller PMC domain. The controller 99 partitioning implies having some parts to operate with this 100 clock in some power management states. 101 const: aux 102 - description: 103 Generic reference clock. In case if there are several 104 interfaces fed up with a common clock source it's advisable to 105 define it with this name (for instance pipe, core and aux can 106 be connected to a single source of the periodic signal). 107 const: ref 108 - description: 109 Clock for the PHY registers interface. Originally this is 110 a PHY-viewport-based interface, but some platform may have 111 specifically designed one. 112 const: phy_reg 113 - description: 114 Vendor-specific clock names. Consider using the generic names 115 above for new bindings. 116 oneOf: 117 - description: See native 'dbi' clock for details 118 enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ] 119 - description: See native 'mstr/slv' clock for details 120 enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ] 121 - description: See native 'pipe' clock for details 122 enum: [ pcie_phy, pcie_phy_ref, link ] 123 - description: See native 'aux' clock for details 124 enum: [ pcie_aux ] 125 - description: See native 'ref' clock for details. 126 enum: [ gio ] 127 - description: See nativs 'phy_reg' clock for details 128 enum: [ pcie_apb_phy, pclk ] 129 130 resets: 131 description: 132 DWC PCIe reference manual explicitly defines a set of the reset 133 signals required to be de-asserted to properly activate the controller 134 sub-parts. All of these signals can be divided into two sub-groups':' 135 application and core resets with respect to the main sub-domains they 136 are supposed to reset. Note the platforms may have some of these signals 137 unspecified in case if they are automatically handled or aggregated into 138 a comprehensive control module. 139 minItems: 1 140 maxItems: 10 141 142 reset-names: 143 minItems: 1 144 maxItems: 10 145 items: 146 oneOf: 147 - description: Data Bus Interface (DBI) domain reset 148 const: dbi 149 - description: AXI-bus Master interface reset 150 const: mstr 151 - description: AXI-bus Slave interface reset 152 const: slv 153 - description: Application-dependent interface reset 154 const: app 155 - description: Controller Non-sticky CSR flags reset 156 const: non-sticky 157 - description: Controller sticky CSR flags reset 158 const: sticky 159 - description: PIPE-interface (Core-PCS) logic reset 160 const: pipe 161 - description: 162 Controller primary reset (resets everything except PMC module) 163 const: core 164 - description: PCS/PHY block reset 165 const: phy 166 - description: PMC hot reset signal 167 const: hot 168 - description: Cold reset signal 169 const: pwr 170 - description: 171 Vendor-specific reset names. Consider using the generic names 172 above for new bindings. 173 oneOf: 174 - description: See native 'app' reset for details 175 enum: [ apps, gio, apb ] 176 - description: See native 'phy' reset for details 177 enum: [ pciephy, link ] 178 - description: See native 'pwr' reset for details 179 enum: [ turnoff ] 180 181 phys: 182 description: 183 There can be up to the number of possible lanes PHYs specified placed in 184 the phandle array in the line-based order. Obviously each the specified 185 PHYs are supposed to be able to work in the PCIe mode with a speed 186 implied by the DWC PCIe controller they are attached to. 187 minItems: 1 188 maxItems: 16 189 190 phy-names: 191 minItems: 1 192 maxItems: 16 193 oneOf: 194 - description: Generic PHY names 195 items: 196 pattern: '^pcie[0-9]+$' 197 - description: 198 Vendor-specific PHY names. Consider using the generic 199 names above for new bindings. 200 items: 201 oneOf: 202 - pattern: '^pcie(-?phy[0-9]*)?$' 203 - pattern: '^p2u-[0-7]$' 204 - pattern: '^cp[01]-pcie[0-2]-x[124](-lane[0-3])?-phy$' # marvell,armada8k-pcie 205 206 reset-gpio: 207 deprecated: true 208 description: 209 Reference to the GPIO-controlled PERST# signal. It is used to reset all 210 the peripheral devices available on the PCIe bus. 211 maxItems: 1 212 213 reset-gpios: 214 description: 215 Reference to the GPIO-controlled PERST# signal. It is used to reset all 216 the peripheral devices available on the PCIe bus. 217 maxItems: 1 218 219 max-link-speed: 220 maximum: 5 221 222 num-lanes: 223 description: 224 Number of PCIe link lanes to use. Can be omitted if the already brought 225 up link is supposed to be preserved. 226 maximum: 16 227 228 num-ob-windows: 229 $ref: /schemas/types.yaml#/definitions/uint32 230 deprecated: true 231 description: 232 Number of outbound address translation windows. This parameter can be 233 auto-detected based on the iATU memory writability. So there is no 234 point in having a dedicated DT-property for it. 235 maximum: 256 236 237 num-ib-windows: 238 $ref: /schemas/types.yaml#/definitions/uint32 239 deprecated: true 240 description: 241 Number of inbound address translation windows. In the same way as 242 for the outbound AT windows, this parameter can be auto-detected based 243 on the iATU memory writability. There is no point having a dedicated 244 DT-property for it either. 245 maximum: 256 246 247 num-viewport: 248 $ref: /schemas/types.yaml#/definitions/uint32 249 deprecated: true 250 description: 251 Number of outbound view ports configured in hardware. It's the same as 252 the number of outbound AT windows. 253 maximum: 256 254 255 snps,enable-cdm-check: 256 $ref: /schemas/types.yaml#/definitions/flag 257 description: 258 Enable automatic checking of CDM (Configuration Dependent Module) 259 registers for data corruption. CDM registers include standard PCIe 260 configuration space registers, Port Logic registers, DMA and iATU 261 registers. This feature has been available since DWC PCIe v4.80a. 262 263 dma-coherent: true 264 265additionalProperties: true 266 267... 268