xref: /linux/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml (revision d8bf56a0ca10af7936de8bbdd510c33041dacecc) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Altera SOCFPGA SoC DWMAC controller
8
9maintainers:
10  - Matthew Gerlach <matthew.gerlach@altera.com>
11
12description:
13  This binding describes the Altera SOCFPGA SoC implementation of the
14  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
15  of chips.
16  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
17  # does not validate against net/snps,dwmac.yaml.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - altr,socfpga-stmmac
25          - altr,socfpga-stmmac-a10-s10
26
27  required:
28    - compatible
29
30properties:
31  compatible:
32    oneOf:
33      - items:
34          - const: altr,socfpga-stmmac
35          - const: snps,dwmac-3.70a
36          - const: snps,dwmac
37      - items:
38          - const: altr,socfpga-stmmac-a10-s10
39          - const: snps,dwmac-3.72a
40          - const: snps,dwmac
41      - items:
42          - const: altr,socfpga-stmmac-a10-s10
43          - const: snps,dwmac-3.74a
44          - const: snps,dwmac
45
46  clocks:
47    minItems: 1
48    items:
49      - description: GMAC main clock
50      - description:
51          PTP reference clock. This clock is used for programming the
52          Timestamp Addend Register. If not passed then the system
53          clock will be used and this is fine on some platforms.
54
55  clock-names:
56    minItems: 1
57    items:
58      - const: stmmaceth
59      - const: ptp_ref
60
61  iommus:
62    maxItems: 2
63
64  phy-mode:
65    enum:
66      - gmii
67      - mii
68      - rgmii
69      - rgmii-id
70      - rgmii-rxid
71      - rgmii-txid
72      - sgmii
73      - 1000base-x
74
75  rxc-skew-ps:
76    description: Skew control of RXC pad
77
78  rxd0-skew-ps:
79    description: Skew control of RX data 0 pad
80
81  rxd1-skew-ps:
82    description: Skew control of RX data 1 pad
83
84  rxd2-skew-ps:
85    description: Skew control of RX data 2 pad
86
87  rxd3-skew-ps:
88    description: Skew control of RX data 3 pad
89
90  rxdv-skew-ps:
91    description: Skew control of RX CTL pad
92
93  txc-skew-ps:
94    description: Skew control of TXC pad
95
96  txen-skew-ps:
97    description: Skew control of TXC pad
98
99  altr,emac-splitter:
100    $ref: /schemas/types.yaml#/definitions/phandle
101    description:
102      Should be the phandle to the emac splitter soft IP node if DWMAC
103      controller is connected an emac splitter.
104
105  altr,f2h_ptp_ref_clk:
106    $ref: /schemas/types.yaml#/definitions/phandle
107    description:
108      Phandle to Precision Time Protocol reference clock. This clock is
109      common to gmac instances and defaults to osc1.
110
111  altr,gmii-to-sgmii-converter:
112    $ref: /schemas/types.yaml#/definitions/phandle
113    description:
114      Should be the phandle to the gmii to sgmii converter soft IP.
115
116  altr,sysmgr-syscon:
117    $ref: /schemas/types.yaml#/definitions/phandle-array
118    description:
119      Should be the phandle to the system manager node that encompass
120      the glue register, the register offset, and the register shift.
121      On Cyclone5/Arria5, the register shift represents the PHY mode
122      bits, while on the Arria10/Stratix10/Agilex platforms, the
123      register shift represents bit for each emac to enable/disable
124      signals from the FPGA fabric to the EMAC modules.
125    items:
126      - items:
127          - description: phandle to the system manager node
128          - description: offset of the control register
129          - description: shift within the control register
130
131patternProperties:
132  "^mdio[0-9]$":
133    type: object
134
135required:
136  - compatible
137  - clocks
138  - clock-names
139  - altr,sysmgr-syscon
140
141allOf:
142  - $ref: snps,dwmac.yaml#
143
144unevaluatedProperties: false
145
146examples:
147
148  - |
149    #include <dt-bindings/interrupt-controller/arm-gic.h>
150    #include <dt-bindings/interrupt-controller/irq.h>
151    soc {
152        #address-cells = <1>;
153        #size-cells = <1>;
154        ethernet@ff700000 {
155            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
156            "snps,dwmac";
157            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
158            reg = <0xff700000 0x2000>;
159            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
160            interrupt-names = "macirq";
161            mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
162            clocks = <&emac_0_clk>;
163            clock-names = "stmmaceth";
164            phy-mode = "sgmii";
165        };
166    };
167