1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: | 13 Flash chips (Memory Technology Devices) are often used for solid state 14 file systems on embedded devices. 15 16allOf: 17 - $ref: mtd.yaml# 18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 19 20properties: 21 compatible: 22 oneOf: 23 - items: 24 - enum: 25 - amd,s29gl01gp 26 - amd,s29gl032a 27 - amd,s29gl256n 28 - amd,s29gl512n 29 - arm,versatile-flash 30 - arm,vexpress-flash 31 - cortina,gemini-flash 32 - cypress,hyperflash 33 - ge,imp3a-firmware-mirror 34 - ge,imp3a-paged-flash 35 - gef,ppc9a-firmware-mirror 36 - gef,ppc9a-paged-flash 37 - gef,sbc310-firmware-mirror 38 - gef,sbc310-paged-flash 39 - gef,sbc610-firmware-mirror 40 - gef,sbc610-paged-flash 41 - intel,28f128j3 42 - intel,dt28f160 43 - intel,ixp4xx-flash 44 - intel,JS28F128 45 - intel,JS28F640 46 - intel,PC28F640P30T85 47 - numonyx,js28f00a 48 - numonyx,js28f128 49 - sst,sst39vf320 50 - xlnx,xps-mch-emc-2.00.a 51 - enum: 52 - cfi-flash 53 - jedec-flash 54 - items: 55 - enum: 56 - cypress,cy7c1019dv33-10zsxi 57 - arm,vexpress-psram 58 - const: mtd-ram 59 - enum: 60 - cfi-flash 61 - jedec-flash 62 - mtd-ram 63 - mtd-rom 64 65 reg: 66 description: | 67 It's possible to (optionally) define multiple "reg" tuples so that 68 non-identical chips can be described in one node. 69 minItems: 1 70 maxItems: 8 71 72 clocks: 73 description: | 74 Chips may need clocks to be enabled for themselves or for transparent 75 bridges. 76 77 power-domains: 78 description: | 79 Chips may need power domains to be enabled for themselves or for 80 transparent bridges. 81 82 bank-width: 83 description: Width (in bytes) of the bank. Equal to the device width times 84 the number of interleaved chips. 85 $ref: /schemas/types.yaml#/definitions/uint32 86 enum: [ 1, 2, 4 ] 87 88 device-width: 89 description: 90 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'. 91 $ref: /schemas/types.yaml#/definitions/uint32 92 enum: [ 1, 2 ] 93 94 no-unaligned-direct-access: 95 type: boolean 96 description: | 97 Disables the default direct mapping of the flash. 98 99 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems 100 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned 101 accesses as implemented in the JFFS2 code via memcpy(). By defining 102 "no-unaligned-direct-access", the flash will not be exposed directly to 103 the MTD users (e.g. JFFS2) any more. 104 105 linux,mtd-name: 106 description: 107 Allows specifying the mtd name for retro capability with physmap-flash 108 drivers as boot loader pass the mtd partition via the old device name 109 physmap-flash. 110 $ref: /schemas/types.yaml#/definitions/string 111 112 use-advanced-sector-protection: 113 type: boolean 114 description: | 115 Enables support for the advanced sector protection (Spansion: PPB - 116 Persistent Protection Bits) locking. 117 118 erase-size: 119 description: The chip's physical erase block size in bytes. 120 $ref: /schemas/types.yaml#/definitions/uint32 121 122 addr-gpios: 123 description: 124 List of GPIO descriptors that will be used to address the MSBs address 125 lines. The order goes from LSB to MSB. 126 minItems: 1 127 maxItems: 8 128 129 '#address-cells': 130 const: 1 131 132 '#size-cells': 133 const: 1 134 135 ranges: true 136 137 big-endian: true 138 little-endian: true 139 140required: 141 - compatible 142 - reg 143 144if: 145 properties: 146 compatible: 147 contains: 148 const: cortina,gemini-flash 149then: 150 properties: 151 syscon: 152 $ref: /schemas/types.yaml#/definitions/phandle 153 description: 154 Phandle to the syscon controller 155 required: 156 - syscon 157 158unevaluatedProperties: false 159 160examples: 161 - | 162 163 flash@ff000000 { 164 compatible = "cfi-flash"; 165 reg = <0xff000000 0x01000000>; 166 bank-width = <4>; 167 device-width = <1>; 168 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0 0xff000000 0x01000000>; 172 173 fs@0 { 174 label = "fs"; 175 reg = <0 0xf80000>; 176 }; 177 firmware@f80000 { 178 label = "firmware"; 179 reg = <0xf80000 0x80000>; 180 read-only; 181 }; 182 }; 183 184 - | 185 /* An example with multiple "reg" tuples */ 186 187 flash@0 { 188 compatible = "intel,PC28F640P30T85", "cfi-flash"; 189 reg = <0x00000000 0x02000000>, 190 <0x02000000 0x02000000>; 191 bank-width = <2>; 192 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0 0 0x04000000>; 196 197 partition@0 { 198 label = "test-part1"; 199 reg = <0 0x04000000>; 200 }; 201 }; 202 203 - | 204 /* An example using SRAM */ 205 bus { 206 #address-cells = <2>; 207 #size-cells = <1>; 208 209 sram@2,0 { 210 compatible = "mtd-ram"; 211 reg = <2 0 0x00200000>; 212 bank-width = <2>; 213 }; 214 }; 215 216 - | 217 /* An example using addr-gpios */ 218 #include <dt-bindings/gpio/gpio.h> 219 220 flash@20000000 { 221 compatible = "cfi-flash"; 222 reg = <0x20000000 0x02000000>; 223 bank-width = <2>; 224 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 225 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0 0x00000000 0x02000000>, 229 <1 0x02000000 0x02000000>; 230 231 partition@0 { 232 label = "test-part1"; 233 reg = <0 0x04000000>; 234 }; 235 }; 236... 237