1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ DMA Controller 8 9maintainers: 10 - Biju Das <biju.das.jz@bp.renesas.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,r7s72100-dmac # RZ/A1H 18 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five 19 - renesas,r9a07g044-dmac # RZ/G2{L,LC} 20 - renesas,r9a07g054-dmac # RZ/V2L 21 - renesas,r9a08g045-dmac # RZ/G3S 22 - const: renesas,rz-dmac 23 24 - const: renesas,r9a09g057-dmac # RZ/V2H(P) 25 26 reg: 27 items: 28 - description: Control and channel register block 29 - description: DMA extended resource selector block 30 minItems: 1 31 32 interrupts: 33 maxItems: 17 34 35 interrupt-names: 36 items: 37 - const: error 38 - const: ch0 39 - const: ch1 40 - const: ch2 41 - const: ch3 42 - const: ch4 43 - const: ch5 44 - const: ch6 45 - const: ch7 46 - const: ch8 47 - const: ch9 48 - const: ch10 49 - const: ch11 50 - const: ch12 51 - const: ch13 52 - const: ch14 53 - const: ch15 54 55 clocks: 56 items: 57 - description: DMA main clock 58 - description: DMA register access clock 59 minItems: 1 60 61 clock-names: 62 items: 63 - const: main 64 - const: register 65 66 '#dma-cells': 67 const: 1 68 description: 69 The cell specifies the encoded MID/RID or the REQ No values of 70 the DMAC port connected to the DMA client and the slave channel 71 configuration parameters. 72 bits[0:9] - Specifies the MID/RID or the REQ No value 73 bit[10] - Specifies DMA request high enable (HIEN) 74 bit[11] - Specifies DMA request detection type (LVL) 75 bits[12:14] - Specifies DMAACK output mode (AM) 76 bit[15] - Specifies Transfer Mode (TM) 77 78 dma-channels: 79 const: 16 80 81 power-domains: 82 maxItems: 1 83 84 resets: 85 items: 86 - description: Reset for DMA ARESETN reset terminal 87 - description: Reset for DMA RST_ASYNC reset terminal 88 minItems: 1 89 90 reset-names: 91 items: 92 - const: arst 93 - const: rst_async 94 95 renesas,icu: 96 description: 97 It must contain the phandle to the ICU and the index of the DMAC as seen 98 from the ICU. 99 $ref: /schemas/types.yaml#/definitions/phandle-array 100 items: 101 - items: 102 - description: Phandle to the ICU node. 103 - description: 104 The number of the DMAC as seen from the ICU, i.e. parameter k from 105 register ICU_DMkSELy. This may differ from the actual DMAC instance 106 number. 107 108required: 109 - compatible 110 - reg 111 - interrupts 112 - interrupt-names 113 - '#dma-cells' 114 - dma-channels 115 116allOf: 117 - $ref: dma-controller.yaml# 118 119 - if: 120 properties: 121 compatible: 122 contains: 123 enum: 124 - renesas,r9a07g043-dmac 125 - renesas,r9a07g044-dmac 126 - renesas,r9a07g054-dmac 127 - renesas,r9a08g045-dmac 128 then: 129 properties: 130 reg: 131 minItems: 2 132 clocks: 133 minItems: 2 134 resets: 135 minItems: 2 136 137 renesas,icu: false 138 139 required: 140 - clocks 141 - clock-names 142 - power-domains 143 - resets 144 - reset-names 145 146 - if: 147 properties: 148 compatible: 149 contains: 150 const: renesas,r7s72100-dmac 151 then: 152 properties: 153 reg: 154 minItems: 2 155 156 clocks: false 157 clock-names: false 158 power-domains: false 159 resets: false 160 reset-names: false 161 renesas,icu: false 162 163 - if: 164 properties: 165 compatible: 166 contains: 167 const: renesas,r9a09g057-dmac 168 then: 169 properties: 170 reg: 171 maxItems: 1 172 clocks: 173 maxItems: 1 174 resets: 175 maxItems: 1 176 177 clock-names: false 178 reset-names: false 179 180 required: 181 - clocks 182 - power-domains 183 - renesas,icu 184 - resets 185 186additionalProperties: false 187 188examples: 189 - | 190 #include <dt-bindings/interrupt-controller/arm-gic.h> 191 #include <dt-bindings/clock/r9a07g044-cpg.h> 192 193 dmac: dma-controller@11820000 { 194 compatible = "renesas,r9a07g044-dmac", 195 "renesas,rz-dmac"; 196 reg = <0x11820000 0x10000>, 197 <0x11830000 0x10000>; 198 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 202 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 203 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 207 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 208 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 210 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 211 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 212 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 213 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 214 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 215 interrupt-names = "error", 216 "ch0", "ch1", "ch2", "ch3", 217 "ch4", "ch5", "ch6", "ch7", 218 "ch8", "ch9", "ch10", "ch11", 219 "ch12", "ch13", "ch14", "ch15"; 220 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 221 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 222 clock-names = "main", "register"; 223 power-domains = <&cpg>; 224 resets = <&cpg R9A07G044_DMAC_ARESETN>, 225 <&cpg R9A07G044_DMAC_RST_ASYNC>; 226 reset-names = "arst", "rst_async"; 227 #dma-cells = <1>; 228 dma-channels = <16>; 229 }; 230