xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml (revision 50b7e7082a3dde5bdba14a4e40a2e2279fd08a7b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8350 Display MDSS
8
9maintainers:
10  - Robert Foss <robert.foss@linaro.org>
11
12description:
13  MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    items:
21      - const: qcom,sm8350-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display hf axi clock
27      - description: Display sf axi clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: nrt_bus
35      - const: core
36
37  iommus:
38    maxItems: 1
39
40  interconnects:
41    items:
42      - description: Interconnect path from the MDP0 port to the data bus
43      - description: Interconnect path from the MDP1 port to the data bus
44      - description: Interconnect path from the CPU to the reg bus
45
46  interconnect-names:
47    items:
48      - const: mdp0-mem
49      - const: mdp1-mem
50      - const: cpu-cfg
51
52patternProperties:
53  "^display-controller@[0-9a-f]+$":
54    type: object
55    additionalProperties: true
56
57    properties:
58      compatible:
59        const: qcom,sm8350-dpu
60
61  "^displayport-controller@[0-9a-f]+$":
62    type: object
63    additionalProperties: true
64
65    properties:
66      compatible:
67        const: qcom,sm8350-dp
68
69  "^dsi@[0-9a-f]+$":
70    type: object
71    additionalProperties: true
72
73    properties:
74      compatible:
75        items:
76          - const: qcom,sm8350-dsi-ctrl
77          - const: qcom,mdss-dsi-ctrl
78
79  "^phy@[0-9a-f]+$":
80    type: object
81    additionalProperties: true
82
83    properties:
84      compatible:
85        const: qcom,sm8350-dsi-phy-5nm
86
87unevaluatedProperties: false
88
89examples:
90  - |
91    #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
92    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
93    #include <dt-bindings/clock/qcom,rpmh.h>
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95    #include <dt-bindings/interconnect/qcom,icc.h>
96    #include <dt-bindings/interconnect/qcom,sm8350.h>
97    #include <dt-bindings/power/qcom,rpmhpd.h>
98
99    display-subsystem@ae00000 {
100        compatible = "qcom,sm8350-mdss";
101        reg = <0x0ae00000 0x1000>;
102        reg-names = "mdss";
103
104        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
105                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
106                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
107                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
108        interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
109
110        power-domains = <&dispcc MDSS_GDSC>;
111        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
112
113        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
114                 <&gcc GCC_DISP_HF_AXI_CLK>,
115                 <&gcc GCC_DISP_SF_AXI_CLK>,
116                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
117        clock-names = "iface", "bus", "nrt_bus", "core";
118
119        iommus = <&apps_smmu 0x820 0x402>;
120
121        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
122        interrupt-controller;
123        #interrupt-cells = <1>;
124
125        #address-cells = <1>;
126        #size-cells = <1>;
127        ranges;
128
129        display-controller@ae01000 {
130            compatible = "qcom,sm8350-dpu";
131            reg = <0x0ae01000 0x8f000>,
132                  <0x0aeb0000 0x2008>;
133            reg-names = "mdp", "vbif";
134
135            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
136                     <&gcc GCC_DISP_SF_AXI_CLK>,
137                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
138                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
139                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
140                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141            clock-names = "bus",
142                          "nrt_bus",
143                          "iface",
144                          "lut",
145                          "core",
146                          "vsync";
147
148            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
149            assigned-clock-rates = <19200000>;
150
151            operating-points-v2 = <&mdp_opp_table>;
152            power-domains = <&rpmhpd RPMHPD_MMCX>;
153
154            interrupt-parent = <&mdss>;
155            interrupts = <0>;
156
157            ports {
158                #address-cells = <1>;
159                #size-cells = <0>;
160
161                port@0 {
162                    reg = <0>;
163                    dpu_intf1_out: endpoint {
164                        remote-endpoint = <&dsi0_in>;
165                    };
166                };
167            };
168
169            mdp_opp_table: opp-table {
170                compatible = "operating-points-v2";
171
172                opp-200000000 {
173                    opp-hz = /bits/ 64 <200000000>;
174                    required-opps = <&rpmhpd_opp_low_svs>;
175                };
176
177                opp-300000000 {
178                    opp-hz = /bits/ 64 <300000000>;
179                    required-opps = <&rpmhpd_opp_svs>;
180                };
181
182                opp-345000000 {
183                    opp-hz = /bits/ 64 <345000000>;
184                    required-opps = <&rpmhpd_opp_svs_l1>;
185                };
186
187                opp-460000000 {
188                    opp-hz = /bits/ 64 <460000000>;
189                    required-opps = <&rpmhpd_opp_nom>;
190                };
191            };
192        };
193
194        dsi0: dsi@ae94000 {
195            compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
196            reg = <0x0ae94000 0x400>;
197            reg-names = "dsi_ctrl";
198
199            interrupt-parent = <&mdss>;
200            interrupts = <4>;
201
202            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
203                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
204                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
205                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
206                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
207                     <&gcc GCC_DISP_HF_AXI_CLK>;
208            clock-names = "byte",
209                      "byte_intf",
210                      "pixel",
211                      "core",
212                      "iface",
213                      "bus";
214
215            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
216                          <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
217            assigned-clock-parents = <&mdss_dsi0_phy 0>,
218                                 <&mdss_dsi0_phy 1>;
219
220            operating-points-v2 = <&dsi_opp_table>;
221            power-domains = <&rpmhpd RPMHPD_MMCX>;
222
223            phys = <&mdss_dsi0_phy>;
224
225            ports {
226             #address-cells = <1>;
227                #size-cells = <0>;
228
229                port@0 {
230                    reg = <0>;
231                    dsi0_in: endpoint {
232                        remote-endpoint = <&dpu_intf1_out>;
233                    };
234                };
235
236                port@1 {
237                    reg = <1>;
238                    dsi0_out: endpoint {
239                    };
240                };
241            };
242        };
243    };
244...
245