1*708ba111SLaurentiu Palcu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*708ba111SLaurentiu Palcu# Copyright 2019 NXP 3*708ba111SLaurentiu Palcu%YAML 1.2 4*708ba111SLaurentiu Palcu--- 5*708ba111SLaurentiu Palcu$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" 6*708ba111SLaurentiu Palcu$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*708ba111SLaurentiu Palcu 8*708ba111SLaurentiu Palcutitle: iMX8MQ Display Controller Subsystem (DCSS) 9*708ba111SLaurentiu Palcu 10*708ba111SLaurentiu Palcumaintainers: 11*708ba111SLaurentiu Palcu - Laurentiu Palcu <laurentiu.palcu@nxp.com> 12*708ba111SLaurentiu Palcu 13*708ba111SLaurentiu Palcudescription: 14*708ba111SLaurentiu Palcu 15*708ba111SLaurentiu Palcu The DCSS (display controller sub system) is used to source up to three 16*708ba111SLaurentiu Palcu display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP 17*708ba111SLaurentiu Palcu 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 18*708ba111SLaurentiu Palcu image processing capabilities are included to provide a solution capable of 19*708ba111SLaurentiu Palcu driving next generation high dynamic range displays. 20*708ba111SLaurentiu Palcu 21*708ba111SLaurentiu Palcuproperties: 22*708ba111SLaurentiu Palcu compatible: 23*708ba111SLaurentiu Palcu const: nxp,imx8mq-dcss 24*708ba111SLaurentiu Palcu 25*708ba111SLaurentiu Palcu reg: 26*708ba111SLaurentiu Palcu items: 27*708ba111SLaurentiu Palcu - description: DCSS base address and size, up to IRQ steer start 28*708ba111SLaurentiu Palcu - description: DCSS BLKCTL base address and size 29*708ba111SLaurentiu Palcu 30*708ba111SLaurentiu Palcu interrupts: 31*708ba111SLaurentiu Palcu items: 32*708ba111SLaurentiu Palcu - description: Context loader completion and error interrupt 33*708ba111SLaurentiu Palcu - description: DTG interrupt used to signal context loader trigger time 34*708ba111SLaurentiu Palcu - description: DTG interrupt for Vblank 35*708ba111SLaurentiu Palcu 36*708ba111SLaurentiu Palcu interrupt-names: 37*708ba111SLaurentiu Palcu items: 38*708ba111SLaurentiu Palcu - const: ctxld 39*708ba111SLaurentiu Palcu - const: ctxld_kick 40*708ba111SLaurentiu Palcu - const: vblank 41*708ba111SLaurentiu Palcu 42*708ba111SLaurentiu Palcu clocks: 43*708ba111SLaurentiu Palcu items: 44*708ba111SLaurentiu Palcu - description: Display APB clock for all peripheral PIO access interfaces 45*708ba111SLaurentiu Palcu - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL 46*708ba111SLaurentiu Palcu - description: RTRAM clock 47*708ba111SLaurentiu Palcu - description: Pixel clock, can be driven either by HDMI phy clock or MIPI 48*708ba111SLaurentiu Palcu - description: DTRC clock, needed by video decompressor 49*708ba111SLaurentiu Palcu 50*708ba111SLaurentiu Palcu clock-names: 51*708ba111SLaurentiu Palcu items: 52*708ba111SLaurentiu Palcu - const: apb 53*708ba111SLaurentiu Palcu - const: axi 54*708ba111SLaurentiu Palcu - const: rtrm 55*708ba111SLaurentiu Palcu - const: pix 56*708ba111SLaurentiu Palcu - const: dtrc 57*708ba111SLaurentiu Palcu 58*708ba111SLaurentiu Palcu assigned-clocks: 59*708ba111SLaurentiu Palcu items: 60*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT 61*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM 62*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or 63*708ba111SLaurentiu Palcu IMX8MQ_VIDEO_PLL1_REF_SEL 64*708ba111SLaurentiu Palcu 65*708ba111SLaurentiu Palcu assigned-clock-parents: 66*708ba111SLaurentiu Palcu items: 67*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M 68*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M 69*708ba111SLaurentiu Palcu - description: Phandle and clock specifier of IMX8MQ_CLK_27M 70*708ba111SLaurentiu Palcu 71*708ba111SLaurentiu Palcu assigned-clock-rates: 72*708ba111SLaurentiu Palcu items: 73*708ba111SLaurentiu Palcu - description: Must be 800 MHz 74*708ba111SLaurentiu Palcu - description: Must be 400 MHz 75*708ba111SLaurentiu Palcu 76*708ba111SLaurentiu Palcu port: 77*708ba111SLaurentiu Palcu type: object 78*708ba111SLaurentiu Palcu description: 79*708ba111SLaurentiu Palcu A port node pointing to the input port of a HDMI/DP or MIPI display bridge. 80*708ba111SLaurentiu Palcu 81*708ba111SLaurentiu PalcuadditionalProperties: false 82*708ba111SLaurentiu Palcu 83*708ba111SLaurentiu Palcuexamples: 84*708ba111SLaurentiu Palcu - | 85*708ba111SLaurentiu Palcu #include <dt-bindings/clock/imx8mq-clock.h> 86*708ba111SLaurentiu Palcu dcss: display-controller@32e00000 { 87*708ba111SLaurentiu Palcu compatible = "nxp,imx8mq-dcss"; 88*708ba111SLaurentiu Palcu reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; 89*708ba111SLaurentiu Palcu interrupts = <6>, <8>, <9>; 90*708ba111SLaurentiu Palcu interrupt-names = "ctxld", "ctxld_kick", "vblank"; 91*708ba111SLaurentiu Palcu interrupt-parent = <&irqsteer>; 92*708ba111SLaurentiu Palcu clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, 93*708ba111SLaurentiu Palcu <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>, 94*708ba111SLaurentiu Palcu <&clk IMX8MQ_CLK_DISP_DTRC>; 95*708ba111SLaurentiu Palcu clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; 96*708ba111SLaurentiu Palcu assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>, 97*708ba111SLaurentiu Palcu <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; 98*708ba111SLaurentiu Palcu assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, 99*708ba111SLaurentiu Palcu <&clk IMX8MQ_CLK_27M>; 100*708ba111SLaurentiu Palcu assigned-clock-rates = <800000000>, 101*708ba111SLaurentiu Palcu <400000000>; 102*708ba111SLaurentiu Palcu port { 103*708ba111SLaurentiu Palcu dcss_out: endpoint { 104*708ba111SLaurentiu Palcu remote-endpoint = <&hdmi_in>; 105*708ba111SLaurentiu Palcu }; 106*708ba111SLaurentiu Palcu }; 107*708ba111SLaurentiu Palcu }; 108*708ba111SLaurentiu Palcu 109