1*124e46a8SAtish Patra=========================================== 2*124e46a8SAtish PatraCPU topology binding description 3*124e46a8SAtish Patra=========================================== 4*124e46a8SAtish Patra 5*124e46a8SAtish Patra=========================================== 6*124e46a8SAtish Patra1 - Introduction 7*124e46a8SAtish Patra=========================================== 8*124e46a8SAtish Patra 9*124e46a8SAtish PatraIn a SMP system, the hierarchy of CPUs is defined through three entities that 10*124e46a8SAtish Patraare used to describe the layout of physical CPUs in the system: 11*124e46a8SAtish Patra 12*124e46a8SAtish Patra- socket 13*124e46a8SAtish Patra- cluster 14*124e46a8SAtish Patra- core 15*124e46a8SAtish Patra- thread 16*124e46a8SAtish Patra 17*124e46a8SAtish PatraThe bottom hierarchy level sits at core or thread level depending on whether 18*124e46a8SAtish Patrasymmetric multi-threading (SMT) is supported or not. 19*124e46a8SAtish Patra 20*124e46a8SAtish PatraFor instance in a system where CPUs support SMT, "cpu" nodes represent all 21*124e46a8SAtish Patrathreads existing in the system and map to the hierarchy level "thread" above. 22*124e46a8SAtish PatraIn systems where SMT is not supported "cpu" nodes represent all cores present 23*124e46a8SAtish Patrain the system and map to the hierarchy level "core" above. 24*124e46a8SAtish Patra 25*124e46a8SAtish PatraCPU topology bindings allow one to associate cpu nodes with hierarchical groups 26*124e46a8SAtish Patracorresponding to the system hierarchy; syntactically they are defined as device 27*124e46a8SAtish Patratree nodes. 28*124e46a8SAtish Patra 29*124e46a8SAtish PatraCurrently, only ARM/RISC-V intend to use this cpu topology binding but it may be 30*124e46a8SAtish Patraused for any other architecture as well. 31*124e46a8SAtish Patra 32*124e46a8SAtish PatraThe cpu nodes, as per bindings defined in [4], represent the devices that 33*124e46a8SAtish Patracorrespond to physical CPUs and are to be mapped to the hierarchy levels. 34*124e46a8SAtish Patra 35*124e46a8SAtish PatraA topology description containing phandles to cpu nodes that are not compliant 36*124e46a8SAtish Patrawith bindings standardized in [4] is therefore considered invalid. 37*124e46a8SAtish Patra 38*124e46a8SAtish Patra=========================================== 39*124e46a8SAtish Patra2 - cpu-map node 40*124e46a8SAtish Patra=========================================== 41*124e46a8SAtish Patra 42*124e46a8SAtish PatraThe ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct 43*124e46a8SAtish Patrachild of the cpus node and provides a container where the actual topology 44*124e46a8SAtish Patranodes are listed. 45*124e46a8SAtish Patra 46*124e46a8SAtish Patra- cpu-map node 47*124e46a8SAtish Patra 48*124e46a8SAtish Patra Usage: Optional - On SMP systems provide CPUs topology to the OS. 49*124e46a8SAtish Patra Uniprocessor systems do not require a topology 50*124e46a8SAtish Patra description and therefore should not define a 51*124e46a8SAtish Patra cpu-map node. 52*124e46a8SAtish Patra 53*124e46a8SAtish Patra Description: The cpu-map node is just a container node where its 54*124e46a8SAtish Patra subnodes describe the CPU topology. 55*124e46a8SAtish Patra 56*124e46a8SAtish Patra Node name must be "cpu-map". 57*124e46a8SAtish Patra 58*124e46a8SAtish Patra The cpu-map node's parent node must be the cpus node. 59*124e46a8SAtish Patra 60*124e46a8SAtish Patra The cpu-map node's child nodes can be: 61*124e46a8SAtish Patra 62*124e46a8SAtish Patra - one or more cluster nodes or 63*124e46a8SAtish Patra - one or more socket nodes in a multi-socket system 64*124e46a8SAtish Patra 65*124e46a8SAtish Patra Any other configuration is considered invalid. 66*124e46a8SAtish Patra 67*124e46a8SAtish PatraThe cpu-map node can only contain 4 types of child nodes: 68*124e46a8SAtish Patra 69*124e46a8SAtish Patra- socket node 70*124e46a8SAtish Patra- cluster node 71*124e46a8SAtish Patra- core node 72*124e46a8SAtish Patra- thread node 73*124e46a8SAtish Patra 74*124e46a8SAtish Patrawhose bindings are described in paragraph 3. 75*124e46a8SAtish Patra 76*124e46a8SAtish PatraThe nodes describing the CPU topology (socket/cluster/core/thread) can 77*124e46a8SAtish Patraonly be defined within the cpu-map node and every core/thread in the 78*124e46a8SAtish Patrasystem must be defined within the topology. Any other configuration is 79*124e46a8SAtish Patrainvalid and therefore must be ignored. 80*124e46a8SAtish Patra 81*124e46a8SAtish Patra=========================================== 82*124e46a8SAtish Patra2.1 - cpu-map child nodes naming convention 83*124e46a8SAtish Patra=========================================== 84*124e46a8SAtish Patra 85*124e46a8SAtish Patracpu-map child nodes must follow a naming convention where the node name 86*124e46a8SAtish Patramust be "socketN", "clusterN", "coreN", "threadN" depending on the node type 87*124e46a8SAtish Patra(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes 88*124e46a8SAtish Patrawhich are siblings within a single common parent node must be given a unique and 89*124e46a8SAtish Patrasequential N value, starting from 0). 90*124e46a8SAtish Patracpu-map child nodes which do not share a common parent node can have the same 91*124e46a8SAtish Patraname (ie same number N as other cpu-map child nodes at different device tree 92*124e46a8SAtish Patralevels) since name uniqueness will be guaranteed by the device tree hierarchy. 93*124e46a8SAtish Patra 94*124e46a8SAtish Patra=========================================== 95*124e46a8SAtish Patra3 - socket/cluster/core/thread node bindings 96*124e46a8SAtish Patra=========================================== 97*124e46a8SAtish Patra 98*124e46a8SAtish PatraBindings for socket/cluster/cpu/thread nodes are defined as follows: 99*124e46a8SAtish Patra 100*124e46a8SAtish Patra- socket node 101*124e46a8SAtish Patra 102*124e46a8SAtish Patra Description: must be declared within a cpu-map node, one node 103*124e46a8SAtish Patra per physical socket in the system. A system can 104*124e46a8SAtish Patra contain single or multiple physical socket. 105*124e46a8SAtish Patra The association of sockets and NUMA nodes is beyond 106*124e46a8SAtish Patra the scope of this bindings, please refer [2] for 107*124e46a8SAtish Patra NUMA bindings. 108*124e46a8SAtish Patra 109*124e46a8SAtish Patra This node is optional for a single socket system. 110*124e46a8SAtish Patra 111*124e46a8SAtish Patra The socket node name must be "socketN" as described in 2.1 above. 112*124e46a8SAtish Patra A socket node can not be a leaf node. 113*124e46a8SAtish Patra 114*124e46a8SAtish Patra A socket node's child nodes must be one or more cluster nodes. 115*124e46a8SAtish Patra 116*124e46a8SAtish Patra Any other configuration is considered invalid. 117*124e46a8SAtish Patra 118*124e46a8SAtish Patra- cluster node 119*124e46a8SAtish Patra 120*124e46a8SAtish Patra Description: must be declared within a cpu-map node, one node 121*124e46a8SAtish Patra per cluster. A system can contain several layers of 122*124e46a8SAtish Patra clustering within a single physical socket and cluster 123*124e46a8SAtish Patra nodes can be contained in parent cluster nodes. 124*124e46a8SAtish Patra 125*124e46a8SAtish Patra The cluster node name must be "clusterN" as described in 2.1 above. 126*124e46a8SAtish Patra A cluster node can not be a leaf node. 127*124e46a8SAtish Patra 128*124e46a8SAtish Patra A cluster node's child nodes must be: 129*124e46a8SAtish Patra 130*124e46a8SAtish Patra - one or more cluster nodes; or 131*124e46a8SAtish Patra - one or more core nodes 132*124e46a8SAtish Patra 133*124e46a8SAtish Patra Any other configuration is considered invalid. 134*124e46a8SAtish Patra 135*124e46a8SAtish Patra- core node 136*124e46a8SAtish Patra 137*124e46a8SAtish Patra Description: must be declared in a cluster node, one node per core in 138*124e46a8SAtish Patra the cluster. If the system does not support SMT, core 139*124e46a8SAtish Patra nodes are leaf nodes, otherwise they become containers of 140*124e46a8SAtish Patra thread nodes. 141*124e46a8SAtish Patra 142*124e46a8SAtish Patra The core node name must be "coreN" as described in 2.1 above. 143*124e46a8SAtish Patra 144*124e46a8SAtish Patra A core node must be a leaf node if SMT is not supported. 145*124e46a8SAtish Patra 146*124e46a8SAtish Patra Properties for core nodes that are leaf nodes: 147*124e46a8SAtish Patra 148*124e46a8SAtish Patra - cpu 149*124e46a8SAtish Patra Usage: required 150*124e46a8SAtish Patra Value type: <phandle> 151*124e46a8SAtish Patra Definition: a phandle to the cpu node that corresponds to the 152*124e46a8SAtish Patra core node. 153*124e46a8SAtish Patra 154*124e46a8SAtish Patra If a core node is not a leaf node (CPUs supporting SMT) a core node's 155*124e46a8SAtish Patra child nodes can be: 156*124e46a8SAtish Patra 157*124e46a8SAtish Patra - one or more thread nodes 158*124e46a8SAtish Patra 159*124e46a8SAtish Patra Any other configuration is considered invalid. 160*124e46a8SAtish Patra 161*124e46a8SAtish Patra- thread node 162*124e46a8SAtish Patra 163*124e46a8SAtish Patra Description: must be declared in a core node, one node per thread 164*124e46a8SAtish Patra in the core if the system supports SMT. Thread nodes are 165*124e46a8SAtish Patra always leaf nodes in the device tree. 166*124e46a8SAtish Patra 167*124e46a8SAtish Patra The thread node name must be "threadN" as described in 2.1 above. 168*124e46a8SAtish Patra 169*124e46a8SAtish Patra A thread node must be a leaf node. 170*124e46a8SAtish Patra 171*124e46a8SAtish Patra A thread node must contain the following property: 172*124e46a8SAtish Patra 173*124e46a8SAtish Patra - cpu 174*124e46a8SAtish Patra Usage: required 175*124e46a8SAtish Patra Value type: <phandle> 176*124e46a8SAtish Patra Definition: a phandle to the cpu node that corresponds to 177*124e46a8SAtish Patra the thread node. 178*124e46a8SAtish Patra 179*124e46a8SAtish Patra=========================================== 180*124e46a8SAtish Patra4 - Example dts 181*124e46a8SAtish Patra=========================================== 182*124e46a8SAtish Patra 183*124e46a8SAtish PatraExample 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single 184*124e46a8SAtish Patraphysical socket): 185*124e46a8SAtish Patra 186*124e46a8SAtish Patracpus { 187*124e46a8SAtish Patra #size-cells = <0>; 188*124e46a8SAtish Patra #address-cells = <2>; 189*124e46a8SAtish Patra 190*124e46a8SAtish Patra cpu-map { 191*124e46a8SAtish Patra socket0 { 192*124e46a8SAtish Patra cluster0 { 193*124e46a8SAtish Patra cluster0 { 194*124e46a8SAtish Patra core0 { 195*124e46a8SAtish Patra thread0 { 196*124e46a8SAtish Patra cpu = <&CPU0>; 197*124e46a8SAtish Patra }; 198*124e46a8SAtish Patra thread1 { 199*124e46a8SAtish Patra cpu = <&CPU1>; 200*124e46a8SAtish Patra }; 201*124e46a8SAtish Patra }; 202*124e46a8SAtish Patra 203*124e46a8SAtish Patra core1 { 204*124e46a8SAtish Patra thread0 { 205*124e46a8SAtish Patra cpu = <&CPU2>; 206*124e46a8SAtish Patra }; 207*124e46a8SAtish Patra thread1 { 208*124e46a8SAtish Patra cpu = <&CPU3>; 209*124e46a8SAtish Patra }; 210*124e46a8SAtish Patra }; 211*124e46a8SAtish Patra }; 212*124e46a8SAtish Patra 213*124e46a8SAtish Patra cluster1 { 214*124e46a8SAtish Patra core0 { 215*124e46a8SAtish Patra thread0 { 216*124e46a8SAtish Patra cpu = <&CPU4>; 217*124e46a8SAtish Patra }; 218*124e46a8SAtish Patra thread1 { 219*124e46a8SAtish Patra cpu = <&CPU5>; 220*124e46a8SAtish Patra }; 221*124e46a8SAtish Patra }; 222*124e46a8SAtish Patra 223*124e46a8SAtish Patra core1 { 224*124e46a8SAtish Patra thread0 { 225*124e46a8SAtish Patra cpu = <&CPU6>; 226*124e46a8SAtish Patra }; 227*124e46a8SAtish Patra thread1 { 228*124e46a8SAtish Patra cpu = <&CPU7>; 229*124e46a8SAtish Patra }; 230*124e46a8SAtish Patra }; 231*124e46a8SAtish Patra }; 232*124e46a8SAtish Patra }; 233*124e46a8SAtish Patra 234*124e46a8SAtish Patra cluster1 { 235*124e46a8SAtish Patra cluster0 { 236*124e46a8SAtish Patra core0 { 237*124e46a8SAtish Patra thread0 { 238*124e46a8SAtish Patra cpu = <&CPU8>; 239*124e46a8SAtish Patra }; 240*124e46a8SAtish Patra thread1 { 241*124e46a8SAtish Patra cpu = <&CPU9>; 242*124e46a8SAtish Patra }; 243*124e46a8SAtish Patra }; 244*124e46a8SAtish Patra core1 { 245*124e46a8SAtish Patra thread0 { 246*124e46a8SAtish Patra cpu = <&CPU10>; 247*124e46a8SAtish Patra }; 248*124e46a8SAtish Patra thread1 { 249*124e46a8SAtish Patra cpu = <&CPU11>; 250*124e46a8SAtish Patra }; 251*124e46a8SAtish Patra }; 252*124e46a8SAtish Patra }; 253*124e46a8SAtish Patra 254*124e46a8SAtish Patra cluster1 { 255*124e46a8SAtish Patra core0 { 256*124e46a8SAtish Patra thread0 { 257*124e46a8SAtish Patra cpu = <&CPU12>; 258*124e46a8SAtish Patra }; 259*124e46a8SAtish Patra thread1 { 260*124e46a8SAtish Patra cpu = <&CPU13>; 261*124e46a8SAtish Patra }; 262*124e46a8SAtish Patra }; 263*124e46a8SAtish Patra core1 { 264*124e46a8SAtish Patra thread0 { 265*124e46a8SAtish Patra cpu = <&CPU14>; 266*124e46a8SAtish Patra }; 267*124e46a8SAtish Patra thread1 { 268*124e46a8SAtish Patra cpu = <&CPU15>; 269*124e46a8SAtish Patra }; 270*124e46a8SAtish Patra }; 271*124e46a8SAtish Patra }; 272*124e46a8SAtish Patra }; 273*124e46a8SAtish Patra }; 274*124e46a8SAtish Patra }; 275*124e46a8SAtish Patra 276*124e46a8SAtish Patra CPU0: cpu@0 { 277*124e46a8SAtish Patra device_type = "cpu"; 278*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 279*124e46a8SAtish Patra reg = <0x0 0x0>; 280*124e46a8SAtish Patra enable-method = "spin-table"; 281*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 282*124e46a8SAtish Patra }; 283*124e46a8SAtish Patra 284*124e46a8SAtish Patra CPU1: cpu@1 { 285*124e46a8SAtish Patra device_type = "cpu"; 286*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 287*124e46a8SAtish Patra reg = <0x0 0x1>; 288*124e46a8SAtish Patra enable-method = "spin-table"; 289*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 290*124e46a8SAtish Patra }; 291*124e46a8SAtish Patra 292*124e46a8SAtish Patra CPU2: cpu@100 { 293*124e46a8SAtish Patra device_type = "cpu"; 294*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 295*124e46a8SAtish Patra reg = <0x0 0x100>; 296*124e46a8SAtish Patra enable-method = "spin-table"; 297*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 298*124e46a8SAtish Patra }; 299*124e46a8SAtish Patra 300*124e46a8SAtish Patra CPU3: cpu@101 { 301*124e46a8SAtish Patra device_type = "cpu"; 302*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 303*124e46a8SAtish Patra reg = <0x0 0x101>; 304*124e46a8SAtish Patra enable-method = "spin-table"; 305*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 306*124e46a8SAtish Patra }; 307*124e46a8SAtish Patra 308*124e46a8SAtish Patra CPU4: cpu@10000 { 309*124e46a8SAtish Patra device_type = "cpu"; 310*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 311*124e46a8SAtish Patra reg = <0x0 0x10000>; 312*124e46a8SAtish Patra enable-method = "spin-table"; 313*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 314*124e46a8SAtish Patra }; 315*124e46a8SAtish Patra 316*124e46a8SAtish Patra CPU5: cpu@10001 { 317*124e46a8SAtish Patra device_type = "cpu"; 318*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 319*124e46a8SAtish Patra reg = <0x0 0x10001>; 320*124e46a8SAtish Patra enable-method = "spin-table"; 321*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 322*124e46a8SAtish Patra }; 323*124e46a8SAtish Patra 324*124e46a8SAtish Patra CPU6: cpu@10100 { 325*124e46a8SAtish Patra device_type = "cpu"; 326*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 327*124e46a8SAtish Patra reg = <0x0 0x10100>; 328*124e46a8SAtish Patra enable-method = "spin-table"; 329*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 330*124e46a8SAtish Patra }; 331*124e46a8SAtish Patra 332*124e46a8SAtish Patra CPU7: cpu@10101 { 333*124e46a8SAtish Patra device_type = "cpu"; 334*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 335*124e46a8SAtish Patra reg = <0x0 0x10101>; 336*124e46a8SAtish Patra enable-method = "spin-table"; 337*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 338*124e46a8SAtish Patra }; 339*124e46a8SAtish Patra 340*124e46a8SAtish Patra CPU8: cpu@100000000 { 341*124e46a8SAtish Patra device_type = "cpu"; 342*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 343*124e46a8SAtish Patra reg = <0x1 0x0>; 344*124e46a8SAtish Patra enable-method = "spin-table"; 345*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 346*124e46a8SAtish Patra }; 347*124e46a8SAtish Patra 348*124e46a8SAtish Patra CPU9: cpu@100000001 { 349*124e46a8SAtish Patra device_type = "cpu"; 350*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 351*124e46a8SAtish Patra reg = <0x1 0x1>; 352*124e46a8SAtish Patra enable-method = "spin-table"; 353*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 354*124e46a8SAtish Patra }; 355*124e46a8SAtish Patra 356*124e46a8SAtish Patra CPU10: cpu@100000100 { 357*124e46a8SAtish Patra device_type = "cpu"; 358*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 359*124e46a8SAtish Patra reg = <0x1 0x100>; 360*124e46a8SAtish Patra enable-method = "spin-table"; 361*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 362*124e46a8SAtish Patra }; 363*124e46a8SAtish Patra 364*124e46a8SAtish Patra CPU11: cpu@100000101 { 365*124e46a8SAtish Patra device_type = "cpu"; 366*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 367*124e46a8SAtish Patra reg = <0x1 0x101>; 368*124e46a8SAtish Patra enable-method = "spin-table"; 369*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 370*124e46a8SAtish Patra }; 371*124e46a8SAtish Patra 372*124e46a8SAtish Patra CPU12: cpu@100010000 { 373*124e46a8SAtish Patra device_type = "cpu"; 374*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 375*124e46a8SAtish Patra reg = <0x1 0x10000>; 376*124e46a8SAtish Patra enable-method = "spin-table"; 377*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 378*124e46a8SAtish Patra }; 379*124e46a8SAtish Patra 380*124e46a8SAtish Patra CPU13: cpu@100010001 { 381*124e46a8SAtish Patra device_type = "cpu"; 382*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 383*124e46a8SAtish Patra reg = <0x1 0x10001>; 384*124e46a8SAtish Patra enable-method = "spin-table"; 385*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 386*124e46a8SAtish Patra }; 387*124e46a8SAtish Patra 388*124e46a8SAtish Patra CPU14: cpu@100010100 { 389*124e46a8SAtish Patra device_type = "cpu"; 390*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 391*124e46a8SAtish Patra reg = <0x1 0x10100>; 392*124e46a8SAtish Patra enable-method = "spin-table"; 393*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 394*124e46a8SAtish Patra }; 395*124e46a8SAtish Patra 396*124e46a8SAtish Patra CPU15: cpu@100010101 { 397*124e46a8SAtish Patra device_type = "cpu"; 398*124e46a8SAtish Patra compatible = "arm,cortex-a57"; 399*124e46a8SAtish Patra reg = <0x1 0x10101>; 400*124e46a8SAtish Patra enable-method = "spin-table"; 401*124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 402*124e46a8SAtish Patra }; 403*124e46a8SAtish Patra}; 404*124e46a8SAtish Patra 405*124e46a8SAtish PatraExample 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): 406*124e46a8SAtish Patra 407*124e46a8SAtish Patracpus { 408*124e46a8SAtish Patra #size-cells = <0>; 409*124e46a8SAtish Patra #address-cells = <1>; 410*124e46a8SAtish Patra 411*124e46a8SAtish Patra cpu-map { 412*124e46a8SAtish Patra cluster0 { 413*124e46a8SAtish Patra core0 { 414*124e46a8SAtish Patra cpu = <&CPU0>; 415*124e46a8SAtish Patra }; 416*124e46a8SAtish Patra core1 { 417*124e46a8SAtish Patra cpu = <&CPU1>; 418*124e46a8SAtish Patra }; 419*124e46a8SAtish Patra core2 { 420*124e46a8SAtish Patra cpu = <&CPU2>; 421*124e46a8SAtish Patra }; 422*124e46a8SAtish Patra core3 { 423*124e46a8SAtish Patra cpu = <&CPU3>; 424*124e46a8SAtish Patra }; 425*124e46a8SAtish Patra }; 426*124e46a8SAtish Patra 427*124e46a8SAtish Patra cluster1 { 428*124e46a8SAtish Patra core0 { 429*124e46a8SAtish Patra cpu = <&CPU4>; 430*124e46a8SAtish Patra }; 431*124e46a8SAtish Patra core1 { 432*124e46a8SAtish Patra cpu = <&CPU5>; 433*124e46a8SAtish Patra }; 434*124e46a8SAtish Patra core2 { 435*124e46a8SAtish Patra cpu = <&CPU6>; 436*124e46a8SAtish Patra }; 437*124e46a8SAtish Patra core3 { 438*124e46a8SAtish Patra cpu = <&CPU7>; 439*124e46a8SAtish Patra }; 440*124e46a8SAtish Patra }; 441*124e46a8SAtish Patra }; 442*124e46a8SAtish Patra 443*124e46a8SAtish Patra CPU0: cpu@0 { 444*124e46a8SAtish Patra device_type = "cpu"; 445*124e46a8SAtish Patra compatible = "arm,cortex-a15"; 446*124e46a8SAtish Patra reg = <0x0>; 447*124e46a8SAtish Patra }; 448*124e46a8SAtish Patra 449*124e46a8SAtish Patra CPU1: cpu@1 { 450*124e46a8SAtish Patra device_type = "cpu"; 451*124e46a8SAtish Patra compatible = "arm,cortex-a15"; 452*124e46a8SAtish Patra reg = <0x1>; 453*124e46a8SAtish Patra }; 454*124e46a8SAtish Patra 455*124e46a8SAtish Patra CPU2: cpu@2 { 456*124e46a8SAtish Patra device_type = "cpu"; 457*124e46a8SAtish Patra compatible = "arm,cortex-a15"; 458*124e46a8SAtish Patra reg = <0x2>; 459*124e46a8SAtish Patra }; 460*124e46a8SAtish Patra 461*124e46a8SAtish Patra CPU3: cpu@3 { 462*124e46a8SAtish Patra device_type = "cpu"; 463*124e46a8SAtish Patra compatible = "arm,cortex-a15"; 464*124e46a8SAtish Patra reg = <0x3>; 465*124e46a8SAtish Patra }; 466*124e46a8SAtish Patra 467*124e46a8SAtish Patra CPU4: cpu@100 { 468*124e46a8SAtish Patra device_type = "cpu"; 469*124e46a8SAtish Patra compatible = "arm,cortex-a7"; 470*124e46a8SAtish Patra reg = <0x100>; 471*124e46a8SAtish Patra }; 472*124e46a8SAtish Patra 473*124e46a8SAtish Patra CPU5: cpu@101 { 474*124e46a8SAtish Patra device_type = "cpu"; 475*124e46a8SAtish Patra compatible = "arm,cortex-a7"; 476*124e46a8SAtish Patra reg = <0x101>; 477*124e46a8SAtish Patra }; 478*124e46a8SAtish Patra 479*124e46a8SAtish Patra CPU6: cpu@102 { 480*124e46a8SAtish Patra device_type = "cpu"; 481*124e46a8SAtish Patra compatible = "arm,cortex-a7"; 482*124e46a8SAtish Patra reg = <0x102>; 483*124e46a8SAtish Patra }; 484*124e46a8SAtish Patra 485*124e46a8SAtish Patra CPU7: cpu@103 { 486*124e46a8SAtish Patra device_type = "cpu"; 487*124e46a8SAtish Patra compatible = "arm,cortex-a7"; 488*124e46a8SAtish Patra reg = <0x103>; 489*124e46a8SAtish Patra }; 490*124e46a8SAtish Patra}; 491*124e46a8SAtish Patra 492*124e46a8SAtish PatraExample 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) 493*124e46a8SAtish Patra 494*124e46a8SAtish Patra{ 495*124e46a8SAtish Patra #address-cells = <2>; 496*124e46a8SAtish Patra #size-cells = <2>; 497*124e46a8SAtish Patra compatible = "sifive,fu540g", "sifive,fu500"; 498*124e46a8SAtish Patra model = "sifive,hifive-unleashed-a00"; 499*124e46a8SAtish Patra 500*124e46a8SAtish Patra ... 501*124e46a8SAtish Patra cpus { 502*124e46a8SAtish Patra #address-cells = <1>; 503*124e46a8SAtish Patra #size-cells = <0>; 504*124e46a8SAtish Patra cpu-map { 505*124e46a8SAtish Patra socket0 { 506*124e46a8SAtish Patra cluster0 { 507*124e46a8SAtish Patra core0 { 508*124e46a8SAtish Patra cpu = <&CPU1>; 509*124e46a8SAtish Patra }; 510*124e46a8SAtish Patra core1 { 511*124e46a8SAtish Patra cpu = <&CPU2>; 512*124e46a8SAtish Patra }; 513*124e46a8SAtish Patra core2 { 514*124e46a8SAtish Patra cpu0 = <&CPU2>; 515*124e46a8SAtish Patra }; 516*124e46a8SAtish Patra core3 { 517*124e46a8SAtish Patra cpu0 = <&CPU3>; 518*124e46a8SAtish Patra }; 519*124e46a8SAtish Patra }; 520*124e46a8SAtish Patra }; 521*124e46a8SAtish Patra }; 522*124e46a8SAtish Patra 523*124e46a8SAtish Patra CPU1: cpu@1 { 524*124e46a8SAtish Patra device_type = "cpu"; 525*124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 526*124e46a8SAtish Patra reg = <0x1>; 527*124e46a8SAtish Patra } 528*124e46a8SAtish Patra 529*124e46a8SAtish Patra CPU2: cpu@2 { 530*124e46a8SAtish Patra device_type = "cpu"; 531*124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 532*124e46a8SAtish Patra reg = <0x2>; 533*124e46a8SAtish Patra } 534*124e46a8SAtish Patra CPU3: cpu@3 { 535*124e46a8SAtish Patra device_type = "cpu"; 536*124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 537*124e46a8SAtish Patra reg = <0x3>; 538*124e46a8SAtish Patra } 539*124e46a8SAtish Patra CPU4: cpu@4 { 540*124e46a8SAtish Patra device_type = "cpu"; 541*124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 542*124e46a8SAtish Patra reg = <0x4>; 543*124e46a8SAtish Patra } 544*124e46a8SAtish Patra } 545*124e46a8SAtish Patra}; 546*124e46a8SAtish Patra=============================================================================== 547*124e46a8SAtish Patra[1] ARM Linux kernel documentation 548*124e46a8SAtish Patra Documentation/devicetree/bindings/arm/cpus.yaml 549*124e46a8SAtish Patra[2] Devicetree NUMA binding description 550*124e46a8SAtish Patra Documentation/devicetree/bindings/numa.txt 551*124e46a8SAtish Patra[3] RISC-V Linux kernel documentation 552*124e46a8SAtish Patra Documentation/devicetree/bindings/riscv/cpus.txt 553*124e46a8SAtish Patra[4] https://www.devicetree.org/specifications/ 554