1124e46a8SAtish Patra=========================================== 2124e46a8SAtish PatraCPU topology binding description 3124e46a8SAtish Patra=========================================== 4124e46a8SAtish Patra 5124e46a8SAtish Patra=========================================== 6124e46a8SAtish Patra1 - Introduction 7124e46a8SAtish Patra=========================================== 8124e46a8SAtish Patra 9124e46a8SAtish PatraIn a SMP system, the hierarchy of CPUs is defined through three entities that 10124e46a8SAtish Patraare used to describe the layout of physical CPUs in the system: 11124e46a8SAtish Patra 12124e46a8SAtish Patra- socket 13124e46a8SAtish Patra- cluster 14124e46a8SAtish Patra- core 15124e46a8SAtish Patra- thread 16124e46a8SAtish Patra 17124e46a8SAtish PatraThe bottom hierarchy level sits at core or thread level depending on whether 18124e46a8SAtish Patrasymmetric multi-threading (SMT) is supported or not. 19124e46a8SAtish Patra 20124e46a8SAtish PatraFor instance in a system where CPUs support SMT, "cpu" nodes represent all 21124e46a8SAtish Patrathreads existing in the system and map to the hierarchy level "thread" above. 22124e46a8SAtish PatraIn systems where SMT is not supported "cpu" nodes represent all cores present 23124e46a8SAtish Patrain the system and map to the hierarchy level "core" above. 24124e46a8SAtish Patra 25124e46a8SAtish PatraCPU topology bindings allow one to associate cpu nodes with hierarchical groups 26124e46a8SAtish Patracorresponding to the system hierarchy; syntactically they are defined as device 27124e46a8SAtish Patratree nodes. 28124e46a8SAtish Patra 29124e46a8SAtish PatraCurrently, only ARM/RISC-V intend to use this cpu topology binding but it may be 30124e46a8SAtish Patraused for any other architecture as well. 31124e46a8SAtish Patra 32124e46a8SAtish PatraThe cpu nodes, as per bindings defined in [4], represent the devices that 33124e46a8SAtish Patracorrespond to physical CPUs and are to be mapped to the hierarchy levels. 34124e46a8SAtish Patra 35124e46a8SAtish PatraA topology description containing phandles to cpu nodes that are not compliant 36124e46a8SAtish Patrawith bindings standardized in [4] is therefore considered invalid. 37124e46a8SAtish Patra 38124e46a8SAtish Patra=========================================== 39124e46a8SAtish Patra2 - cpu-map node 40124e46a8SAtish Patra=========================================== 41124e46a8SAtish Patra 42124e46a8SAtish PatraThe ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct 43124e46a8SAtish Patrachild of the cpus node and provides a container where the actual topology 44124e46a8SAtish Patranodes are listed. 45124e46a8SAtish Patra 46124e46a8SAtish Patra- cpu-map node 47124e46a8SAtish Patra 48124e46a8SAtish Patra Usage: Optional - On SMP systems provide CPUs topology to the OS. 49124e46a8SAtish Patra Uniprocessor systems do not require a topology 50124e46a8SAtish Patra description and therefore should not define a 51124e46a8SAtish Patra cpu-map node. 52124e46a8SAtish Patra 53124e46a8SAtish Patra Description: The cpu-map node is just a container node where its 54124e46a8SAtish Patra subnodes describe the CPU topology. 55124e46a8SAtish Patra 56124e46a8SAtish Patra Node name must be "cpu-map". 57124e46a8SAtish Patra 58124e46a8SAtish Patra The cpu-map node's parent node must be the cpus node. 59124e46a8SAtish Patra 60124e46a8SAtish Patra The cpu-map node's child nodes can be: 61124e46a8SAtish Patra 62124e46a8SAtish Patra - one or more cluster nodes or 63124e46a8SAtish Patra - one or more socket nodes in a multi-socket system 64124e46a8SAtish Patra 65124e46a8SAtish Patra Any other configuration is considered invalid. 66124e46a8SAtish Patra 67124e46a8SAtish PatraThe cpu-map node can only contain 4 types of child nodes: 68124e46a8SAtish Patra 69124e46a8SAtish Patra- socket node 70124e46a8SAtish Patra- cluster node 71124e46a8SAtish Patra- core node 72124e46a8SAtish Patra- thread node 73124e46a8SAtish Patra 74124e46a8SAtish Patrawhose bindings are described in paragraph 3. 75124e46a8SAtish Patra 76124e46a8SAtish PatraThe nodes describing the CPU topology (socket/cluster/core/thread) can 77124e46a8SAtish Patraonly be defined within the cpu-map node and every core/thread in the 78124e46a8SAtish Patrasystem must be defined within the topology. Any other configuration is 79124e46a8SAtish Patrainvalid and therefore must be ignored. 80124e46a8SAtish Patra 81124e46a8SAtish Patra=========================================== 82124e46a8SAtish Patra2.1 - cpu-map child nodes naming convention 83124e46a8SAtish Patra=========================================== 84124e46a8SAtish Patra 85124e46a8SAtish Patracpu-map child nodes must follow a naming convention where the node name 86124e46a8SAtish Patramust be "socketN", "clusterN", "coreN", "threadN" depending on the node type 87124e46a8SAtish Patra(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes 88124e46a8SAtish Patrawhich are siblings within a single common parent node must be given a unique and 89124e46a8SAtish Patrasequential N value, starting from 0). 90124e46a8SAtish Patracpu-map child nodes which do not share a common parent node can have the same 91124e46a8SAtish Patraname (ie same number N as other cpu-map child nodes at different device tree 92124e46a8SAtish Patralevels) since name uniqueness will be guaranteed by the device tree hierarchy. 93124e46a8SAtish Patra 94124e46a8SAtish Patra=========================================== 95124e46a8SAtish Patra3 - socket/cluster/core/thread node bindings 96124e46a8SAtish Patra=========================================== 97124e46a8SAtish Patra 98124e46a8SAtish PatraBindings for socket/cluster/cpu/thread nodes are defined as follows: 99124e46a8SAtish Patra 100124e46a8SAtish Patra- socket node 101124e46a8SAtish Patra 102124e46a8SAtish Patra Description: must be declared within a cpu-map node, one node 103124e46a8SAtish Patra per physical socket in the system. A system can 104124e46a8SAtish Patra contain single or multiple physical socket. 105124e46a8SAtish Patra The association of sockets and NUMA nodes is beyond 106124e46a8SAtish Patra the scope of this bindings, please refer [2] for 107124e46a8SAtish Patra NUMA bindings. 108124e46a8SAtish Patra 109124e46a8SAtish Patra This node is optional for a single socket system. 110124e46a8SAtish Patra 111124e46a8SAtish Patra The socket node name must be "socketN" as described in 2.1 above. 112124e46a8SAtish Patra A socket node can not be a leaf node. 113124e46a8SAtish Patra 114124e46a8SAtish Patra A socket node's child nodes must be one or more cluster nodes. 115124e46a8SAtish Patra 116124e46a8SAtish Patra Any other configuration is considered invalid. 117124e46a8SAtish Patra 118124e46a8SAtish Patra- cluster node 119124e46a8SAtish Patra 120124e46a8SAtish Patra Description: must be declared within a cpu-map node, one node 121124e46a8SAtish Patra per cluster. A system can contain several layers of 122124e46a8SAtish Patra clustering within a single physical socket and cluster 123124e46a8SAtish Patra nodes can be contained in parent cluster nodes. 124124e46a8SAtish Patra 125124e46a8SAtish Patra The cluster node name must be "clusterN" as described in 2.1 above. 126124e46a8SAtish Patra A cluster node can not be a leaf node. 127124e46a8SAtish Patra 128124e46a8SAtish Patra A cluster node's child nodes must be: 129124e46a8SAtish Patra 130124e46a8SAtish Patra - one or more cluster nodes; or 131124e46a8SAtish Patra - one or more core nodes 132124e46a8SAtish Patra 133124e46a8SAtish Patra Any other configuration is considered invalid. 134124e46a8SAtish Patra 135124e46a8SAtish Patra- core node 136124e46a8SAtish Patra 137124e46a8SAtish Patra Description: must be declared in a cluster node, one node per core in 138124e46a8SAtish Patra the cluster. If the system does not support SMT, core 139124e46a8SAtish Patra nodes are leaf nodes, otherwise they become containers of 140124e46a8SAtish Patra thread nodes. 141124e46a8SAtish Patra 142124e46a8SAtish Patra The core node name must be "coreN" as described in 2.1 above. 143124e46a8SAtish Patra 144124e46a8SAtish Patra A core node must be a leaf node if SMT is not supported. 145124e46a8SAtish Patra 146124e46a8SAtish Patra Properties for core nodes that are leaf nodes: 147124e46a8SAtish Patra 148124e46a8SAtish Patra - cpu 149124e46a8SAtish Patra Usage: required 150124e46a8SAtish Patra Value type: <phandle> 151124e46a8SAtish Patra Definition: a phandle to the cpu node that corresponds to the 152124e46a8SAtish Patra core node. 153124e46a8SAtish Patra 154124e46a8SAtish Patra If a core node is not a leaf node (CPUs supporting SMT) a core node's 155124e46a8SAtish Patra child nodes can be: 156124e46a8SAtish Patra 157124e46a8SAtish Patra - one or more thread nodes 158124e46a8SAtish Patra 159124e46a8SAtish Patra Any other configuration is considered invalid. 160124e46a8SAtish Patra 161124e46a8SAtish Patra- thread node 162124e46a8SAtish Patra 163124e46a8SAtish Patra Description: must be declared in a core node, one node per thread 164124e46a8SAtish Patra in the core if the system supports SMT. Thread nodes are 165124e46a8SAtish Patra always leaf nodes in the device tree. 166124e46a8SAtish Patra 167124e46a8SAtish Patra The thread node name must be "threadN" as described in 2.1 above. 168124e46a8SAtish Patra 169124e46a8SAtish Patra A thread node must be a leaf node. 170124e46a8SAtish Patra 171124e46a8SAtish Patra A thread node must contain the following property: 172124e46a8SAtish Patra 173124e46a8SAtish Patra - cpu 174124e46a8SAtish Patra Usage: required 175124e46a8SAtish Patra Value type: <phandle> 176124e46a8SAtish Patra Definition: a phandle to the cpu node that corresponds to 177124e46a8SAtish Patra the thread node. 178124e46a8SAtish Patra 179124e46a8SAtish Patra=========================================== 180124e46a8SAtish Patra4 - Example dts 181124e46a8SAtish Patra=========================================== 182124e46a8SAtish Patra 183124e46a8SAtish PatraExample 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single 184124e46a8SAtish Patraphysical socket): 185124e46a8SAtish Patra 186124e46a8SAtish Patracpus { 187124e46a8SAtish Patra #size-cells = <0>; 188124e46a8SAtish Patra #address-cells = <2>; 189124e46a8SAtish Patra 190124e46a8SAtish Patra cpu-map { 191124e46a8SAtish Patra socket0 { 192124e46a8SAtish Patra cluster0 { 193124e46a8SAtish Patra cluster0 { 194124e46a8SAtish Patra core0 { 195124e46a8SAtish Patra thread0 { 196124e46a8SAtish Patra cpu = <&CPU0>; 197124e46a8SAtish Patra }; 198124e46a8SAtish Patra thread1 { 199124e46a8SAtish Patra cpu = <&CPU1>; 200124e46a8SAtish Patra }; 201124e46a8SAtish Patra }; 202124e46a8SAtish Patra 203124e46a8SAtish Patra core1 { 204124e46a8SAtish Patra thread0 { 205124e46a8SAtish Patra cpu = <&CPU2>; 206124e46a8SAtish Patra }; 207124e46a8SAtish Patra thread1 { 208124e46a8SAtish Patra cpu = <&CPU3>; 209124e46a8SAtish Patra }; 210124e46a8SAtish Patra }; 211124e46a8SAtish Patra }; 212124e46a8SAtish Patra 213124e46a8SAtish Patra cluster1 { 214124e46a8SAtish Patra core0 { 215124e46a8SAtish Patra thread0 { 216124e46a8SAtish Patra cpu = <&CPU4>; 217124e46a8SAtish Patra }; 218124e46a8SAtish Patra thread1 { 219124e46a8SAtish Patra cpu = <&CPU5>; 220124e46a8SAtish Patra }; 221124e46a8SAtish Patra }; 222124e46a8SAtish Patra 223124e46a8SAtish Patra core1 { 224124e46a8SAtish Patra thread0 { 225124e46a8SAtish Patra cpu = <&CPU6>; 226124e46a8SAtish Patra }; 227124e46a8SAtish Patra thread1 { 228124e46a8SAtish Patra cpu = <&CPU7>; 229124e46a8SAtish Patra }; 230124e46a8SAtish Patra }; 231124e46a8SAtish Patra }; 232124e46a8SAtish Patra }; 233124e46a8SAtish Patra 234124e46a8SAtish Patra cluster1 { 235124e46a8SAtish Patra cluster0 { 236124e46a8SAtish Patra core0 { 237124e46a8SAtish Patra thread0 { 238124e46a8SAtish Patra cpu = <&CPU8>; 239124e46a8SAtish Patra }; 240124e46a8SAtish Patra thread1 { 241124e46a8SAtish Patra cpu = <&CPU9>; 242124e46a8SAtish Patra }; 243124e46a8SAtish Patra }; 244124e46a8SAtish Patra core1 { 245124e46a8SAtish Patra thread0 { 246124e46a8SAtish Patra cpu = <&CPU10>; 247124e46a8SAtish Patra }; 248124e46a8SAtish Patra thread1 { 249124e46a8SAtish Patra cpu = <&CPU11>; 250124e46a8SAtish Patra }; 251124e46a8SAtish Patra }; 252124e46a8SAtish Patra }; 253124e46a8SAtish Patra 254124e46a8SAtish Patra cluster1 { 255124e46a8SAtish Patra core0 { 256124e46a8SAtish Patra thread0 { 257124e46a8SAtish Patra cpu = <&CPU12>; 258124e46a8SAtish Patra }; 259124e46a8SAtish Patra thread1 { 260124e46a8SAtish Patra cpu = <&CPU13>; 261124e46a8SAtish Patra }; 262124e46a8SAtish Patra }; 263124e46a8SAtish Patra core1 { 264124e46a8SAtish Patra thread0 { 265124e46a8SAtish Patra cpu = <&CPU14>; 266124e46a8SAtish Patra }; 267124e46a8SAtish Patra thread1 { 268124e46a8SAtish Patra cpu = <&CPU15>; 269124e46a8SAtish Patra }; 270124e46a8SAtish Patra }; 271124e46a8SAtish Patra }; 272124e46a8SAtish Patra }; 273124e46a8SAtish Patra }; 274124e46a8SAtish Patra }; 275124e46a8SAtish Patra 276124e46a8SAtish Patra CPU0: cpu@0 { 277124e46a8SAtish Patra device_type = "cpu"; 278124e46a8SAtish Patra compatible = "arm,cortex-a57"; 279124e46a8SAtish Patra reg = <0x0 0x0>; 280124e46a8SAtish Patra enable-method = "spin-table"; 281124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 282124e46a8SAtish Patra }; 283124e46a8SAtish Patra 284124e46a8SAtish Patra CPU1: cpu@1 { 285124e46a8SAtish Patra device_type = "cpu"; 286124e46a8SAtish Patra compatible = "arm,cortex-a57"; 287124e46a8SAtish Patra reg = <0x0 0x1>; 288124e46a8SAtish Patra enable-method = "spin-table"; 289124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 290124e46a8SAtish Patra }; 291124e46a8SAtish Patra 292124e46a8SAtish Patra CPU2: cpu@100 { 293124e46a8SAtish Patra device_type = "cpu"; 294124e46a8SAtish Patra compatible = "arm,cortex-a57"; 295124e46a8SAtish Patra reg = <0x0 0x100>; 296124e46a8SAtish Patra enable-method = "spin-table"; 297124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 298124e46a8SAtish Patra }; 299124e46a8SAtish Patra 300124e46a8SAtish Patra CPU3: cpu@101 { 301124e46a8SAtish Patra device_type = "cpu"; 302124e46a8SAtish Patra compatible = "arm,cortex-a57"; 303124e46a8SAtish Patra reg = <0x0 0x101>; 304124e46a8SAtish Patra enable-method = "spin-table"; 305124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 306124e46a8SAtish Patra }; 307124e46a8SAtish Patra 308124e46a8SAtish Patra CPU4: cpu@10000 { 309124e46a8SAtish Patra device_type = "cpu"; 310124e46a8SAtish Patra compatible = "arm,cortex-a57"; 311124e46a8SAtish Patra reg = <0x0 0x10000>; 312124e46a8SAtish Patra enable-method = "spin-table"; 313124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 314124e46a8SAtish Patra }; 315124e46a8SAtish Patra 316124e46a8SAtish Patra CPU5: cpu@10001 { 317124e46a8SAtish Patra device_type = "cpu"; 318124e46a8SAtish Patra compatible = "arm,cortex-a57"; 319124e46a8SAtish Patra reg = <0x0 0x10001>; 320124e46a8SAtish Patra enable-method = "spin-table"; 321124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 322124e46a8SAtish Patra }; 323124e46a8SAtish Patra 324124e46a8SAtish Patra CPU6: cpu@10100 { 325124e46a8SAtish Patra device_type = "cpu"; 326124e46a8SAtish Patra compatible = "arm,cortex-a57"; 327124e46a8SAtish Patra reg = <0x0 0x10100>; 328124e46a8SAtish Patra enable-method = "spin-table"; 329124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 330124e46a8SAtish Patra }; 331124e46a8SAtish Patra 332124e46a8SAtish Patra CPU7: cpu@10101 { 333124e46a8SAtish Patra device_type = "cpu"; 334124e46a8SAtish Patra compatible = "arm,cortex-a57"; 335124e46a8SAtish Patra reg = <0x0 0x10101>; 336124e46a8SAtish Patra enable-method = "spin-table"; 337124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 338124e46a8SAtish Patra }; 339124e46a8SAtish Patra 340124e46a8SAtish Patra CPU8: cpu@100000000 { 341124e46a8SAtish Patra device_type = "cpu"; 342124e46a8SAtish Patra compatible = "arm,cortex-a57"; 343124e46a8SAtish Patra reg = <0x1 0x0>; 344124e46a8SAtish Patra enable-method = "spin-table"; 345124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 346124e46a8SAtish Patra }; 347124e46a8SAtish Patra 348124e46a8SAtish Patra CPU9: cpu@100000001 { 349124e46a8SAtish Patra device_type = "cpu"; 350124e46a8SAtish Patra compatible = "arm,cortex-a57"; 351124e46a8SAtish Patra reg = <0x1 0x1>; 352124e46a8SAtish Patra enable-method = "spin-table"; 353124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 354124e46a8SAtish Patra }; 355124e46a8SAtish Patra 356124e46a8SAtish Patra CPU10: cpu@100000100 { 357124e46a8SAtish Patra device_type = "cpu"; 358124e46a8SAtish Patra compatible = "arm,cortex-a57"; 359124e46a8SAtish Patra reg = <0x1 0x100>; 360124e46a8SAtish Patra enable-method = "spin-table"; 361124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 362124e46a8SAtish Patra }; 363124e46a8SAtish Patra 364124e46a8SAtish Patra CPU11: cpu@100000101 { 365124e46a8SAtish Patra device_type = "cpu"; 366124e46a8SAtish Patra compatible = "arm,cortex-a57"; 367124e46a8SAtish Patra reg = <0x1 0x101>; 368124e46a8SAtish Patra enable-method = "spin-table"; 369124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 370124e46a8SAtish Patra }; 371124e46a8SAtish Patra 372124e46a8SAtish Patra CPU12: cpu@100010000 { 373124e46a8SAtish Patra device_type = "cpu"; 374124e46a8SAtish Patra compatible = "arm,cortex-a57"; 375124e46a8SAtish Patra reg = <0x1 0x10000>; 376124e46a8SAtish Patra enable-method = "spin-table"; 377124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 378124e46a8SAtish Patra }; 379124e46a8SAtish Patra 380124e46a8SAtish Patra CPU13: cpu@100010001 { 381124e46a8SAtish Patra device_type = "cpu"; 382124e46a8SAtish Patra compatible = "arm,cortex-a57"; 383124e46a8SAtish Patra reg = <0x1 0x10001>; 384124e46a8SAtish Patra enable-method = "spin-table"; 385124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 386124e46a8SAtish Patra }; 387124e46a8SAtish Patra 388124e46a8SAtish Patra CPU14: cpu@100010100 { 389124e46a8SAtish Patra device_type = "cpu"; 390124e46a8SAtish Patra compatible = "arm,cortex-a57"; 391124e46a8SAtish Patra reg = <0x1 0x10100>; 392124e46a8SAtish Patra enable-method = "spin-table"; 393124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 394124e46a8SAtish Patra }; 395124e46a8SAtish Patra 396124e46a8SAtish Patra CPU15: cpu@100010101 { 397124e46a8SAtish Patra device_type = "cpu"; 398124e46a8SAtish Patra compatible = "arm,cortex-a57"; 399124e46a8SAtish Patra reg = <0x1 0x10101>; 400124e46a8SAtish Patra enable-method = "spin-table"; 401124e46a8SAtish Patra cpu-release-addr = <0 0x20000000>; 402124e46a8SAtish Patra }; 403124e46a8SAtish Patra}; 404124e46a8SAtish Patra 405124e46a8SAtish PatraExample 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): 406124e46a8SAtish Patra 407124e46a8SAtish Patracpus { 408124e46a8SAtish Patra #size-cells = <0>; 409124e46a8SAtish Patra #address-cells = <1>; 410124e46a8SAtish Patra 411124e46a8SAtish Patra cpu-map { 412124e46a8SAtish Patra cluster0 { 413124e46a8SAtish Patra core0 { 414124e46a8SAtish Patra cpu = <&CPU0>; 415124e46a8SAtish Patra }; 416124e46a8SAtish Patra core1 { 417124e46a8SAtish Patra cpu = <&CPU1>; 418124e46a8SAtish Patra }; 419124e46a8SAtish Patra core2 { 420124e46a8SAtish Patra cpu = <&CPU2>; 421124e46a8SAtish Patra }; 422124e46a8SAtish Patra core3 { 423124e46a8SAtish Patra cpu = <&CPU3>; 424124e46a8SAtish Patra }; 425124e46a8SAtish Patra }; 426124e46a8SAtish Patra 427124e46a8SAtish Patra cluster1 { 428124e46a8SAtish Patra core0 { 429124e46a8SAtish Patra cpu = <&CPU4>; 430124e46a8SAtish Patra }; 431124e46a8SAtish Patra core1 { 432124e46a8SAtish Patra cpu = <&CPU5>; 433124e46a8SAtish Patra }; 434124e46a8SAtish Patra core2 { 435124e46a8SAtish Patra cpu = <&CPU6>; 436124e46a8SAtish Patra }; 437124e46a8SAtish Patra core3 { 438124e46a8SAtish Patra cpu = <&CPU7>; 439124e46a8SAtish Patra }; 440124e46a8SAtish Patra }; 441124e46a8SAtish Patra }; 442124e46a8SAtish Patra 443124e46a8SAtish Patra CPU0: cpu@0 { 444124e46a8SAtish Patra device_type = "cpu"; 445124e46a8SAtish Patra compatible = "arm,cortex-a15"; 446124e46a8SAtish Patra reg = <0x0>; 447124e46a8SAtish Patra }; 448124e46a8SAtish Patra 449124e46a8SAtish Patra CPU1: cpu@1 { 450124e46a8SAtish Patra device_type = "cpu"; 451124e46a8SAtish Patra compatible = "arm,cortex-a15"; 452124e46a8SAtish Patra reg = <0x1>; 453124e46a8SAtish Patra }; 454124e46a8SAtish Patra 455124e46a8SAtish Patra CPU2: cpu@2 { 456124e46a8SAtish Patra device_type = "cpu"; 457124e46a8SAtish Patra compatible = "arm,cortex-a15"; 458124e46a8SAtish Patra reg = <0x2>; 459124e46a8SAtish Patra }; 460124e46a8SAtish Patra 461124e46a8SAtish Patra CPU3: cpu@3 { 462124e46a8SAtish Patra device_type = "cpu"; 463124e46a8SAtish Patra compatible = "arm,cortex-a15"; 464124e46a8SAtish Patra reg = <0x3>; 465124e46a8SAtish Patra }; 466124e46a8SAtish Patra 467124e46a8SAtish Patra CPU4: cpu@100 { 468124e46a8SAtish Patra device_type = "cpu"; 469124e46a8SAtish Patra compatible = "arm,cortex-a7"; 470124e46a8SAtish Patra reg = <0x100>; 471124e46a8SAtish Patra }; 472124e46a8SAtish Patra 473124e46a8SAtish Patra CPU5: cpu@101 { 474124e46a8SAtish Patra device_type = "cpu"; 475124e46a8SAtish Patra compatible = "arm,cortex-a7"; 476124e46a8SAtish Patra reg = <0x101>; 477124e46a8SAtish Patra }; 478124e46a8SAtish Patra 479124e46a8SAtish Patra CPU6: cpu@102 { 480124e46a8SAtish Patra device_type = "cpu"; 481124e46a8SAtish Patra compatible = "arm,cortex-a7"; 482124e46a8SAtish Patra reg = <0x102>; 483124e46a8SAtish Patra }; 484124e46a8SAtish Patra 485124e46a8SAtish Patra CPU7: cpu@103 { 486124e46a8SAtish Patra device_type = "cpu"; 487124e46a8SAtish Patra compatible = "arm,cortex-a7"; 488124e46a8SAtish Patra reg = <0x103>; 489124e46a8SAtish Patra }; 490124e46a8SAtish Patra}; 491124e46a8SAtish Patra 492124e46a8SAtish PatraExample 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) 493124e46a8SAtish Patra 494124e46a8SAtish Patra{ 495124e46a8SAtish Patra #address-cells = <2>; 496124e46a8SAtish Patra #size-cells = <2>; 497124e46a8SAtish Patra compatible = "sifive,fu540g", "sifive,fu500"; 498124e46a8SAtish Patra model = "sifive,hifive-unleashed-a00"; 499124e46a8SAtish Patra 500124e46a8SAtish Patra ... 501124e46a8SAtish Patra cpus { 502124e46a8SAtish Patra #address-cells = <1>; 503124e46a8SAtish Patra #size-cells = <0>; 504124e46a8SAtish Patra cpu-map { 505124e46a8SAtish Patra socket0 { 506124e46a8SAtish Patra cluster0 { 507124e46a8SAtish Patra core0 { 508124e46a8SAtish Patra cpu = <&CPU1>; 509124e46a8SAtish Patra }; 510124e46a8SAtish Patra core1 { 511124e46a8SAtish Patra cpu = <&CPU2>; 512124e46a8SAtish Patra }; 513124e46a8SAtish Patra core2 { 514124e46a8SAtish Patra cpu0 = <&CPU2>; 515124e46a8SAtish Patra }; 516124e46a8SAtish Patra core3 { 517124e46a8SAtish Patra cpu0 = <&CPU3>; 518124e46a8SAtish Patra }; 519124e46a8SAtish Patra }; 520124e46a8SAtish Patra }; 521124e46a8SAtish Patra }; 522124e46a8SAtish Patra 523124e46a8SAtish Patra CPU1: cpu@1 { 524124e46a8SAtish Patra device_type = "cpu"; 525124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 526124e46a8SAtish Patra reg = <0x1>; 527124e46a8SAtish Patra } 528124e46a8SAtish Patra 529124e46a8SAtish Patra CPU2: cpu@2 { 530124e46a8SAtish Patra device_type = "cpu"; 531124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 532124e46a8SAtish Patra reg = <0x2>; 533124e46a8SAtish Patra } 534124e46a8SAtish Patra CPU3: cpu@3 { 535124e46a8SAtish Patra device_type = "cpu"; 536124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 537124e46a8SAtish Patra reg = <0x3>; 538124e46a8SAtish Patra } 539124e46a8SAtish Patra CPU4: cpu@4 { 540124e46a8SAtish Patra device_type = "cpu"; 541124e46a8SAtish Patra compatible = "sifive,rocket0", "riscv"; 542124e46a8SAtish Patra reg = <0x4>; 543124e46a8SAtish Patra } 544124e46a8SAtish Patra } 545124e46a8SAtish Patra}; 546124e46a8SAtish Patra=============================================================================== 547124e46a8SAtish Patra[1] ARM Linux kernel documentation 548124e46a8SAtish Patra Documentation/devicetree/bindings/arm/cpus.yaml 549124e46a8SAtish Patra[2] Devicetree NUMA binding description 550124e46a8SAtish Patra Documentation/devicetree/bindings/numa.txt 551124e46a8SAtish Patra[3] RISC-V Linux kernel documentation 552*0ac624f4SMauro Carvalho Chehab Documentation/devicetree/bindings/riscv/cpus.yaml 553124e46a8SAtish Patra[4] https://www.devicetree.org/specifications/ 554