1*dc8ea920SConor Dooley# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*dc8ea920SConor Dooley# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 3*dc8ea920SConor Dooley%YAML 1.2 4*dc8ea920SConor Dooley--- 5*dc8ea920SConor Dooley$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml# 6*dc8ea920SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 7*dc8ea920SConor Dooley 8*dc8ea920SConor Dooleytitle: Baikal-T1 L2-cache Control Block 9*dc8ea920SConor Dooley 10*dc8ea920SConor Dooleymaintainers: 11*dc8ea920SConor Dooley - Serge Semin <fancer.lancer@gmail.com> 12*dc8ea920SConor Dooley 13*dc8ea920SConor Dooleydescription: | 14*dc8ea920SConor Dooley By means of the System Controller Baikal-T1 SoC exposes a few settings to 15*dc8ea920SConor Dooley tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible 16*dc8ea920SConor Dooley to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 17*dc8ea920SConor Dooley L2-cache controller block is responsible for the tuning. Its DT node is 18*dc8ea920SConor Dooley supposed to be a child of the system controller. 19*dc8ea920SConor Dooley 20*dc8ea920SConor Dooleyproperties: 21*dc8ea920SConor Dooley compatible: 22*dc8ea920SConor Dooley const: baikal,bt1-l2-ctl 23*dc8ea920SConor Dooley 24*dc8ea920SConor Dooley reg: 25*dc8ea920SConor Dooley maxItems: 1 26*dc8ea920SConor Dooley 27*dc8ea920SConor Dooley baikal,l2-ws-latency: 28*dc8ea920SConor Dooley $ref: /schemas/types.yaml#/definitions/uint32 29*dc8ea920SConor Dooley description: Cycles of latency for Way-select RAM accesses 30*dc8ea920SConor Dooley default: 0 31*dc8ea920SConor Dooley minimum: 0 32*dc8ea920SConor Dooley maximum: 3 33*dc8ea920SConor Dooley 34*dc8ea920SConor Dooley baikal,l2-tag-latency: 35*dc8ea920SConor Dooley $ref: /schemas/types.yaml#/definitions/uint32 36*dc8ea920SConor Dooley description: Cycles of latency for Tag RAM accesses 37*dc8ea920SConor Dooley default: 0 38*dc8ea920SConor Dooley minimum: 0 39*dc8ea920SConor Dooley maximum: 3 40*dc8ea920SConor Dooley 41*dc8ea920SConor Dooley baikal,l2-data-latency: 42*dc8ea920SConor Dooley $ref: /schemas/types.yaml#/definitions/uint32 43*dc8ea920SConor Dooley description: Cycles of latency for Data RAM accesses 44*dc8ea920SConor Dooley default: 1 45*dc8ea920SConor Dooley minimum: 0 46*dc8ea920SConor Dooley maximum: 3 47*dc8ea920SConor Dooley 48*dc8ea920SConor DooleyadditionalProperties: false 49*dc8ea920SConor Dooley 50*dc8ea920SConor Dooleyrequired: 51*dc8ea920SConor Dooley - compatible 52*dc8ea920SConor Dooley 53*dc8ea920SConor Dooleyexamples: 54*dc8ea920SConor Dooley - | 55*dc8ea920SConor Dooley l2@1f04d028 { 56*dc8ea920SConor Dooley compatible = "baikal,bt1-l2-ctl"; 57*dc8ea920SConor Dooley reg = <0x1f04d028 0x004>; 58*dc8ea920SConor Dooley 59*dc8ea920SConor Dooley baikal,l2-ws-latency = <1>; 60*dc8ea920SConor Dooley baikal,l2-tag-latency = <1>; 61*dc8ea920SConor Dooley baikal,l2-data-latency = <2>; 62*dc8ea920SConor Dooley }; 63*dc8ea920SConor Dooley... 64