1cba3c40dSFabien Parent# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2cba3c40dSFabien Parent%YAML 1.2 3cba3c40dSFabien Parent--- 44b71ed9fSRob Herring$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml# 54b71ed9fSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6cba3c40dSFabien Parent 7cba3c40dSFabien Parenttitle: MediaTek mmsys controller 8cba3c40dSFabien Parent 9cba3c40dSFabien Parentmaintainers: 10cba3c40dSFabien Parent - Matthias Brugger <matthias.bgg@gmail.com> 11cba3c40dSFabien Parent 12cba3c40dSFabien Parentdescription: 13cba3c40dSFabien Parent The MediaTek mmsys system controller provides clock control, routing control, 14cba3c40dSFabien Parent and miscellaneous control in mmsys partition. 15cba3c40dSFabien Parent 16cba3c40dSFabien Parentproperties: 17cba3c40dSFabien Parent $nodename: 18cba3c40dSFabien Parent pattern: "^syscon@[0-9a-f]+$" 19cba3c40dSFabien Parent 20cba3c40dSFabien Parent compatible: 21cba3c40dSFabien Parent oneOf: 22cba3c40dSFabien Parent - items: 23cba3c40dSFabien Parent - enum: 24cba3c40dSFabien Parent - mediatek,mt2701-mmsys 25cba3c40dSFabien Parent - mediatek,mt2712-mmsys 26cba3c40dSFabien Parent - mediatek,mt6765-mmsys 27cba3c40dSFabien Parent - mediatek,mt6779-mmsys 28d5099c95SAngeloGioacchino Del Regno - mediatek,mt6795-mmsys 29cba3c40dSFabien Parent - mediatek,mt6797-mmsys 30cba3c40dSFabien Parent - mediatek,mt8167-mmsys 31cba3c40dSFabien Parent - mediatek,mt8173-mmsys 32cba3c40dSFabien Parent - mediatek,mt8183-mmsys 33eb1b02beSRex-BC Chen - mediatek,mt8186-mmsys 342433c716SNathan Lu - mediatek,mt8188-vdosys0 35*41b3a96cSHsiao Chien Sung - mediatek,mt8188-vdosys1 3626bcd8a5Syu-chang.lee - mediatek,mt8188-vppsys0 3726bcd8a5Syu-chang.lee - mediatek,mt8188-vppsys1 3875d6e7d9SLinus Torvalds - mediatek,mt8192-mmsys 3982219cfbSNancy.Lin - mediatek,mt8195-vdosys1 401873da26SMoudy Ho - mediatek,mt8195-vppsys0 411873da26SMoudy Ho - mediatek,mt8195-vppsys1 42f72999f5SFabien Parent - mediatek,mt8365-mmsys 43cba3c40dSFabien Parent - const: syscon 44b237efd4SJason-JH.Lin 45b237efd4SJason-JH.Lin - description: vdosys0 and vdosys1 are 2 display HW pipelines, 46b237efd4SJason-JH.Lin so mt8195 binding should be deprecated. 47b237efd4SJason-JH.Lin deprecated: true 48b237efd4SJason-JH.Lin items: 49b237efd4SJason-JH.Lin - const: mediatek,mt8195-mmsys 50b237efd4SJason-JH.Lin - const: syscon 51b237efd4SJason-JH.Lin 52cba3c40dSFabien Parent - items: 53cba3c40dSFabien Parent - const: mediatek,mt7623-mmsys 54cba3c40dSFabien Parent - const: mediatek,mt2701-mmsys 55cba3c40dSFabien Parent - const: syscon 56cba3c40dSFabien Parent 57b237efd4SJason-JH.Lin - items: 58b237efd4SJason-JH.Lin - const: mediatek,mt8195-vdosys0 59b237efd4SJason-JH.Lin - const: mediatek,mt8195-mmsys 60b237efd4SJason-JH.Lin - const: syscon 61b237efd4SJason-JH.Lin 62cba3c40dSFabien Parent reg: 63cba3c40dSFabien Parent maxItems: 1 64cba3c40dSFabien Parent 651da90b8aSjason-jh.lin power-domains: 661da90b8aSjason-jh.lin description: 671da90b8aSjason-jh.lin A phandle and PM domain specifier as defined by bindings 681da90b8aSjason-jh.lin of the power controller specified by phandle. See 691da90b8aSjason-jh.lin Documentation/devicetree/bindings/power/power-domain.yaml for details. 701da90b8aSjason-jh.lin 711da90b8aSjason-jh.lin mboxes: 721da90b8aSjason-jh.lin description: 731da90b8aSjason-jh.lin Using mailbox to communicate with GCE, it should have this 741da90b8aSjason-jh.lin property and list of phandle, mailbox specifiers. See 75cd425807SAngeloGioacchino Del Regno Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml 76cd425807SAngeloGioacchino Del Regno for details. 771da90b8aSjason-jh.lin $ref: /schemas/types.yaml#/definitions/phandle-array 781da90b8aSjason-jh.lin 791da90b8aSjason-jh.lin mediatek,gce-client-reg: 801da90b8aSjason-jh.lin description: 811da90b8aSjason-jh.lin The register of client driver can be configured by gce with 4 arguments 821da90b8aSjason-jh.lin defined in this property, such as phandle of gce, subsys id, 831da90b8aSjason-jh.lin register offset and size. 841da90b8aSjason-jh.lin Each subsys id is mapping to a base address of display function blocks 851da90b8aSjason-jh.lin register which is defined in the gce header 861da90b8aSjason-jh.lin include/dt-bindings/gce/<chip>-gce.h. 871da90b8aSjason-jh.lin $ref: /schemas/types.yaml#/definitions/phandle-array 881da90b8aSjason-jh.lin maxItems: 1 891da90b8aSjason-jh.lin 90cba3c40dSFabien Parent "#clock-cells": 91cba3c40dSFabien Parent const: 1 92cba3c40dSFabien Parent 936046ffc3SEnric Balletbo i Serra '#reset-cells': 946046ffc3SEnric Balletbo i Serra const: 1 956046ffc3SEnric Balletbo i Serra 96cba3c40dSFabien Parentrequired: 97cba3c40dSFabien Parent - compatible 98cba3c40dSFabien Parent - reg 99cba3c40dSFabien Parent - "#clock-cells" 100cba3c40dSFabien Parent 101cba3c40dSFabien ParentadditionalProperties: false 102cba3c40dSFabien Parent 103cba3c40dSFabien Parentexamples: 104cba3c40dSFabien Parent - | 1051da90b8aSjason-jh.lin #include <dt-bindings/power/mt8173-power.h> 1061da90b8aSjason-jh.lin #include <dt-bindings/gce/mt8173-gce.h> 1071da90b8aSjason-jh.lin 108cba3c40dSFabien Parent mmsys: syscon@14000000 { 109cba3c40dSFabien Parent compatible = "mediatek,mt8173-mmsys", "syscon"; 110cba3c40dSFabien Parent reg = <0x14000000 0x1000>; 1111da90b8aSjason-jh.lin power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 112cba3c40dSFabien Parent #clock-cells = <1>; 1136046ffc3SEnric Balletbo i Serra #reset-cells = <1>; 1141da90b8aSjason-jh.lin mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1151da90b8aSjason-jh.lin <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1161da90b8aSjason-jh.lin mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 117cba3c40dSFabien Parent }; 118