1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MC_OPL_H 27 #define _SYS_MC_OPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/note.h> 36 37 #ifdef DEBUG 38 #define MC_LOG if (oplmc_debug) printf 39 extern int oplmc_debug; 40 #else 41 #define MC_LOG _NOTE(CONSTANTCONDITION) if (0) printf 42 #endif 43 44 /* 45 * load/store MAC register 46 */ 47 extern uint32_t mc_ldphysio(uint64_t); 48 extern void mc_stphysio(uint64_t, uint32_t); 49 #define LD_MAC_REG(paddr) mc_ldphysio(paddr) 50 #define ST_MAC_REG(paddr, data) mc_stphysio((paddr), (data)) 51 52 #define BANKNUM_PER_SB 8 53 54 typedef struct scf_log { 55 struct scf_log *sl_next; 56 int sl_bank; 57 uint32_t sl_err_add; 58 uint32_t sl_err_log; 59 } scf_log_t; 60 61 typedef struct mc_opl_state { 62 struct mc_opl_state *next; 63 dev_info_t *mc_dip; 64 uint32_t mc_status; 65 #define MC_POLL_RUNNING 0x1 66 #define MC_SOFT_SUSPENDED 0x2 /* suspended by DR */ 67 #define MC_DRIVER_SUSPENDED 0x4 /* DDI_SUSPEND */ 68 uint32_t mc_board_num; /* board# */ 69 uint64_t mc_start_address; /* sb-mem-ranges */ 70 uint64_t mc_size; 71 struct mc_bank { 72 uint32_t mcb_status; 73 #define BANK_INSTALLED 0x80000000 74 #define BANK_MIRROR_MODE 0x40000000 /* 0: normal 1: mirror */ 75 #define BANK_PTRL_RUNNING 0x00000001 76 uint64_t mcb_reg_base; 77 uint32_t mcb_ptrl_cntl; 78 } mc_bank[BANKNUM_PER_SB]; 79 uchar_t mc_trans_table[2][64]; /* csX-mac-pa-trans-table */ 80 clock_t mc_interval_hz; 81 timeout_id_t mc_tid; 82 kmutex_t mc_lock; 83 scf_log_t *mc_scf_log; 84 scf_log_t *mc_scf_log_tail; 85 int mc_scf_total; 86 #define MAX_SCF_LOGS 64 87 struct mc_inst_list *mc_list; 88 struct memlist *mlist; 89 int mc_scf_retry[BANKNUM_PER_SB]; 90 int mc_last_error; 91 #define MAX_SCF_RETRY 10 92 uint64_t mc_period; /* number of times memory scanned */ 93 } mc_opl_t; 94 95 typedef struct mc_inst_list { 96 struct mc_inst_list *next; 97 mc_opl_t *mc_opl; 98 uint32_t mc_board_num; 99 uint64_t mc_start_address; 100 uint64_t mc_size; 101 } mc_inst_list_t; 102 103 #define IS_MIRROR(mcp, bn) ((mcp)->mc_bank[bn].mcb_status\ 104 & BANK_MIRROR_MODE) 105 typedef struct mc_addr { 106 int ma_bd; /* board number */ 107 int ma_bank; /* bank number */ 108 uint32_t ma_dimm_addr; /* DIMM address (same format as ERR_ADD) */ 109 } mc_addr_t; 110 111 typedef struct mc_addr_info { 112 struct mc_addr mi_maddr; 113 int mi_valid; 114 int mi_advance; 115 } mc_addr_info_t; 116 117 typedef struct mc_flt_stat { 118 uint32_t mf_type; /* fault type */ 119 #define FLT_TYPE_CMPE 0x0001 120 #define FLT_TYPE_UE 0x0002 121 #define FLT_TYPE_PERMANENT_CE 0x0003 122 #define FLT_TYPE_INTERMITTENT_CE 0x0004 123 #define FLT_TYPE_SUE 0x0005 124 #define FLT_TYPE_MUE 0x0006 125 uint32_t mf_cntl; /* MAC_BANKm_PTRL_CNTL Register */ 126 uint32_t mf_err_add; /* MAC_BANKm_{PTRL|MI}_ERR_ADD Register */ 127 uint32_t mf_err_log; /* MAC_BANKm_{PTRL|MI}_ERR_LOG Register */ 128 uint32_t mf_synd; 129 uchar_t mf_errlog_valid; 130 uchar_t mf_dimm_slot; 131 uchar_t mf_dram_place; 132 uint64_t mf_flt_paddr; /* faulty physical address */ 133 mc_addr_t mf_flt_maddr; /* faulty DIMM address */ 134 } mc_flt_stat_t; 135 136 typedef struct mc_aflt { 137 uint64_t mflt_id; /* gethrtime() at time of fault */ 138 mc_opl_t *mflt_mcp; /* mc-opl structure */ 139 char *mflt_erpt_class; /* ereport class name */ 140 int mflt_is_ptrl; /* detected by PTRL or MI */ 141 int mflt_nflts; /* 1 or 2 */ 142 int mflt_pr; /* page retire flags */ 143 mc_flt_stat_t *mflt_stat[2]; /* fault status */ 144 } mc_aflt_t; 145 146 #define MAC_PTRL_STAT(mcp, i) (mcp->mc_bank[i].mcb_reg_base) 147 #define MAC_PTRL_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x10) 148 #define MAC_PTRL_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x20) 149 #define MAC_PTRL_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x24) 150 #define MAC_MI_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x28) 151 #define MAC_MI_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x2c) 152 #define MAC_STATIC_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x30) 153 #define MAC_STATIC_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x34) 154 #define MAC_RESTART_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x40) 155 #define MAC_REWRITE_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x44) 156 #define MAC_EG_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x48) 157 #define MAC_EG_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x4c) 158 #define MAC_MIRR(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x50) 159 160 /* use PA[37:6] */ 161 #define MAC_RESTART_PA(pa) ((pa >> 6) & 0xffffffff) 162 /* 163 * MAC_BANKm_PTRL_STAT_Register 164 */ 165 #define MAC_STAT_PTRL_CE 0x00000020 166 #define MAC_STAT_PTRL_UE 0x00000010 167 #define MAC_STAT_PTRL_CMPE 0x00000008 168 #define MAC_STAT_MI_CE 0x00000004 169 #define MAC_STAT_MI_UE 0x00000002 170 #define MAC_STAT_MI_CMPE 0x00000001 171 172 #define MAC_STAT_PTRL_ERRS (MAC_STAT_PTRL_CE|MAC_STAT_PTRL_UE\ 173 |MAC_STAT_PTRL_CMPE) 174 #define MAC_STAT_MI_ERRS (MAC_STAT_MI_CE|MAC_STAT_MI_UE\ 175 |MAC_STAT_MI_CMPE) 176 177 /* 178 * MAC_BANKm_PTRL_CTRL_Register 179 */ 180 #define MAC_CNTL_PTRL_START 0x80000000 181 #define MAC_CNTL_USE_RESTART_ADD 0x40000000 182 #define MAC_CNTL_PTRL_STOP 0x20000000 183 #define MAC_CNTL_PTRL_INTERVAL 0x1c000000 184 #define MAC_CNTL_PTRL_RESET 0x02000000 185 #define MAC_CNTL_PTRL_STATUS 0x01000000 186 #define MAC_CNTL_REW_REQ 0x00800000 187 #define MAC_CNTL_REW_RESET 0x00400000 188 #define MAC_CNTL_CS0_DEG_MODE 0x00200000 189 #define MAC_CNTL_PTRL_CE 0x00008000 190 #define MAC_CNTL_PTRL_UE 0x00004000 191 #define MAC_CNTL_PTRL_CMPE 0x00002000 192 #define MAC_CNTL_MI_CE 0x00001000 193 #define MAC_CNTL_MI_UE 0x00000800 194 #define MAC_CNTL_MI_CMPE 0x00000400 195 #define MAC_CNTL_REW_CE 0x00000200 196 #define MAC_CNTL_REW_UE 0x00000100 197 #define MAC_CNTL_REW_END 0x00000080 198 #define MAC_CNTL_PTRL_ADD_MAX 0x00000040 199 #define MAC_CNTL_REW_CMPE 0x00000020 200 201 #define MAC_CNTL_PTRL_PRESERVE_BITS (MAC_CNTL_PTRL_INTERVAL) 202 203 #define MAC_CNTL_PTRL_ERRS (MAC_CNTL_PTRL_CE|MAC_CNTL_PTRL_UE\ 204 |MAC_CNTL_PTRL_CMPE) 205 #define MAC_CNTL_MI_ERRS (MAC_CNTL_MI_CE|MAC_CNTL_MI_UE\ 206 |MAC_CNTL_MI_CMPE) 207 #define MAC_CNTL_REW_ERRS (MAC_CNTL_REW_CE|MAC_CNTL_REW_CMPE|\ 208 MAC_CNTL_REW_UE|MAC_CNTL_REW_END) 209 #define MAC_CNTL_ALL_ERRS (MAC_CNTL_PTRL_ERRS|\ 210 MAC_CNTL_MI_ERRS|MAC_CNTL_REW_ERRS) 211 212 #define MAC_ERRLOG_SYND_SHIFT 16 213 #define MAC_ERRLOG_SYND_MASK 0xffff 214 #define MAC_ERRLOG_DIMMSLOT_SHIFT 13 215 #define MAC_ERRLOG_DIMMSLOT_MASK 0x7 216 #define MAC_ERRLOG_DRAM_PLACE_SHIFT 8 217 #define MAC_ERRLOG_DRAM_PLACE_MASK 0x1f 218 219 #define MAC_SET_ERRLOG_INFO(flt_stat) \ 220 (flt_stat)->mf_errlog_valid = 1; \ 221 (flt_stat)->mf_synd = ((flt_stat)->mf_err_log >> \ 222 MAC_ERRLOG_SYND_SHIFT) & \ 223 MAC_ERRLOG_SYND_MASK; \ 224 (flt_stat)->mf_dimm_slot = ((flt_stat)->mf_err_log >> \ 225 MAC_ERRLOG_DIMMSLOT_SHIFT) & \ 226 MAC_ERRLOG_DIMMSLOT_MASK; \ 227 (flt_stat)->mf_dram_place = ((flt_stat)->mf_err_log >> \ 228 MAC_ERRLOG_DRAM_PLACE_SHIFT) & \ 229 MAC_ERRLOG_DRAM_PLACE_MASK; 230 231 extern void mc_write_cntl(mc_opl_t *, int, uint32_t); 232 #define MAC_CMD(mcp, i, cmd) mc_write_cntl(mcp, i, cmd) 233 234 #define MAC_PTRL_START_ADD(mcp, i) MAC_CMD((mcp), (i),\ 235 MAC_CNTL_PTRL_START|MAC_CNTL_USE_RESTART_ADD) 236 #define MAC_PTRL_START(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_START) 237 #define MAC_PTRL_STOP(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_STOP) 238 #define MAC_PTRL_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_RESET) 239 #define MAC_REW_REQ(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_REQ) 240 #define MAC_REW_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_RESET) 241 #define MAC_CLEAR_ERRS(mcp, i, errs) MAC_CMD((mcp), (i), errs) 242 #define MAC_CLEAR_ALL_ERRS(mcp, i) MAC_CMD((mcp), (i),\ 243 MAC_CNTL_ALL_ERRS) 244 #define MAC_CLEAR_MAX(mcp, i) \ 245 MAC_CMD((mcp), (i), MAC_CNTL_PTRL_ADD_MAX) 246 247 248 /* 249 * MAC_BANKm_PTRL/MI_ERR_ADD/LOG_Register 250 */ 251 #define MAC_ERR_ADD_INVALID 0x80000000 252 #define MAC_ERR_LOG_INVALID 0x00000080 253 254 /* 255 * MAC_BANKm_STATIC_ERR_ADD_Register 256 */ 257 #define MAC_STATIC_ERR_VLD 0x80000000 258 259 /* 260 * MAC_BANKm_MIRR_Register 261 */ 262 #define MAC_MIRR_MIRROR_MODE 0x80000000 263 #define MAC_MIRR_BANK_EXCLUSIVE 0x40000000 264 265 #define OPL_BOARD_MAX 16 266 #define OPL_BANK_MAX 8 267 268 /* 269 * MAC_BANKm_EG_ADD_Register 270 */ 271 #define MAC_EG_ADD_MASK 0x7ffffffc 272 /* 273 * To set the EG_CNTL register, bit[26-25] and 274 * bit[21-20] must be cleared. Then the other 275 * control bit should be set. Then the bit[26-25] 276 * and bit[21-20] should be set while other bits 277 * should be the same as before. 278 */ 279 #define MAC_EG_CNTL_MASK 0x06300000 280 281 #define MAC_EG_ADD_FIX 0x80000000 282 #define MAC_EG_FORCE_DERR00 0x40000000 283 #define MAC_EG_FORCE_DERR16 0x20000000 284 #define MAC_EG_FORCE_DERR64 0x10000000 285 #define MAC_EG_FORCE_DERR80 0x08000000 286 #define MAC_EG_DERR_ALWAYS 0x02000000 287 #define MAC_EG_DERR_ONCE 0x04000000 288 #define MAC_EG_DERR_NOP 0x06000000 289 #define MAC_EG_FORCE_READ00 0x00800000 290 #define MAC_EG_FORCE_READ16 0x00400000 291 #define MAC_EG_RDERR_ALWAYS 0x00100000 292 #define MAC_EG_RDERR_ONCE 0x00200000 293 #define MAC_EG_RDERR_NOP 0x00300000 294 295 #define MAC_EG_SETUP_MASK 0xf9cfffff 296 297 /* For MAC-PA translation */ 298 #define MC_ADDRESS_BITS 31 299 #define PA_BITS_FOR_MAC 39 300 #define INDEX_OF_BANK_SUPPLEMENT_BIT 39 301 #define MP_NONE 128 302 #define MP_BANK_0 129 303 #define MP_BANK_1 130 304 #define MP_BANK_2 131 305 306 #define CS_SHIFT 29 307 #define MC_TT_ENTRIES 64 308 #define MC_TT_CS 2 309 310 311 #define MAX_MC_LOOP_COUNT 100 312 313 /* export interface for error injection */ 314 extern int mc_inject_error(int error_type, uint64_t pa, uint32_t flags); 315 316 #define MC_INJECT_NOP 0x0 317 #define MC_INJECT_INTERMITTENT_CE 0x1 318 #define MC_INJECT_PERMANENT_CE 0x2 319 #define MC_INJECT_UE 0x3 320 #define MC_INJECT_INTERMITTENT_MCE 0x11 321 #define MC_INJECT_PERMANENT_MCE 0x12 322 #define MC_INJECT_SUE 0x13 323 #define MC_INJECT_MUE 0x14 324 #define MC_INJECT_CMPE 0x15 325 326 #define MC_INJECT_MIRROR_MODE 0x10 327 #define MC_INJECT_MIRROR(x) (x & MC_INJECT_MIRROR_MODE) 328 329 #define MC_INJECT_FLAG_NO_TRAP 0x1 330 #define MC_INJECT_FLAG_RESTART 0x2 331 #define MC_INJECT_FLAG_POLL 0x4 332 #define MC_INJECT_FLAG_RESET 0x8 333 #define MC_INJECT_FLAG_OTHER 0x10 334 #define MC_INJECT_FLAG_LD 0x20 335 #define MC_INJECT_FLAG_ST 0x40 336 #define MC_INJECT_FLAG_PATH 0x80 337 338 #ifdef __cplusplus 339 } 340 #endif 341 342 #endif /* _SYS_MC_OPL_H */ 343