1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express nexus DVMA and DMA core routines: 30 * dma_map/dma_bind_handle implementation 31 * bypass and peer-to-peer support 32 * fast track DVMA space allocation 33 * runtime DVMA debug 34 */ 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/async.h> 38 #include <sys/sysmacros.h> 39 #include <sys/sunddi.h> 40 #include <sys/ddi_impldefs.h> 41 #include "px_obj.h" 42 43 /*LINTLIBRARY*/ 44 45 /* 46 * px_dma_allocmp - Allocate a pci dma implementation structure 47 * 48 * An extra ddi_dma_attr structure is bundled with the usual ddi_dma_impl 49 * to hold unmodified device limits. The ddi_dma_attr inside the 50 * ddi_dma_impl structure is augumented with system limits to enhance 51 * DVMA performance at runtime. The unaugumented device limits saved 52 * right after (accessed through (ddi_dma_attr_t *)(mp + 1)) is used 53 * strictly for peer-to-peer transfers which do not obey system limits. 54 * 55 * return: DDI_SUCCESS DDI_DMA_NORESOURCES 56 */ 57 ddi_dma_impl_t * 58 px_dma_allocmp(dev_info_t *dip, dev_info_t *rdip, int (*waitfp)(caddr_t), 59 caddr_t arg) 60 { 61 register ddi_dma_impl_t *mp; 62 int sleep = (waitfp == DDI_DMA_SLEEP) ? KM_SLEEP : KM_NOSLEEP; 63 64 /* Caution: we don't use zalloc to enhance performance! */ 65 if ((mp = kmem_alloc(sizeof (px_dma_hdl_t), sleep)) == 0) { 66 DBG(DBG_DMA_MAP, dip, "can't alloc dma_handle\n"); 67 if (waitfp != DDI_DMA_DONTWAIT) { 68 DBG(DBG_DMA_MAP, dip, "alloc_mp kmem cb\n"); 69 ddi_set_callback(waitfp, arg, &px_kmem_clid); 70 } 71 return (mp); 72 } 73 74 mp->dmai_rdip = rdip; 75 mp->dmai_flags = 0; 76 mp->dmai_pfnlst = NULL; 77 mp->dmai_winlst = NULL; 78 79 /* 80 * kmem_alloc debug: the following fields are not zero-ed 81 * mp->dmai_mapping = 0; 82 * mp->dmai_size = 0; 83 * mp->dmai_offset = 0; 84 * mp->dmai_minxfer = 0; 85 * mp->dmai_burstsizes = 0; 86 * mp->dmai_ndvmapages = 0; 87 * mp->dmai_pool/roffset = 0; 88 * mp->dmai_rflags = 0; 89 * mp->dmai_inuse/flags 90 * mp->dmai_nwin = 0; 91 * mp->dmai_winsize = 0; 92 * mp->dmai_nexus_private/tte = 0; 93 * mp->dmai_iopte/pfnlst 94 * mp->dmai_sbi/pfn0 = 0; 95 * mp->dmai_minfo/winlst/fdvma 96 * mp->dmai_rdip 97 * bzero(&mp->dmai_object, sizeof (ddi_dma_obj_t)); 98 * bzero(&mp->dmai_attr, sizeof (ddi_dma_attr_t)); 99 * mp->dmai_cookie = 0; 100 */ 101 102 mp->dmai_attr.dma_attr_version = (uint_t)DMA_ATTR_VERSION; 103 mp->dmai_attr.dma_attr_flags = (uint_t)0; 104 mp->dmai_fault = 0; 105 mp->dmai_fault_check = NULL; 106 mp->dmai_fault_notify = NULL; 107 108 mp->dmai_error.err_ena = 0; 109 mp->dmai_error.err_status = DDI_FM_OK; 110 mp->dmai_error.err_expected = DDI_FM_ERR_UNEXPECTED; 111 mp->dmai_error.err_ontrap = NULL; 112 mp->dmai_error.err_fep = NULL; 113 114 if (px_child_prefetch(mp->dmai_rdip)) 115 mp->dmai_flags |= (PX_DMAI_FLAGS_MAP_BUFZONE | 116 PX_DMAI_FLAGS_REDZONE); 117 118 return (mp); 119 } 120 121 void 122 px_dma_freemp(ddi_dma_impl_t *mp) 123 { 124 if (mp->dmai_ndvmapages > 1) 125 px_dma_freepfn(mp); 126 if (mp->dmai_winlst) 127 px_dma_freewin(mp); 128 kmem_free(mp, sizeof (px_dma_hdl_t)); 129 } 130 131 void 132 px_dma_freepfn(ddi_dma_impl_t *mp) 133 { 134 void *addr = mp->dmai_pfnlst; 135 if (addr) { 136 size_t npages = mp->dmai_ndvmapages; 137 if (npages > 1) 138 kmem_free(addr, npages * sizeof (px_iopfn_t)); 139 mp->dmai_pfnlst = NULL; 140 } 141 mp->dmai_ndvmapages = 0; 142 } 143 144 /* 145 * px_dma_lmts2hdl - alloate a ddi_dma_impl_t, validate practical limits 146 * and convert dmareq->dmar_limits to mp->dmai_attr 147 * 148 * ddi_dma_impl_t member modified input 149 * ------------------------------------------------------------------------ 150 * mp->dmai_minxfer - dev 151 * mp->dmai_burstsizes - dev 152 * mp->dmai_flags - no limit? peer-to-peer only? 153 * 154 * ddi_dma_attr member modified input 155 * ------------------------------------------------------------------------ 156 * mp->dmai_attr.dma_attr_addr_lo - dev lo, sys lo 157 * mp->dmai_attr.dma_attr_addr_hi - dev hi, sys hi 158 * mp->dmai_attr.dma_attr_count_max - dev count max, dev/sys lo/hi delta 159 * mp->dmai_attr.dma_attr_seg - 0 (no nocross restriction) 160 * mp->dmai_attr.dma_attr_align - 1 (no alignment restriction) 161 * 162 * The dlim_dmaspeed member of dmareq->dmar_limits is ignored. 163 */ 164 ddi_dma_impl_t * 165 px_dma_lmts2hdl(dev_info_t *dip, dev_info_t *rdip, px_mmu_t *mmu_p, 166 ddi_dma_req_t *dmareq) 167 { 168 ddi_dma_impl_t *mp; 169 ddi_dma_attr_t *attr_p; 170 uint64_t syslo = mmu_p->mmu_dvma_base; 171 uint64_t syshi = mmu_p->mmu_dvma_end; 172 uint64_t fasthi = mmu_p->mmu_dvma_fast_end; 173 ddi_dma_lim_t *lim_p = dmareq->dmar_limits; 174 uint32_t count_max = lim_p->dlim_cntr_max; 175 uint64_t lo = lim_p->dlim_addr_lo; 176 uint64_t hi = lim_p->dlim_addr_hi; 177 if (hi <= lo) { 178 DBG(DBG_DMA_MAP, dip, "Bad limits\n"); 179 return ((ddi_dma_impl_t *)DDI_DMA_NOMAPPING); 180 } 181 if (!count_max) 182 count_max--; 183 184 if (!(mp = px_dma_allocmp(dip, rdip, dmareq->dmar_fp, 185 dmareq->dmar_arg))) 186 return (NULL); 187 188 /* store original dev input at the 2nd ddi_dma_attr */ 189 attr_p = PX_DEV_ATTR(mp); 190 SET_DMAATTR(attr_p, lo, hi, -1, count_max); 191 SET_DMAALIGN(attr_p, 1); 192 193 lo = MAX(lo, syslo); 194 hi = MIN(hi, syshi); 195 if (hi <= lo) 196 mp->dmai_flags |= PX_DMAI_FLAGS_PEER_ONLY; 197 count_max = MIN(count_max, hi - lo); 198 199 if (PX_DEV_NOSYSLIMIT(lo, hi, syslo, fasthi, 1)) 200 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT | 201 PX_DMAI_FLAGS_NOSYSLIMIT; 202 else { 203 if (PX_DEV_NOFASTLIMIT(lo, hi, syslo, syshi, 1)) 204 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT; 205 } 206 if (PX_DMA_NOCTX(rdip)) 207 mp->dmai_flags |= PX_DMAI_FLAGS_NOCTX; 208 209 /* store augumented dev input to mp->dmai_attr */ 210 mp->dmai_minxfer = lim_p->dlim_minxfer; 211 mp->dmai_burstsizes = lim_p->dlim_burstsizes; 212 attr_p = &mp->dmai_attr; 213 SET_DMAATTR(attr_p, lo, hi, -1, count_max); 214 SET_DMAALIGN(attr_p, 1); 215 return (mp); 216 } 217 218 /* 219 * Called from px_attach to check for bypass dma support and set 220 * flags accordingly. 221 */ 222 int 223 px_dma_attach(px_t *px_p) 224 { 225 uint64_t baddr; 226 227 if (px_lib_iommu_getbypass(px_p->px_dip, 0ull, 228 PCI_MAP_ATTR_WRITE|PCI_MAP_ATTR_READ, 229 &baddr) != DDI_ENOTSUP) 230 /* ignore all other errors */ 231 px_p->px_dev_caps |= PX_BYPASS_DMA_ALLOWED; 232 233 return (DDI_SUCCESS); 234 } 235 236 /* 237 * px_dma_attr2hdl 238 * 239 * This routine is called from the alloc handle entry point to sanity check the 240 * dma attribute structure. 241 * 242 * use by: px_dma_allochdl() 243 * 244 * return value: 245 * 246 * DDI_SUCCESS - on success 247 * DDI_DMA_BADATTR - attribute has invalid version number 248 * or address limits exclude dvma space 249 */ 250 int 251 px_dma_attr2hdl(px_t *px_p, ddi_dma_impl_t *mp) 252 { 253 px_mmu_t *mmu_p = px_p->px_mmu_p; 254 uint64_t syslo, syshi; 255 int ret; 256 ddi_dma_attr_t *attrp = PX_DEV_ATTR(mp); 257 uint64_t hi = attrp->dma_attr_addr_hi; 258 uint64_t lo = attrp->dma_attr_addr_lo; 259 uint64_t align = attrp->dma_attr_align; 260 uint64_t nocross = attrp->dma_attr_seg; 261 uint64_t count_max = attrp->dma_attr_count_max; 262 263 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "attrp=%p cntr_max=%x.%08x\n", 264 attrp, HI32(count_max), LO32(count_max)); 265 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "hi=%x.%08x lo=%x.%08x\n", 266 HI32(hi), LO32(hi), HI32(lo), LO32(lo)); 267 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "seg=%x.%08x align=%x.%08x\n", 268 HI32(nocross), LO32(nocross), HI32(align), LO32(align)); 269 270 if (!nocross) 271 nocross--; 272 if (attrp->dma_attr_flags & DDI_DMA_FORCE_PHYSICAL) { /* BYPASS */ 273 274 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "bypass mode\n"); 275 /* 276 * If Bypass DMA is not supported, return error so that 277 * target driver can fall back to dvma mode of operation 278 */ 279 if (!(px_p->px_dev_caps & PX_BYPASS_DMA_ALLOWED)) 280 return (DDI_DMA_BADATTR); 281 mp->dmai_flags |= PX_DMAI_FLAGS_BYPASSREQ; 282 if (nocross != UINT64_MAX) 283 return (DDI_DMA_BADATTR); 284 if (align && (align > MMU_PAGE_SIZE)) 285 return (DDI_DMA_BADATTR); 286 align = 1; /* align on 1 page boundary */ 287 288 /* do a range check and get the limits */ 289 ret = px_lib_dma_bypass_rngchk(px_p->px_dip, attrp, 290 &syslo, &syshi); 291 if (ret != DDI_SUCCESS) 292 return (ret); 293 } else { /* MMU_XLATE or PEER_TO_PEER */ 294 align = MAX(align, MMU_PAGE_SIZE) - 1; 295 if ((align & nocross) != align) { 296 dev_info_t *rdip = mp->dmai_rdip; 297 cmn_err(CE_WARN, "%s%d dma_attr_seg not aligned", 298 NAMEINST(rdip)); 299 return (DDI_DMA_BADATTR); 300 } 301 align = MMU_BTOP(align + 1); 302 syslo = mmu_p->mmu_dvma_base; 303 syshi = mmu_p->mmu_dvma_end; 304 } 305 if (hi <= lo) { 306 dev_info_t *rdip = mp->dmai_rdip; 307 cmn_err(CE_WARN, "%s%d limits out of range", NAMEINST(rdip)); 308 return (DDI_DMA_BADATTR); 309 } 310 lo = MAX(lo, syslo); 311 hi = MIN(hi, syshi); 312 if (!count_max) 313 count_max--; 314 315 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "hi=%x.%08x, lo=%x.%08x\n", 316 HI32(hi), LO32(hi), HI32(lo), LO32(lo)); 317 if (hi <= lo) { /* peer transfers cannot have alignment & nocross */ 318 dev_info_t *rdip = mp->dmai_rdip; 319 cmn_err(CE_WARN, "%s%d peer only dev %p", NAMEINST(rdip), mp); 320 if ((nocross < UINT32_MAX) || (align > 1)) { 321 cmn_err(CE_WARN, "%s%d peer only device bad attr", 322 NAMEINST(rdip)); 323 return (DDI_DMA_BADATTR); 324 } 325 mp->dmai_flags |= PX_DMAI_FLAGS_PEER_ONLY; 326 } else /* set practical counter_max value */ 327 count_max = MIN(count_max, hi - lo); 328 329 if (PX_DEV_NOSYSLIMIT(lo, hi, syslo, syshi, align)) 330 mp->dmai_flags |= PX_DMAI_FLAGS_NOSYSLIMIT | 331 PX_DMAI_FLAGS_NOFASTLIMIT; 332 else { 333 syshi = mmu_p->mmu_dvma_fast_end; 334 if (PX_DEV_NOFASTLIMIT(lo, hi, syslo, syshi, align)) 335 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT; 336 } 337 if (PX_DMA_NOCTX(mp->dmai_rdip)) 338 mp->dmai_flags |= PX_DMAI_FLAGS_NOCTX; 339 340 mp->dmai_minxfer = attrp->dma_attr_minxfer; 341 mp->dmai_burstsizes = attrp->dma_attr_burstsizes; 342 attrp = &mp->dmai_attr; 343 SET_DMAATTR(attrp, lo, hi, nocross, count_max); 344 return (DDI_SUCCESS); 345 } 346 347 #define TGT_PFN_INBETWEEN(pfn, bgn, end) ((pfn >= bgn) && (pfn <= end)) 348 349 /* 350 * px_dma_type - determine which of the three types DMA (peer-to-peer, 351 * mmu bypass, or mmu translate) we are asked to do. 352 * Also checks pfn0 and rejects any non-peer-to-peer 353 * requests for peer-only devices. 354 * 355 * return values: 356 * DDI_DMA_NOMAPPING - can't get valid pfn0, or bad dma type 357 * DDI_SUCCESS 358 * 359 * dma handle members affected (set on exit): 360 * mp->dmai_object - dmareq->dmar_object 361 * mp->dmai_rflags - consistent?, nosync?, dmareq->dmar_flags 362 * mp->dmai_flags - DMA type 363 * mp->dmai_pfn0 - 1st page pfn (if va/size pair and not shadow) 364 * mp->dmai_roffset - initialized to starting MMU page offset 365 * mp->dmai_ndvmapages - # of total MMU pages of entire object 366 */ 367 int 368 px_dma_type(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 369 { 370 dev_info_t *dip = px_p->px_dip; 371 ddi_dma_obj_t *dobj_p = &dmareq->dmar_object; 372 px_pec_t *pec_p = px_p->px_pec_p; 373 uint32_t offset; 374 pfn_t pfn0; 375 376 mp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS | DMP_NOSYNC; 377 378 switch (dobj_p->dmao_type) { 379 case DMA_OTYP_BUFVADDR: 380 case DMA_OTYP_VADDR: { 381 page_t **pplist = dobj_p->dmao_obj.virt_obj.v_priv; 382 caddr_t vaddr = dobj_p->dmao_obj.virt_obj.v_addr; 383 384 DBG(DBG_DMA_MAP, dip, "vaddr=%p pplist=%p\n", vaddr, pplist); 385 offset = (ulong_t)vaddr & MMU_PAGE_OFFSET; 386 if (pplist) { /* shadow list */ 387 mp->dmai_flags |= PX_DMAI_FLAGS_PGPFN; 388 pfn0 = page_pptonum(*pplist); 389 } else { 390 struct as *as_p = dobj_p->dmao_obj.virt_obj.v_as; 391 struct hat *hat_p = as_p ? as_p->a_hat : kas.a_hat; 392 pfn0 = hat_getpfnum(hat_p, vaddr); 393 } 394 } 395 break; 396 397 case DMA_OTYP_PAGES: 398 offset = dobj_p->dmao_obj.pp_obj.pp_offset; 399 mp->dmai_flags |= PX_DMAI_FLAGS_PGPFN; 400 pfn0 = page_pptonum(dobj_p->dmao_obj.pp_obj.pp_pp); 401 break; 402 403 case DMA_OTYP_PADDR: 404 default: 405 cmn_err(CE_WARN, "%s%d requested unsupported dma type %x", 406 NAMEINST(mp->dmai_rdip), dobj_p->dmao_type); 407 return (DDI_DMA_NOMAPPING); 408 } 409 if (pfn0 == PFN_INVALID) { 410 cmn_err(CE_WARN, "%s%d: invalid pfn0 for DMA object %p", 411 NAMEINST(dip), dobj_p); 412 return (DDI_DMA_NOMAPPING); 413 } 414 if (TGT_PFN_INBETWEEN(pfn0, pec_p->pec_base32_pfn, 415 pec_p->pec_last32_pfn)) { 416 mp->dmai_flags |= PX_DMAI_FLAGS_PTP|PX_DMAI_FLAGS_PTP32; 417 goto done; /* leave bypass and dvma flag as 0 */ 418 } else if (TGT_PFN_INBETWEEN(pfn0, pec_p->pec_base64_pfn, 419 pec_p->pec_last64_pfn)) { 420 mp->dmai_flags |= PX_DMAI_FLAGS_PTP|PX_DMAI_FLAGS_PTP64; 421 goto done; /* leave bypass and dvma flag as 0 */ 422 } 423 if (PX_DMA_ISPEERONLY(mp)) { 424 dev_info_t *rdip = mp->dmai_rdip; 425 cmn_err(CE_WARN, "Bad peer-to-peer req %s%d", NAMEINST(rdip)); 426 return (DDI_DMA_NOMAPPING); 427 } 428 mp->dmai_flags |= (mp->dmai_flags & PX_DMAI_FLAGS_BYPASSREQ) ? 429 PX_DMAI_FLAGS_BYPASS : PX_DMAI_FLAGS_DVMA | 430 (mp->dmai_rflags & DDI_DMA_REDZONE ? PX_DMAI_FLAGS_REDZONE : 0); 431 done: 432 mp->dmai_object = *dobj_p; /* whole object */ 433 mp->dmai_pfn0 = (void *)pfn0; /* cache pfn0 */ 434 mp->dmai_roffset = offset; /* win0 pg0 offset */ 435 mp->dmai_ndvmapages = MMU_BTOPR(offset + mp->dmai_object.dmao_size); 436 return (DDI_SUCCESS); 437 } 438 439 /* 440 * px_dma_pgpfn - set up pfnlst array according to pages 441 * VA/size pair: <shadow IO, bypass, peer-to-peer>, or OTYP_PAGES 442 */ 443 /*ARGSUSED*/ 444 static int 445 px_dma_pgpfn(px_t *px_p, ddi_dma_impl_t *mp, uint_t npages) 446 { 447 int i; 448 dev_info_t *dip = px_p->px_dip; 449 450 switch (mp->dmai_object.dmao_type) { 451 case DMA_OTYP_BUFVADDR: 452 case DMA_OTYP_VADDR: { 453 page_t **pplist = mp->dmai_object.dmao_obj.virt_obj.v_priv; 454 DBG(DBG_DMA_MAP, dip, "shadow pplist=%p, %x pages, pfns=", 455 pplist, npages); 456 for (i = 1; i < npages; i++) { 457 px_iopfn_t pfn = page_pptonum(pplist[i]); 458 PX_SET_MP_PFN1(mp, i, pfn); 459 DBG(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn); 460 } 461 DBG(DBG_DMA_MAP|DBG_CONT, dip, "\n"); 462 } 463 break; 464 465 case DMA_OTYP_PAGES: { 466 page_t *pp = mp->dmai_object.dmao_obj.pp_obj.pp_pp->p_next; 467 DBG(DBG_DMA_MAP, dip, "pp=%p pfns=", pp); 468 for (i = 1; i < npages; i++, pp = pp->p_next) { 469 px_iopfn_t pfn = page_pptonum(pp); 470 PX_SET_MP_PFN1(mp, i, pfn); 471 DBG(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn); 472 } 473 DBG(DBG_DMA_MAP|DBG_CONT, dip, "\n"); 474 } 475 break; 476 477 default: /* check is already done by px_dma_type */ 478 ASSERT(0); 479 break; 480 } 481 return (DDI_SUCCESS); 482 } 483 484 /* 485 * px_dma_vapfn - set up pfnlst array according to VA 486 * VA/size pair: <normal, bypass, peer-to-peer> 487 * pfn0 is skipped as it is already done. 488 * In this case, the cached pfn0 is used to fill pfnlst[0] 489 */ 490 static int 491 px_dma_vapfn(px_t *px_p, ddi_dma_impl_t *mp, uint_t npages) 492 { 493 dev_info_t *dip = px_p->px_dip; 494 int i; 495 caddr_t vaddr = (caddr_t)mp->dmai_object.dmao_obj.virt_obj.v_as; 496 struct hat *hat_p = vaddr ? ((struct as *)vaddr)->a_hat : kas.a_hat; 497 498 vaddr = mp->dmai_object.dmao_obj.virt_obj.v_addr + MMU_PAGE_SIZE; 499 for (i = 1; i < npages; i++, vaddr += MMU_PAGE_SIZE) { 500 px_iopfn_t pfn = hat_getpfnum(hat_p, vaddr); 501 if (pfn == PFN_INVALID) 502 goto err_badpfn; 503 PX_SET_MP_PFN1(mp, i, pfn); 504 DBG(DBG_DMA_BINDH, dip, "px_dma_vapfn: mp=%p pfnlst[%x]=%x\n", 505 mp, i, pfn); 506 } 507 return (DDI_SUCCESS); 508 err_badpfn: 509 cmn_err(CE_WARN, "%s%d: bad page frame vaddr=%p", NAMEINST(dip), vaddr); 510 return (DDI_DMA_NOMAPPING); 511 } 512 513 /* 514 * px_dma_pfn - Fills pfn list for all pages being DMA-ed. 515 * 516 * dependencies: 517 * mp->dmai_ndvmapages - set to total # of dma pages 518 * 519 * return value: 520 * DDI_SUCCESS 521 * DDI_DMA_NOMAPPING 522 */ 523 int 524 px_dma_pfn(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 525 { 526 uint32_t npages = mp->dmai_ndvmapages; 527 int (*waitfp)(caddr_t) = dmareq->dmar_fp; 528 int i, ret, peer = PX_DMA_ISPTP(mp); 529 int peer32 = PX_DMA_ISPTP32(mp); 530 dev_info_t *dip = px_p->px_dip; 531 532 px_pec_t *pec_p = px_p->px_pec_p; 533 px_iopfn_t pfn_base = peer32 ? pec_p->pec_base32_pfn : 534 pec_p->pec_base64_pfn; 535 px_iopfn_t pfn_last = peer32 ? pec_p->pec_last32_pfn : 536 pec_p->pec_last64_pfn; 537 px_iopfn_t pfn_adj = peer ? pfn_base : 0; 538 539 DBG(DBG_DMA_BINDH, dip, "px_dma_pfn: mp=%p pfn0=%x\n", 540 mp, PX_MP_PFN0(mp) - pfn_adj); 541 /* 1 page: no array alloc/fill, no mixed mode check */ 542 if (npages == 1) { 543 PX_SET_MP_PFN(mp, 0, PX_MP_PFN0(mp) - pfn_adj); 544 return (DDI_SUCCESS); 545 } 546 /* allocate pfn array */ 547 if (!(mp->dmai_pfnlst = kmem_alloc(npages * sizeof (px_iopfn_t), 548 waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP))) { 549 if (waitfp != DDI_DMA_DONTWAIT) 550 ddi_set_callback(waitfp, dmareq->dmar_arg, 551 &px_kmem_clid); 552 return (DDI_DMA_NORESOURCES); 553 } 554 /* fill pfn array */ 555 PX_SET_MP_PFN(mp, 0, PX_MP_PFN0(mp) - pfn_adj); /* pfnlst[0] */ 556 if ((ret = PX_DMA_ISPGPFN(mp) ? px_dma_pgpfn(px_p, mp, npages) : 557 px_dma_vapfn(px_p, mp, npages)) != DDI_SUCCESS) 558 goto err; 559 560 /* skip pfn0, check mixed mode and adjust peer to peer pfn */ 561 for (i = 1; i < npages; i++) { 562 px_iopfn_t pfn = PX_GET_MP_PFN1(mp, i); 563 if (peer ^ TGT_PFN_INBETWEEN(pfn, pfn_base, pfn_last)) { 564 cmn_err(CE_WARN, "%s%d mixed mode DMA %lx %lx", 565 NAMEINST(mp->dmai_rdip), PX_MP_PFN0(mp), pfn); 566 ret = DDI_DMA_NOMAPPING; /* mixed mode */ 567 goto err; 568 } 569 DBG(DBG_DMA_MAP, dip, 570 "px_dma_pfn: pfnlst[%x]=%x-%x\n", i, pfn, pfn_adj); 571 if (pfn_adj) 572 PX_SET_MP_PFN1(mp, i, pfn - pfn_adj); 573 } 574 return (DDI_SUCCESS); 575 err: 576 px_dma_freepfn(mp); 577 return (ret); 578 } 579 580 /* 581 * px_dvma_win() - trim requested DVMA size down to window size 582 * The 1st window starts from offset and ends at page-aligned boundary. 583 * From the 2nd window on, each window starts and ends at page-aligned 584 * boundary except the last window ends at wherever requested. 585 * 586 * accesses the following mp-> members: 587 * mp->dmai_attr.dma_attr_count_max 588 * mp->dmai_attr.dma_attr_seg 589 * mp->dmai_roffset - start offset of 1st window 590 * mp->dmai_rflags (redzone) 591 * mp->dmai_ndvmapages (for 1 page fast path) 592 * 593 * sets the following mp-> members: 594 * mp->dmai_size - xfer size, != winsize if 1st/last win (not fixed) 595 * mp->dmai_winsize - window size (no redzone), n * page size (fixed) 596 * mp->dmai_nwin - # of DMA windows of entire object (fixed) 597 * mp->dmai_rflags - remove partial flag if nwin == 1 (fixed) 598 * mp->dmai_winlst - NULL, window objects not used for DVMA (fixed) 599 * 600 * fixed - not changed across different DMA windows 601 */ 602 /*ARGSUSED*/ 603 int 604 px_dvma_win(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 605 { 606 uint32_t redzone_sz = PX_HAS_REDZONE(mp) ? MMU_PAGE_SIZE : 0; 607 size_t obj_sz = mp->dmai_object.dmao_size; 608 size_t xfer_sz; 609 ulong_t pg_off; 610 611 if ((mp->dmai_ndvmapages == 1) && !redzone_sz) { 612 mp->dmai_rflags &= ~DDI_DMA_PARTIAL; 613 mp->dmai_size = obj_sz; 614 mp->dmai_winsize = MMU_PAGE_SIZE; 615 mp->dmai_nwin = 1; 616 goto done; 617 } 618 619 pg_off = mp->dmai_roffset; 620 xfer_sz = obj_sz + redzone_sz; 621 622 /* include redzone in nocross check */ { 623 uint64_t nocross = mp->dmai_attr.dma_attr_seg; 624 if (xfer_sz + pg_off - 1 > nocross) 625 xfer_sz = nocross - pg_off + 1; 626 if (redzone_sz && (xfer_sz <= redzone_sz)) { 627 DBG(DBG_DMA_MAP, px_p->px_dip, 628 "nocross too small: " 629 "%lx(%lx)+%lx+%lx < %llx\n", 630 xfer_sz, obj_sz, pg_off, redzone_sz, nocross); 631 return (DDI_DMA_TOOBIG); 632 } 633 } 634 xfer_sz -= redzone_sz; /* restore transfer size */ 635 /* check counter max */ { 636 uint32_t count_max = mp->dmai_attr.dma_attr_count_max; 637 if (xfer_sz - 1 > count_max) 638 xfer_sz = count_max + 1; 639 } 640 if (xfer_sz >= obj_sz) { 641 mp->dmai_rflags &= ~DDI_DMA_PARTIAL; 642 mp->dmai_size = xfer_sz; 643 mp->dmai_winsize = P2ROUNDUP(xfer_sz + pg_off, MMU_PAGE_SIZE); 644 mp->dmai_nwin = 1; 645 goto done; 646 } 647 if (!(dmareq->dmar_flags & DDI_DMA_PARTIAL)) { 648 DBG(DBG_DMA_MAP, px_p->px_dip, "too big: %lx+%lx+%lx > %lx\n", 649 obj_sz, pg_off, redzone_sz, xfer_sz); 650 return (DDI_DMA_TOOBIG); 651 } 652 653 xfer_sz = MMU_PTOB(MMU_BTOP(xfer_sz + pg_off)); /* page align */ 654 mp->dmai_size = xfer_sz - pg_off; /* 1st window xferrable size */ 655 mp->dmai_winsize = xfer_sz; /* redzone not in winsize */ 656 mp->dmai_nwin = (obj_sz + pg_off + xfer_sz - 1) / xfer_sz; 657 done: 658 mp->dmai_winlst = NULL; 659 px_dump_dma_handle(DBG_DMA_MAP, px_p->px_dip, mp); 660 return (DDI_SUCCESS); 661 } 662 663 /* 664 * fast track cache entry to mmu context, inserts 3 0 bits between 665 * upper 6-bits and lower 3-bits of the 9-bit cache entry 666 */ 667 #define MMU_FCE_TO_CTX(i) (((i) << 3) | ((i) & 0x7) | 0x38) 668 669 /* 670 * px_dvma_map_fast - attempts to map fast trackable DVMA 671 */ 672 /*ARGSUSED*/ 673 int 674 px_dvma_map_fast(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) 675 { 676 uint_t clustsz = px_dvma_page_cache_clustsz; 677 uint_t entries = px_dvma_page_cache_entries; 678 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 679 mp->dmai_attr.dma_attr_flags); 680 int i = mmu_p->mmu_dvma_addr_scan_start; 681 uint8_t *lock_addr = mmu_p->mmu_dvma_cache_locks + i; 682 px_dvma_addr_t dvma_pg; 683 size_t npages = MMU_BTOP(mp->dmai_winsize); 684 dev_info_t *dip = mmu_p->mmu_px_p->px_dip; 685 686 extern uint8_t ldstub(uint8_t *); 687 ASSERT(MMU_PTOB(npages) == mp->dmai_winsize); 688 ASSERT(npages + PX_HAS_REDZONE(mp) <= clustsz); 689 690 for (; i < entries && ldstub(lock_addr); i++, lock_addr++); 691 if (i >= entries) { 692 lock_addr = mmu_p->mmu_dvma_cache_locks; 693 i = 0; 694 for (; i < entries && ldstub(lock_addr); i++, lock_addr++); 695 if (i >= entries) { 696 #ifdef PX_DMA_PROF 697 px_dvmaft_exhaust++; 698 #endif /* PX_DMA_PROF */ 699 return (DDI_DMA_NORESOURCES); 700 } 701 } 702 mmu_p->mmu_dvma_addr_scan_start = (i + 1) & (entries - 1); 703 704 i *= clustsz; 705 dvma_pg = mmu_p->dvma_base_pg + i; 706 707 if (px_lib_iommu_map(dip, PCI_TSBID(0, i), npages, attr, 708 (void *)mp, 0, MMU_MAP_PFN) != DDI_SUCCESS) { 709 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " 710 "px_lib_iommu_map failed\n"); 711 712 return (DDI_FAILURE); 713 } 714 715 if (!PX_MAP_BUFZONE(mp)) 716 goto done; 717 718 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: redzone pg=%x\n", i + npages); 719 720 ASSERT(PX_HAS_REDZONE(mp)); 721 722 if (px_lib_iommu_map(dip, PCI_TSBID(0, i + npages), 1, attr, 723 (void *)mp, npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) { 724 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " 725 "mapping REDZONE page failed\n"); 726 727 (void) px_lib_iommu_demap(dip, PCI_TSBID(0, i), npages); 728 return (DDI_FAILURE); 729 } 730 731 done: 732 #ifdef PX_DMA_PROF 733 px_dvmaft_success++; 734 #endif 735 mp->dmai_mapping = mp->dmai_roffset | MMU_PTOB(dvma_pg); 736 mp->dmai_offset = 0; 737 mp->dmai_flags |= PX_DMAI_FLAGS_FASTTRACK; 738 PX_SAVE_MP_TTE(mp, attr); /* save TTE template for unmapping */ 739 if (PX_DVMA_DBG_ON(mmu_p)) 740 px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping, 741 mp->dmai_size, mp); 742 return (DDI_SUCCESS); 743 } 744 745 /* 746 * px_dvma_map: map non-fasttrack DMA 747 * Use quantum cache if single page DMA. 748 */ 749 int 750 px_dvma_map(ddi_dma_impl_t *mp, ddi_dma_req_t *dmareq, px_mmu_t *mmu_p) 751 { 752 uint_t npages = PX_DMA_WINNPGS(mp); 753 px_dvma_addr_t dvma_pg, dvma_pg_index; 754 void *dvma_addr; 755 uint64_t tte = PX_GET_TTE_ATTR(mp->dmai_rflags, 756 mp->dmai_attr.dma_attr_flags); 757 int sleep = dmareq->dmar_fp == DDI_DMA_SLEEP ? VM_SLEEP : VM_NOSLEEP; 758 dev_info_t *dip = mp->dmai_rdip; 759 int ret = DDI_SUCCESS; 760 761 /* 762 * allocate dvma space resource and map in the first window. 763 * (vmem_t *vmp, size_t size, 764 * size_t align, size_t phase, size_t nocross, 765 * void *minaddr, void *maxaddr, int vmflag) 766 */ 767 if ((npages == 1) && !PX_HAS_REDZONE(mp) && PX_HAS_NOSYSLIMIT(mp)) { 768 dvma_addr = vmem_alloc(mmu_p->mmu_dvma_map, 769 MMU_PAGE_SIZE, sleep); 770 mp->dmai_flags |= PX_DMAI_FLAGS_VMEMCACHE; 771 #ifdef PX_DMA_PROF 772 px_dvma_vmem_alloc++; 773 #endif /* PX_DMA_PROF */ 774 } else { 775 dvma_addr = vmem_xalloc(mmu_p->mmu_dvma_map, 776 MMU_PTOB(npages + PX_HAS_REDZONE(mp)), 777 MAX(mp->dmai_attr.dma_attr_align, MMU_PAGE_SIZE), 778 0, 779 mp->dmai_attr.dma_attr_seg + 1, 780 (void *)mp->dmai_attr.dma_attr_addr_lo, 781 (void *)(mp->dmai_attr.dma_attr_addr_hi + 1), 782 sleep); 783 #ifdef PX_DMA_PROF 784 px_dvma_vmem_xalloc++; 785 #endif /* PX_DMA_PROF */ 786 } 787 dvma_pg = MMU_BTOP((ulong_t)dvma_addr); 788 dvma_pg_index = dvma_pg - mmu_p->dvma_base_pg; 789 DBG(DBG_DMA_MAP, dip, "fallback dvma_pages: dvma_pg=%x index=%x\n", 790 dvma_pg, dvma_pg_index); 791 if (dvma_pg == 0) 792 goto noresource; 793 794 mp->dmai_mapping = mp->dmai_roffset | MMU_PTOB(dvma_pg); 795 mp->dmai_offset = 0; 796 PX_SAVE_MP_TTE(mp, tte); /* mp->dmai_tte = tte */ 797 798 if ((ret = px_mmu_map_pages(mmu_p, 799 mp, dvma_pg, npages, 0)) != DDI_SUCCESS) { 800 if (mp->dmai_flags & PX_DMAI_FLAGS_VMEMCACHE) { 801 vmem_free(mmu_p->mmu_dvma_map, (void *)dvma_addr, 802 MMU_PAGE_SIZE); 803 #ifdef PX_DMA_PROF 804 px_dvma_vmem_free++; 805 #endif /* PX_DMA_PROF */ 806 } else { 807 vmem_xfree(mmu_p->mmu_dvma_map, (void *)dvma_addr, 808 MMU_PTOB(npages + PX_HAS_REDZONE(mp))); 809 #ifdef PX_DMA_PROF 810 px_dvma_vmem_xfree++; 811 #endif /* PX_DMA_PROF */ 812 } 813 } 814 815 return (ret); 816 noresource: 817 if (dmareq->dmar_fp != DDI_DMA_DONTWAIT) { 818 DBG(DBG_DMA_MAP, dip, "dvma_pg 0 - set callback\n"); 819 ddi_set_callback(dmareq->dmar_fp, dmareq->dmar_arg, 820 &mmu_p->mmu_dvma_clid); 821 } 822 DBG(DBG_DMA_MAP, dip, "vmem_xalloc - DDI_DMA_NORESOURCES\n"); 823 return (DDI_DMA_NORESOURCES); 824 } 825 826 void 827 px_dvma_unmap(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) 828 { 829 px_dvma_addr_t dvma_addr = (px_dvma_addr_t)mp->dmai_mapping; 830 px_dvma_addr_t dvma_pg = MMU_BTOP(dvma_addr); 831 dvma_addr = MMU_PTOB(dvma_pg); 832 833 if (mp->dmai_flags & PX_DMAI_FLAGS_FASTTRACK) { 834 px_iopfn_t index = dvma_pg - mmu_p->dvma_base_pg; 835 ASSERT(index % px_dvma_page_cache_clustsz == 0); 836 index /= px_dvma_page_cache_clustsz; 837 ASSERT(index < px_dvma_page_cache_entries); 838 mmu_p->mmu_dvma_cache_locks[index] = 0; 839 #ifdef PX_DMA_PROF 840 px_dvmaft_free++; 841 #endif /* PX_DMA_PROF */ 842 return; 843 } 844 845 if (mp->dmai_flags & PX_DMAI_FLAGS_VMEMCACHE) { 846 vmem_free(mmu_p->mmu_dvma_map, (void *)dvma_addr, 847 MMU_PAGE_SIZE); 848 #ifdef PX_DMA_PROF 849 px_dvma_vmem_free++; 850 #endif /* PX_DMA_PROF */ 851 } else { 852 size_t npages = MMU_BTOP(mp->dmai_winsize) + PX_HAS_REDZONE(mp); 853 vmem_xfree(mmu_p->mmu_dvma_map, (void *)dvma_addr, 854 MMU_PTOB(npages)); 855 #ifdef PX_DMA_PROF 856 px_dvma_vmem_xfree++; 857 #endif /* PX_DMA_PROF */ 858 } 859 } 860 861 /* 862 * DVMA mappings may have multiple windows, but each window always have 863 * one segment. 864 */ 865 int 866 px_dvma_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_impl_t *mp, 867 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 868 uint_t cache_flags) 869 { 870 switch (cmd) { 871 case DDI_DMA_SYNC: 872 return (px_lib_dma_sync(dip, rdip, (ddi_dma_handle_t)mp, 873 *offp, *lenp, cache_flags)); 874 875 case DDI_DMA_HTOC: { 876 int ret; 877 off_t wo_off, off = *offp; /* wo_off: wnd's obj offset */ 878 uint_t win_size = mp->dmai_winsize; 879 ddi_dma_cookie_t *cp = (ddi_dma_cookie_t *)objp; 880 881 if (off >= mp->dmai_object.dmao_size) { 882 cmn_err(CE_WARN, "%s%d invalid dma_htoc offset %lx", 883 NAMEINST(mp->dmai_rdip), off); 884 return (DDI_FAILURE); 885 } 886 off += mp->dmai_roffset; 887 ret = px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 888 off / win_size, &wo_off, NULL, cp, NULL); /* lenp == NULL */ 889 if (ret) 890 return (ret); 891 DBG(DBG_DMA_CTL, dip, "HTOC:cookie=%x+%lx off=%lx,%lx\n", 892 cp->dmac_address, cp->dmac_size, off, *offp); 893 894 /* adjust cookie addr/len if we are not on window boundary */ 895 ASSERT((off % win_size) == (off - 896 (PX_DMA_CURWIN(mp) ? mp->dmai_roffset : 0) - wo_off)); 897 off = PX_DMA_CURWIN(mp) ? off % win_size : *offp; 898 ASSERT(cp->dmac_size > off); 899 cp->dmac_laddress += off; 900 cp->dmac_size -= off; 901 DBG(DBG_DMA_CTL, dip, "HTOC:mp=%p cookie=%x+%lx off=%lx,%lx\n", 902 mp, cp->dmac_address, cp->dmac_size, off, wo_off); 903 } 904 return (DDI_SUCCESS); 905 906 case DDI_DMA_REPWIN: 907 *offp = mp->dmai_offset; 908 *lenp = mp->dmai_size; 909 return (DDI_SUCCESS); 910 911 case DDI_DMA_MOVWIN: { 912 off_t off = *offp; 913 if (off >= mp->dmai_object.dmao_size) 914 return (DDI_FAILURE); 915 off += mp->dmai_roffset; 916 return (px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 917 off / mp->dmai_winsize, offp, lenp, 918 (ddi_dma_cookie_t *)objp, NULL)); 919 } 920 921 case DDI_DMA_NEXTWIN: { 922 px_window_t win = PX_DMA_CURWIN(mp); 923 if (offp) { 924 if (*(px_window_t *)offp != win) { 925 /* window not active */ 926 *(px_window_t *)objp = win; /* return cur win */ 927 return (DDI_DMA_STALE); 928 } 929 win++; 930 } else /* map win 0 */ 931 win = 0; 932 if (win >= mp->dmai_nwin) { 933 *(px_window_t *)objp = win - 1; 934 return (DDI_DMA_DONE); 935 } 936 if (px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 937 win, 0, 0, 0, 0)) { 938 *(px_window_t *)objp = win - 1; 939 return (DDI_FAILURE); 940 } 941 *(px_window_t *)objp = win; 942 } 943 return (DDI_SUCCESS); 944 945 case DDI_DMA_NEXTSEG: 946 if (*(px_window_t *)offp != PX_DMA_CURWIN(mp)) 947 return (DDI_DMA_STALE); 948 if (lenp) /* only 1 seg allowed */ 949 return (DDI_DMA_DONE); 950 951 /* return mp as seg 0 */ 952 *(ddi_dma_seg_t *)objp = (ddi_dma_seg_t)mp; 953 return (DDI_SUCCESS); 954 955 case DDI_DMA_SEGTOC: 956 MAKE_DMA_COOKIE((ddi_dma_cookie_t *)objp, mp->dmai_mapping, 957 mp->dmai_size); 958 *offp = mp->dmai_offset; 959 *lenp = mp->dmai_size; 960 return (DDI_SUCCESS); 961 962 case DDI_DMA_COFF: { 963 ddi_dma_cookie_t *cp = (ddi_dma_cookie_t *)offp; 964 if (cp->dmac_address < mp->dmai_mapping || 965 (cp->dmac_address + cp->dmac_size) > 966 (mp->dmai_mapping + mp->dmai_size)) 967 return (DDI_FAILURE); 968 *objp = (caddr_t)(cp->dmac_address - mp->dmai_mapping + 969 mp->dmai_offset); 970 } 971 return (DDI_SUCCESS); 972 default: 973 DBG(DBG_DMA_CTL, dip, "unknown command (%x): rdip=%s%d\n", 974 cmd, ddi_driver_name(rdip), ddi_get_instance(rdip)); 975 break; 976 } 977 return (DDI_FAILURE); 978 } 979 980 void 981 px_dma_freewin(ddi_dma_impl_t *mp) 982 { 983 px_dma_win_t *win_p = mp->dmai_winlst, *win2_p; 984 for (win2_p = win_p; win_p; win2_p = win_p) { 985 win_p = win2_p->win_next; 986 kmem_free(win2_p, sizeof (px_dma_win_t) + 987 sizeof (ddi_dma_cookie_t) * win2_p->win_ncookies); 988 } 989 mp->dmai_nwin = 0; 990 mp->dmai_winlst = NULL; 991 } 992 993 /* 994 * px_dma_newwin - create a dma window object and cookies 995 * 996 * After the initial scan in px_dma_physwin(), which identifies 997 * a portion of the pfn array that belongs to a dma window, 998 * we are called to allocate and initialize representing memory 999 * resources. We know from the 1st scan the number of cookies 1000 * or dma segment in this window so we can allocate a contiguous 1001 * memory array for the dma cookies (The implementation of 1002 * ddi_dma_nextcookie(9f) dictates dma cookies be contiguous). 1003 * 1004 * A second round scan is done on the pfn array to identify 1005 * each dma segment and initialize its corresponding dma cookie. 1006 * We don't need to do all the safety checking and we know they 1007 * all belong to the same dma window. 1008 * 1009 * Input: cookie_no - # of cookies identified by the 1st scan 1010 * start_idx - subscript of the pfn array for the starting pfn 1011 * end_idx - subscript of the last pfn in dma window 1012 * win_pp - pointer to win_next member of previous window 1013 * Return: DDI_SUCCESS - with **win_pp as newly created window object 1014 * DDI_DMA_NORESROUCE - caller frees all previous window objs 1015 * Note: Each cookie and window size are all initialized on page 1016 * boundary. This is not true for the 1st cookie of the 1st 1017 * window and the last cookie of the last window. 1018 * We fix that later in upper layer which has access to size 1019 * and offset info. 1020 * 1021 */ 1022 /*ARGSUSED*/ 1023 static int 1024 px_dma_newwin(dev_info_t *dip, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp, 1025 uint32_t cookie_no, uint32_t start_idx, uint32_t end_idx, 1026 px_dma_win_t **win_pp, uint64_t count_max, uint64_t bypass) 1027 { 1028 int (*waitfp)(caddr_t) = dmareq->dmar_fp; 1029 ddi_dma_cookie_t *cookie_p; 1030 uint32_t pfn_no = 1; 1031 px_iopfn_t pfn = PX_GET_MP_PFN(mp, start_idx); 1032 px_iopfn_t prev_pfn = pfn; 1033 uint64_t baddr, seg_pfn0 = pfn; 1034 size_t sz = cookie_no * sizeof (ddi_dma_cookie_t); 1035 px_dma_win_t *win_p = kmem_zalloc(sizeof (px_dma_win_t) + sz, 1036 waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP); 1037 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 1038 mp->dmai_attr.dma_attr_flags); 1039 1040 if (!win_p) 1041 goto noresource; 1042 1043 win_p->win_next = NULL; 1044 win_p->win_ncookies = cookie_no; 1045 win_p->win_curseg = 0; /* start from segment 0 */ 1046 win_p->win_size = MMU_PTOB(end_idx - start_idx + 1); 1047 /* win_p->win_offset is left uninitialized */ 1048 1049 cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1050 start_idx++; 1051 for (; start_idx <= end_idx; start_idx++, prev_pfn = pfn, pfn_no++) { 1052 pfn = PX_GET_MP_PFN1(mp, start_idx); 1053 if ((pfn == prev_pfn + 1) && 1054 (MMU_PTOB(pfn_no + 1) - 1 <= count_max)) 1055 continue; 1056 1057 /* close up the cookie up to (including) prev_pfn */ 1058 baddr = MMU_PTOB(seg_pfn0); 1059 if (bypass && (px_lib_iommu_getbypass(dip, 1060 baddr, attr, &baddr) != DDI_SUCCESS)) 1061 return (DDI_FAILURE); 1062 1063 MAKE_DMA_COOKIE(cookie_p, baddr, MMU_PTOB(pfn_no)); 1064 DBG(DBG_BYPASS, mp->dmai_rdip, "cookie %p (%x pages)\n", 1065 MMU_PTOB(seg_pfn0), pfn_no); 1066 1067 cookie_p++; /* advance to next available cookie cell */ 1068 pfn_no = 0; 1069 seg_pfn0 = pfn; /* start a new segment from current pfn */ 1070 } 1071 1072 baddr = MMU_PTOB(seg_pfn0); 1073 if (bypass && (px_lib_iommu_getbypass(dip, 1074 baddr, attr, &baddr) != DDI_SUCCESS)) 1075 return (DDI_FAILURE); 1076 1077 MAKE_DMA_COOKIE(cookie_p, baddr, MMU_PTOB(pfn_no)); 1078 DBG(DBG_BYPASS, mp->dmai_rdip, "cookie %p (%x pages) of total %x\n", 1079 MMU_PTOB(seg_pfn0), pfn_no, cookie_no); 1080 #ifdef DEBUG 1081 cookie_p++; 1082 ASSERT((cookie_p - (ddi_dma_cookie_t *)(win_p + 1)) == cookie_no); 1083 #endif /* DEBUG */ 1084 *win_pp = win_p; 1085 return (DDI_SUCCESS); 1086 noresource: 1087 if (waitfp != DDI_DMA_DONTWAIT) 1088 ddi_set_callback(waitfp, dmareq->dmar_arg, &px_kmem_clid); 1089 return (DDI_DMA_NORESOURCES); 1090 } 1091 1092 /* 1093 * px_dma_adjust - adjust 1st and last cookie and window sizes 1094 * remove initial dma page offset from 1st cookie and window size 1095 * remove last dma page remainder from last cookie and window size 1096 * fill win_offset of each dma window according to just fixed up 1097 * each window sizes 1098 * px_dma_win_t members modified: 1099 * win_p->win_offset - this window's offset within entire DMA object 1100 * win_p->win_size - xferrable size (in bytes) for this window 1101 * 1102 * ddi_dma_impl_t members modified: 1103 * mp->dmai_size - 1st window xferrable size 1104 * mp->dmai_offset - 0, which is the dma offset of the 1st window 1105 * 1106 * ddi_dma_cookie_t members modified: 1107 * cookie_p->dmac_size - 1st and last cookie remove offset or remainder 1108 * cookie_p->dmac_laddress - 1st cookie add page offset 1109 */ 1110 static void 1111 px_dma_adjust(ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp, px_dma_win_t *win_p) 1112 { 1113 ddi_dma_cookie_t *cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1114 size_t pg_offset = mp->dmai_roffset; 1115 size_t win_offset = 0; 1116 1117 cookie_p->dmac_size -= pg_offset; 1118 cookie_p->dmac_laddress |= pg_offset; 1119 win_p->win_size -= pg_offset; 1120 DBG(DBG_BYPASS, mp->dmai_rdip, "pg0 adjust %lx\n", pg_offset); 1121 1122 mp->dmai_size = win_p->win_size; 1123 mp->dmai_offset = 0; 1124 1125 pg_offset += mp->dmai_object.dmao_size; 1126 pg_offset &= MMU_PAGE_OFFSET; 1127 if (pg_offset) 1128 pg_offset = MMU_PAGE_SIZE - pg_offset; 1129 DBG(DBG_BYPASS, mp->dmai_rdip, "last pg adjust %lx\n", pg_offset); 1130 1131 for (; win_p->win_next; win_p = win_p->win_next) { 1132 DBG(DBG_BYPASS, mp->dmai_rdip, "win off %p\n", win_offset); 1133 win_p->win_offset = win_offset; 1134 win_offset += win_p->win_size; 1135 } 1136 /* last window */ 1137 win_p->win_offset = win_offset; 1138 cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1139 cookie_p[win_p->win_ncookies - 1].dmac_size -= pg_offset; 1140 win_p->win_size -= pg_offset; 1141 ASSERT((win_offset + win_p->win_size) == mp->dmai_object.dmao_size); 1142 } 1143 1144 /* 1145 * px_dma_physwin() - carve up dma windows using physical addresses. 1146 * Called to handle mmu bypass and pci peer-to-peer transfers. 1147 * Calls px_dma_newwin() to allocate window objects. 1148 * 1149 * Dependency: mp->dmai_pfnlst points to an array of pfns 1150 * 1151 * 1. Each dma window is represented by a px_dma_win_t object. 1152 * The object will be casted to ddi_dma_win_t and returned 1153 * to leaf driver through the DDI interface. 1154 * 2. Each dma window can have several dma segments with each 1155 * segment representing a physically contiguous either memory 1156 * space (if we are doing an mmu bypass transfer) or pci address 1157 * space (if we are doing a peer-to-peer transfer). 1158 * 3. Each segment has a DMA cookie to program the DMA engine. 1159 * The cookies within each DMA window must be located in a 1160 * contiguous array per ddi_dma_nextcookie(9f). 1161 * 4. The number of DMA segments within each DMA window cannot exceed 1162 * mp->dmai_attr.dma_attr_sgllen. If the transfer size is 1163 * too large to fit in the sgllen, the rest needs to be 1164 * relocated to the next dma window. 1165 * 5. Peer-to-peer DMA segment follows device hi, lo, count_max, 1166 * and nocross restrictions while bypass DMA follows the set of 1167 * restrictions with system limits factored in. 1168 * 1169 * Return: 1170 * mp->dmai_winlst - points to a link list of px_dma_win_t objects. 1171 * Each px_dma_win_t object on the link list contains 1172 * infomation such as its window size (# of pages), 1173 * starting offset (also see Restriction), an array of 1174 * DMA cookies, and # of cookies in the array. 1175 * mp->dmai_pfnlst - NULL, the pfn list is freed to conserve memory. 1176 * mp->dmai_nwin - # of total DMA windows on mp->dmai_winlst. 1177 * mp->dmai_mapping - starting cookie address 1178 * mp->dmai_rflags - consistent, nosync, no redzone 1179 * mp->dmai_cookie - start of cookie table of the 1st DMA window 1180 * 1181 * Restriction: 1182 * Each px_dma_win_t object can theoratically start from any offset 1183 * since the mmu is not involved. However, this implementation 1184 * always make windows start from page aligned offset (except 1185 * the 1st window, which follows the requested offset) due to the 1186 * fact that we are handed a pfn list. This does require device's 1187 * count_max and attr_seg to be at least MMU_PAGE_SIZE aligned. 1188 */ 1189 int 1190 px_dma_physwin(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 1191 { 1192 uint_t npages = mp->dmai_ndvmapages; 1193 int ret, sgllen = mp->dmai_attr.dma_attr_sgllen; 1194 px_iopfn_t pfn_lo, pfn_hi, prev_pfn; 1195 px_iopfn_t pfn = PX_GET_MP_PFN(mp, 0); 1196 uint32_t i, win_no = 0, pfn_no = 1, win_pfn0_index = 0, cookie_no = 0; 1197 uint64_t count_max, bypass_addr = 0; 1198 px_dma_win_t **win_pp = (px_dma_win_t **)&mp->dmai_winlst; 1199 ddi_dma_cookie_t *cookie0_p; 1200 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 1201 mp->dmai_attr.dma_attr_flags); 1202 dev_info_t *dip = px_p->px_dip; 1203 1204 ASSERT(PX_DMA_ISPTP(mp) || PX_DMA_ISBYPASS(mp)); 1205 if (PX_DMA_ISPTP(mp)) { /* ignore sys limits for peer-to-peer */ 1206 ddi_dma_attr_t *dev_attr_p = PX_DEV_ATTR(mp); 1207 uint64_t nocross = dev_attr_p->dma_attr_seg; 1208 px_pec_t *pec_p = px_p->px_pec_p; 1209 px_iopfn_t pfn_last = PX_DMA_ISPTP32(mp) ? 1210 pec_p->pec_last32_pfn - pec_p->pec_base32_pfn : 1211 pec_p->pec_last64_pfn - pec_p->pec_base64_pfn; 1212 1213 if (nocross && (nocross < UINT32_MAX)) 1214 return (DDI_DMA_NOMAPPING); 1215 if (dev_attr_p->dma_attr_align > MMU_PAGE_SIZE) 1216 return (DDI_DMA_NOMAPPING); 1217 pfn_lo = MMU_BTOP(dev_attr_p->dma_attr_addr_lo); 1218 pfn_hi = MMU_BTOP(dev_attr_p->dma_attr_addr_hi); 1219 pfn_hi = MIN(pfn_hi, pfn_last); 1220 if ((pfn_lo > pfn_hi) || (pfn < pfn_lo)) 1221 return (DDI_DMA_NOMAPPING); 1222 1223 count_max = dev_attr_p->dma_attr_count_max; 1224 count_max = MIN(count_max, nocross); 1225 /* 1226 * the following count_max trim is not done because we are 1227 * making sure pfn_lo <= pfn <= pfn_hi inside the loop 1228 * count_max=MIN(count_max, MMU_PTOB(pfn_hi - pfn_lo + 1)-1); 1229 */ 1230 } else { /* bypass hi/lo/count_max have been processed by attr2hdl() */ 1231 count_max = mp->dmai_attr.dma_attr_count_max; 1232 pfn_lo = MMU_BTOP(mp->dmai_attr.dma_attr_addr_lo); 1233 pfn_hi = MMU_BTOP(mp->dmai_attr.dma_attr_addr_hi); 1234 1235 if (px_lib_iommu_getbypass(dip, MMU_PTOB(pfn), 1236 attr, &bypass_addr) != DDI_SUCCESS) { 1237 cmn_err(CE_WARN, "bypass cookie failure %lx\n", pfn); 1238 return (DDI_DMA_NOMAPPING); 1239 } 1240 pfn = MMU_BTOP(bypass_addr); 1241 } 1242 1243 /* pfn: absolute (bypass mode) or relative (p2p mode) */ 1244 for (prev_pfn = pfn, i = 1; i < npages; 1245 i++, prev_pfn = pfn, pfn_no++) { 1246 pfn = PX_GET_MP_PFN1(mp, i); 1247 if (bypass_addr) { 1248 if (px_lib_iommu_getbypass(dip, MMU_PTOB(pfn), attr, 1249 &bypass_addr) != DDI_SUCCESS) { 1250 ret = DDI_DMA_NOMAPPING; 1251 goto err; 1252 } 1253 pfn = MMU_BTOP(bypass_addr); 1254 } 1255 if ((pfn == prev_pfn + 1) && 1256 (MMU_PTOB(pfn_no + 1) - 1 <= count_max)) 1257 continue; 1258 if ((pfn < pfn_lo) || (prev_pfn > pfn_hi)) { 1259 ret = DDI_DMA_NOMAPPING; 1260 goto err; 1261 } 1262 cookie_no++; 1263 pfn_no = 0; 1264 if (cookie_no < sgllen) 1265 continue; 1266 1267 DBG(DBG_BYPASS, mp->dmai_rdip, "newwin pfn[%x-%x] %x cks\n", 1268 win_pfn0_index, i - 1, cookie_no); 1269 if (ret = px_dma_newwin(dip, dmareq, mp, cookie_no, 1270 win_pfn0_index, i - 1, win_pp, count_max, bypass_addr)) 1271 goto err; 1272 1273 win_pp = &(*win_pp)->win_next; /* win_pp = *(win_pp) */ 1274 win_no++; 1275 win_pfn0_index = i; 1276 cookie_no = 0; 1277 } 1278 if (pfn > pfn_hi) { 1279 ret = DDI_DMA_NOMAPPING; 1280 goto err; 1281 } 1282 cookie_no++; 1283 DBG(DBG_BYPASS, mp->dmai_rdip, "newwin pfn[%x-%x] %x cks\n", 1284 win_pfn0_index, i - 1, cookie_no); 1285 if (ret = px_dma_newwin(dip, dmareq, mp, cookie_no, win_pfn0_index, 1286 i - 1, win_pp, count_max, bypass_addr)) 1287 goto err; 1288 win_no++; 1289 px_dma_adjust(dmareq, mp, mp->dmai_winlst); 1290 mp->dmai_nwin = win_no; 1291 mp->dmai_rflags |= DDI_DMA_CONSISTENT | DMP_NOSYNC; 1292 mp->dmai_rflags &= ~DDI_DMA_REDZONE; 1293 mp->dmai_flags |= PX_DMAI_FLAGS_NOSYNC; 1294 cookie0_p = (ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); 1295 mp->dmai_cookie = PX_WINLST(mp)->win_ncookies > 1 ? cookie0_p + 1 : 0; 1296 mp->dmai_mapping = cookie0_p->dmac_laddress; 1297 1298 px_dma_freepfn(mp); 1299 return (DDI_DMA_MAPPED); 1300 err: 1301 px_dma_freewin(mp); 1302 return (ret); 1303 } 1304 1305 int 1306 px_dma_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_impl_t *mp, 1307 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1308 uint_t cache_flags) 1309 { 1310 switch (cmd) { 1311 case DDI_DMA_SYNC: 1312 return (DDI_SUCCESS); 1313 1314 case DDI_DMA_HTOC: { 1315 off_t off = *offp; 1316 ddi_dma_cookie_t *loop_cp, *cp; 1317 px_dma_win_t *win_p = mp->dmai_winlst; 1318 1319 if (off >= mp->dmai_object.dmao_size) 1320 return (DDI_FAILURE); 1321 1322 /* locate window */ 1323 while (win_p->win_offset + win_p->win_size <= off) 1324 win_p = win_p->win_next; 1325 1326 loop_cp = cp = (ddi_dma_cookie_t *)(win_p + 1); 1327 mp->dmai_offset = win_p->win_offset; 1328 mp->dmai_size = win_p->win_size; 1329 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 start addr */ 1330 1331 /* adjust cookie addr/len if we are not on cookie boundary */ 1332 off -= win_p->win_offset; /* offset within window */ 1333 for (; off >= loop_cp->dmac_size; loop_cp++) 1334 off -= loop_cp->dmac_size; /* offset within cookie */ 1335 1336 mp->dmai_cookie = loop_cp + 1; 1337 win_p->win_curseg = loop_cp - cp; 1338 cp = (ddi_dma_cookie_t *)objp; 1339 MAKE_DMA_COOKIE(cp, loop_cp->dmac_laddress + off, 1340 loop_cp->dmac_size - off); 1341 1342 DBG(DBG_DMA_CTL, dip, 1343 "HTOC: cookie - dmac_laddress=%p dmac_size=%x\n", 1344 cp->dmac_laddress, cp->dmac_size); 1345 } 1346 return (DDI_SUCCESS); 1347 1348 case DDI_DMA_REPWIN: 1349 *offp = mp->dmai_offset; 1350 *lenp = mp->dmai_size; 1351 return (DDI_SUCCESS); 1352 1353 case DDI_DMA_MOVWIN: { 1354 off_t off = *offp; 1355 ddi_dma_cookie_t *cp; 1356 px_dma_win_t *win_p = mp->dmai_winlst; 1357 1358 if (off >= mp->dmai_object.dmao_size) 1359 return (DDI_FAILURE); 1360 1361 /* locate window */ 1362 while (win_p->win_offset + win_p->win_size <= off) 1363 win_p = win_p->win_next; 1364 1365 cp = (ddi_dma_cookie_t *)(win_p + 1); 1366 mp->dmai_offset = win_p->win_offset; 1367 mp->dmai_size = win_p->win_size; 1368 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 star addr */ 1369 mp->dmai_cookie = cp + 1; 1370 win_p->win_curseg = 0; 1371 1372 *(ddi_dma_cookie_t *)objp = *cp; 1373 *offp = win_p->win_offset; 1374 *lenp = win_p->win_size; 1375 DBG(DBG_DMA_CTL, dip, 1376 "HTOC: cookie - dmac_laddress=%p dmac_size=%x\n", 1377 cp->dmac_laddress, cp->dmac_size); 1378 } 1379 return (DDI_SUCCESS); 1380 1381 case DDI_DMA_NEXTWIN: { 1382 px_dma_win_t *win_p = *(px_dma_win_t **)offp; 1383 px_dma_win_t **nw_pp = (px_dma_win_t **)objp; 1384 ddi_dma_cookie_t *cp; 1385 if (!win_p) { 1386 *nw_pp = mp->dmai_winlst; 1387 return (DDI_SUCCESS); 1388 } 1389 1390 if (win_p->win_offset != mp->dmai_offset) 1391 return (DDI_DMA_STALE); 1392 if (!win_p->win_next) 1393 return (DDI_DMA_DONE); 1394 win_p = win_p->win_next; 1395 cp = (ddi_dma_cookie_t *)(win_p + 1); 1396 mp->dmai_offset = win_p->win_offset; 1397 mp->dmai_size = win_p->win_size; 1398 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 star addr */ 1399 mp->dmai_cookie = cp + 1; 1400 win_p->win_curseg = 0; 1401 *nw_pp = win_p; 1402 } 1403 return (DDI_SUCCESS); 1404 1405 case DDI_DMA_NEXTSEG: { 1406 px_dma_win_t *w_p = *(px_dma_win_t **)offp; 1407 if (w_p->win_offset != mp->dmai_offset) 1408 return (DDI_DMA_STALE); 1409 if (w_p->win_curseg + 1 >= w_p->win_ncookies) 1410 return (DDI_DMA_DONE); 1411 w_p->win_curseg++; 1412 } 1413 *(ddi_dma_seg_t *)objp = (ddi_dma_seg_t)mp; 1414 return (DDI_SUCCESS); 1415 1416 case DDI_DMA_SEGTOC: { 1417 px_dma_win_t *win_p = mp->dmai_winlst; 1418 off_t off = mp->dmai_offset; 1419 ddi_dma_cookie_t *cp; 1420 int i; 1421 1422 /* locate active window */ 1423 for (; win_p->win_offset != off; win_p = win_p->win_next); 1424 cp = (ddi_dma_cookie_t *)(win_p + 1); 1425 for (i = 0; i < win_p->win_curseg; i++, cp++) 1426 off += cp->dmac_size; 1427 *offp = off; 1428 *lenp = cp->dmac_size; 1429 *(ddi_dma_cookie_t *)objp = *cp; /* copy cookie */ 1430 } 1431 return (DDI_SUCCESS); 1432 1433 case DDI_DMA_COFF: { 1434 px_dma_win_t *win_p; 1435 ddi_dma_cookie_t *cp; 1436 uint64_t addr, key = ((ddi_dma_cookie_t *)offp)->dmac_laddress; 1437 size_t win_off; 1438 1439 for (win_p = mp->dmai_winlst; win_p; win_p = win_p->win_next) { 1440 int i; 1441 win_off = 0; 1442 cp = (ddi_dma_cookie_t *)(win_p + 1); 1443 for (i = 0; i < win_p->win_ncookies; i++, cp++) { 1444 size_t sz = cp->dmac_size; 1445 1446 addr = cp->dmac_laddress; 1447 if ((addr <= key) && (addr + sz >= key)) 1448 goto found; 1449 win_off += sz; 1450 } 1451 } 1452 return (DDI_FAILURE); 1453 found: 1454 *objp = (caddr_t)(win_p->win_offset + win_off + (key - addr)); 1455 return (DDI_SUCCESS); 1456 } 1457 default: 1458 DBG(DBG_DMA_CTL, dip, "unknown command (%x): rdip=%s%d\n", 1459 cmd, ddi_driver_name(rdip), ddi_get_instance(rdip)); 1460 break; 1461 } 1462 return (DDI_FAILURE); 1463 } 1464 1465 static void 1466 px_dvma_debug_init(px_mmu_t *mmu_p) 1467 { 1468 size_t sz = sizeof (struct px_dvma_rec) * px_dvma_debug_rec; 1469 ASSERT(MUTEX_HELD(&mmu_p->dvma_debug_lock)); 1470 cmn_err(CE_NOTE, "PCI Express DVMA %p stat ON", mmu_p); 1471 1472 mmu_p->dvma_alloc_rec = kmem_alloc(sz, KM_SLEEP); 1473 mmu_p->dvma_free_rec = kmem_alloc(sz, KM_SLEEP); 1474 1475 mmu_p->dvma_active_list = NULL; 1476 mmu_p->dvma_alloc_rec_index = 0; 1477 mmu_p->dvma_free_rec_index = 0; 1478 mmu_p->dvma_active_count = 0; 1479 } 1480 1481 void 1482 px_dvma_debug_fini(px_mmu_t *mmu_p) 1483 { 1484 struct px_dvma_rec *prev, *ptr; 1485 size_t sz = sizeof (struct px_dvma_rec) * px_dvma_debug_rec; 1486 uint64_t mask = ~(1ull << mmu_p->mmu_inst); 1487 cmn_err(CE_NOTE, "PCI Express DVMA %p stat OFF", mmu_p); 1488 1489 kmem_free(mmu_p->dvma_alloc_rec, sz); 1490 kmem_free(mmu_p->dvma_free_rec, sz); 1491 mmu_p->dvma_alloc_rec = mmu_p->dvma_free_rec = NULL; 1492 1493 prev = mmu_p->dvma_active_list; 1494 if (!prev) 1495 return; 1496 for (ptr = prev->next; ptr; prev = ptr, ptr = ptr->next) 1497 kmem_free(prev, sizeof (struct px_dvma_rec)); 1498 kmem_free(prev, sizeof (struct px_dvma_rec)); 1499 1500 mmu_p->dvma_active_list = NULL; 1501 mmu_p->dvma_alloc_rec_index = 0; 1502 mmu_p->dvma_free_rec_index = 0; 1503 mmu_p->dvma_active_count = 0; 1504 1505 px_dvma_debug_off &= mask; 1506 px_dvma_debug_on &= mask; 1507 } 1508 1509 void 1510 px_dvma_alloc_debug(px_mmu_t *mmu_p, char *address, uint_t len, 1511 ddi_dma_impl_t *mp) 1512 { 1513 struct px_dvma_rec *ptr; 1514 mutex_enter(&mmu_p->dvma_debug_lock); 1515 1516 if (!mmu_p->dvma_alloc_rec) 1517 px_dvma_debug_init(mmu_p); 1518 if (PX_DVMA_DBG_OFF(mmu_p)) { 1519 px_dvma_debug_fini(mmu_p); 1520 goto done; 1521 } 1522 1523 ptr = &mmu_p->dvma_alloc_rec[mmu_p->dvma_alloc_rec_index]; 1524 ptr->dvma_addr = address; 1525 ptr->len = len; 1526 ptr->mp = mp; 1527 if (++mmu_p->dvma_alloc_rec_index == px_dvma_debug_rec) 1528 mmu_p->dvma_alloc_rec_index = 0; 1529 1530 ptr = kmem_alloc(sizeof (struct px_dvma_rec), KM_SLEEP); 1531 ptr->dvma_addr = address; 1532 ptr->len = len; 1533 ptr->mp = mp; 1534 1535 ptr->next = mmu_p->dvma_active_list; 1536 mmu_p->dvma_active_list = ptr; 1537 mmu_p->dvma_active_count++; 1538 done: 1539 mutex_exit(&mmu_p->dvma_debug_lock); 1540 } 1541 1542 void 1543 px_dvma_free_debug(px_mmu_t *mmu_p, char *address, uint_t len, 1544 ddi_dma_impl_t *mp) 1545 { 1546 struct px_dvma_rec *ptr, *ptr_save; 1547 mutex_enter(&mmu_p->dvma_debug_lock); 1548 1549 if (!mmu_p->dvma_alloc_rec) 1550 px_dvma_debug_init(mmu_p); 1551 if (PX_DVMA_DBG_OFF(mmu_p)) { 1552 px_dvma_debug_fini(mmu_p); 1553 goto done; 1554 } 1555 1556 ptr = &mmu_p->dvma_free_rec[mmu_p->dvma_free_rec_index]; 1557 ptr->dvma_addr = address; 1558 ptr->len = len; 1559 ptr->mp = mp; 1560 if (++mmu_p->dvma_free_rec_index == px_dvma_debug_rec) 1561 mmu_p->dvma_free_rec_index = 0; 1562 1563 ptr_save = mmu_p->dvma_active_list; 1564 for (ptr = ptr_save; ptr; ptr = ptr->next) { 1565 if ((ptr->dvma_addr == address) && (ptr->len = len)) 1566 break; 1567 ptr_save = ptr; 1568 } 1569 if (!ptr) { 1570 cmn_err(CE_WARN, "bad dvma free addr=%lx len=%x", 1571 (long)address, len); 1572 goto done; 1573 } 1574 if (ptr == mmu_p->dvma_active_list) 1575 mmu_p->dvma_active_list = ptr->next; 1576 else 1577 ptr_save->next = ptr->next; 1578 kmem_free(ptr, sizeof (struct px_dvma_rec)); 1579 mmu_p->dvma_active_count--; 1580 done: 1581 mutex_exit(&mmu_p->dvma_debug_lock); 1582 } 1583 1584 #ifdef DEBUG 1585 void 1586 px_dump_dma_handle(uint64_t flag, dev_info_t *dip, ddi_dma_impl_t *hp) 1587 { 1588 DBG(flag, dip, "mp(%p): flags=%x mapping=%lx xfer_size=%x\n", 1589 hp, hp->dmai_inuse, hp->dmai_mapping, hp->dmai_size); 1590 DBG(flag|DBG_CONT, dip, "\tnpages=%x roffset=%x rflags=%x nwin=%x\n", 1591 hp->dmai_ndvmapages, hp->dmai_roffset, hp->dmai_rflags, 1592 hp->dmai_nwin); 1593 DBG(flag|DBG_CONT, dip, "\twinsize=%x tte=%p pfnlst=%p pfn0=%p\n", 1594 hp->dmai_winsize, hp->dmai_tte, hp->dmai_pfnlst, hp->dmai_pfn0); 1595 DBG(flag|DBG_CONT, dip, "\twinlst=%x obj=%p attr=%p ckp=%p\n", 1596 hp->dmai_winlst, &hp->dmai_object, &hp->dmai_attr, 1597 hp->dmai_cookie); 1598 } 1599 #endif /* DEBUG */ 1600