1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2018, Joyent, Inc. 24 * Copyright 2022 Tintri by DDN, Inc. All rights reserved. 25 */ 26 27 #ifndef _SYS_CONTROLREGS_H 28 #define _SYS_CONTROLREGS_H 29 30 #ifndef _ASM 31 #include <sys/types.h> 32 #endif 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * This file describes the x86 architecture control registers which 40 * are part of the privileged architecture. 41 * 42 * Many of these definitions are shared between IA-32-style and 43 * AMD64-style processors. 44 */ 45 46 /* CR0 Register */ 47 48 #define CR0_PG 0x80000000 /* paging enabled */ 49 #define CR0_CD 0x40000000 /* cache disable */ 50 #define CR0_NW 0x20000000 /* not writethrough */ 51 #define CR0_AM 0x00040000 /* alignment mask */ 52 #define CR0_WP 0x00010000 /* write protect */ 53 #define CR0_NE 0x00000020 /* numeric error */ 54 #define CR0_ET 0x00000010 /* extension type */ 55 #define CR0_TS 0x00000008 /* task switch */ 56 #define CR0_EM 0x00000004 /* emulation */ 57 #define CR0_MP 0x00000002 /* monitor coprocessor */ 58 #define CR0_PE 0x00000001 /* protection enabled */ 59 60 /* XX64 eliminate these compatibility defines */ 61 62 #define CR0_CE CR0_CD 63 #define CR0_WT CR0_NW 64 65 #define FMT_CR0 \ 66 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 67 68 /* 69 * Set the FPU-related control bits to explain to the processor that 70 * we're managing FPU state: 71 * - set monitor coprocessor (allow TS bit to control FPU) 72 * - set numeric exception (disable IGNNE# mechanism) 73 * - set task switch (#nm on first fp instruction) 74 * - clear emulate math bit (cause we're not emulating!) 75 */ 76 #define CR0_ENABLE_FPU_FLAGS(cr) \ 77 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM) 78 79 /* 80 * Set the FPU-related control bits to explain to the processor that 81 * we're -not- managing FPU state: 82 * - set emulate (all fp instructions cause #nm) 83 * - clear monitor coprocessor (so fwait/wait doesn't #nm) 84 */ 85 #define CR0_DISABLE_FPU_FLAGS(cr) \ 86 (((cr) | CR0_EM) & (uint32_t)~CR0_MP) 87 88 /* CR3 Register */ 89 90 #define CR3_PCD 0x00000010 /* cache disable */ 91 #define CR3_PWT 0x00000008 /* write through */ 92 #if defined(_ASM) 93 #define CR3_NOINVL_BIT 0x8000000000000000 94 #else 95 #define CR3_NOINVL_BIT 0x8000000000000000ULL /* no invalidation */ 96 #endif 97 #define PCID_NONE 0x000 /* generic PCID */ 98 #define PCID_KERNEL 0x000 /* kernel's PCID */ 99 #define PCID_USER 0x001 /* user-space PCID */ 100 101 /* CR4 Register */ 102 103 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 104 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 105 #define CR4_TSD 0x0004 /* time stamp disable */ 106 #define CR4_DE 0x0008 /* debugging extensions */ 107 #define CR4_PSE 0x0010 /* page size extensions */ 108 #define CR4_PAE 0x0020 /* physical address extension */ 109 #define CR4_MCE 0x0040 /* machine check enable */ 110 #define CR4_PGE 0x0080 /* page global enable */ 111 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 112 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 113 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 114 #define CR4_UMIP 0x0800 /* user-mode instruction prevention */ 115 #define CR4_LA57 0x1000 /* enable 57 bit Logical addressing */ 116 #define CR4_VMXE 0x2000 /* VMX enable */ 117 #define CR4_SMXE 0x4000 /* SMX enable */ 118 /* 0x8000 reserved */ 119 #define CR4_FSGSBASE 0x10000 /* FSGSBASE enable */ 120 #define CR4_PCIDE 0x20000 /* PCID enable */ 121 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */ 122 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */ 123 #define CR4_SMAP 0x200000 /* kernel can't access user pages */ 124 #define CR4_PKE 0x400000 /* protection key enable */ 125 126 #define FMT_CR4 \ 127 "\20\27pke\26smap\25smep\23osxsav" \ 128 "\22pcide\21fsgsbase\17smxe\16vmxe" \ 129 "\15la57\14umip\13xmme\12fxsr\11pce\10pge" \ 130 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 131 132 /* 133 * Enable the SSE-related control bits to explain to the processor that 134 * we're managing XMM state and exceptions 135 */ 136 #define CR4_ENABLE_SSE_FLAGS(cr) \ 137 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT) 138 139 /* 140 * Disable the SSE-related control bits to explain to the processor 141 * that we're NOT managing XMM state 142 */ 143 #define CR4_DISABLE_SSE_FLAGS(cr) \ 144 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT)) 145 146 /* Intel's SYSENTER configuration registers */ 147 148 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 149 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 150 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 151 152 /* Intel's microcode registers */ 153 #define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */ 154 #define MSR_INTC_UCODE_REV 0x8b /* microcode revision */ 155 #define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */ 156 157 /* Intel's platform identification */ 158 #define MSR_INTC_PLATFORM_ID 0x17 159 #define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */ 160 #define INTC_PLATFORM_ID_MASK 0x7 161 162 /* AMD's EFER register */ 163 164 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 165 166 #define AMD_EFER_TCE 0x8000 /* translation cache extension */ 167 #define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */ 168 #define AMD_EFER_LMSLE 0x2000 /* long mode segment limit enable */ 169 #define AMD_EFER_SVME 0x1000 /* svm enable */ 170 #define AMD_EFER_NXE 0x0800 /* no-execute enable */ 171 #define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */ 172 #define AMD_EFER_LME 0x0100 /* long mode enable */ 173 #define AMD_EFER_SCE 0x0001 /* system call extensions */ 174 175 #define FMT_AMD_EFER \ 176 "\20\20tce\17ffxsr\16lmsle\15svme\14nxe\13lma\11lme\1sce" 177 178 /* AMD's SYSCFG register */ 179 180 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 181 182 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 183 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 184 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 185 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 186 187 #define FMT_AMD_SYSCFG \ 188 "\20\26tom2\25mvdm\24mfdm\23mfde" 189 190 /* AMD's syscall/sysret MSRs */ 191 192 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 193 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 194 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 195 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 196 197 /* AMD's FS.base and GS.base MSRs */ 198 199 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 200 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 201 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 202 #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */ 203 204 205 /* AMD's SVM MSRs */ 206 207 #define MSR_AMD_VM_CR 0xc0010114 /* SVM global control */ 208 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 /* SVM host save area address */ 209 210 #define AMD_VM_CR_DPD (1 << 0) 211 #define AMD_VM_CR_R_INIT (1 << 1) 212 #define AMD_VM_CR_DIS_A20M (1 << 2) 213 #define AMD_VM_CR_LOCK (1 << 3) 214 #define AMD_VM_CR_SVMDIS (1 << 4) 215 216 /* AMD's configuration MSRs, weakly documented in the revision guide */ 217 218 #define MSR_AMD_DC_CFG 0xc0011022 219 220 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 221 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 222 223 /* AMD's HWCR MSR */ 224 225 #define MSR_AMD_HWCR 0xc0010015 226 227 #define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3) 228 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ 229 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ 230 231 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 232 233 #define MSR_AMD_NB_CFG 0xc001001f 234 235 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) 236 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32) 237 238 #define MSR_AMD_BU_CFG 0xc0011023 239 240 #define AMD_BU_CFG_E298 (UINT64_C(1) << 1) 241 242 /* 243 * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction 244 * decoding. Most notably, for the AMD variant of retpolines, we must improve 245 * the serializability of lfence for the lfence based method to work. 246 */ 247 #define MSR_AMD_DE_CFG 0xc0011029 248 249 #define AMD_DE_CFG_E721 (1UL << 0) 250 #define AMD_DE_CFG_LFENCE_DISPATCH (1UL << 1) 251 252 /* AMD's osvw MSRs */ 253 #define MSR_AMD_OSVW_ID_LEN 0xc0010140 254 #define MSR_AMD_OSVW_STATUS 0xc0010141 255 256 257 #define OSVW_ID_LEN_MASK 0xffffULL 258 #define OSVW_ID_CNT_PER_MSR 64 259 260 /* 261 * Enable PCI Extended Configuration Space (ECS) on Greyhound 262 */ 263 #define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46) 264 265 /* AMD microcode patch loader */ 266 #define MSR_AMD_PATCHLEVEL 0x8b 267 #define MSR_AMD_PATCHLOADER 0xc0010020 268 269 #ifdef __cplusplus 270 } 271 #endif 272 273 #endif /* !_SYS_CONTROLREGS_H */ 274