1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2018 Joyent, Inc. 24 * Copyright (c) 2017 by Delphix. All rights reserved. 25 */ 26 /* 27 * Copyright (c) 2010, Intel Corporation. 28 * All rights reserved. 29 */ 30 31 #ifndef _SYS_APIC_APIC_H 32 #define _SYS_APIC_APIC_H 33 34 #include <sys/psm_types.h> 35 #include <sys/avintr.h> 36 #include <sys/pci.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <sys/psm_common.h> 43 44 #define APIC_PCPLUSMP_NAME "pcplusmp" 45 #define APIC_APIX_NAME "apix" 46 47 #define APIC_IO_ADDR 0xfec00000 48 #define APIC_LOCAL_ADDR 0xfee00000 49 #define APIC_IO_MEMLEN 0xf 50 #define APIC_LOCAL_MEMLEN 0xfffff 51 52 /* Local Unit ID register */ 53 #define APIC_LID_REG 0x8 54 55 /* I/o Unit Version Register */ 56 #define APIC_VERS_REG 0xc 57 58 /* Task Priority register */ 59 #define APIC_TASK_REG 0x20 60 61 /* EOI register */ 62 #define APIC_EOI_REG 0x2c 63 64 /* Remote Read register */ 65 #define APIC_REMOTE_READ 0x30 66 67 /* Logical Destination register */ 68 #define APIC_DEST_REG 0x34 69 70 /* Destination Format register */ 71 #define APIC_FORMAT_REG 0x38 72 73 /* Spurious Interrupt Vector register */ 74 #define APIC_SPUR_INT_REG 0x3c 75 76 /* Error Status Register */ 77 #define APIC_ERROR_STATUS 0xa0 78 79 /* Interrupt Command registers */ 80 #define APIC_INT_CMD1 0xc0 81 #define APIC_INT_CMD2 0xc4 82 83 /* Local Interrupt Vector registers */ 84 #define APIC_CMCI_VECT 0xbc 85 #define APIC_THERM_VECT 0xcc 86 #define APIC_PCINT_VECT 0xd0 87 #define APIC_INT_VECT0 0xd4 88 #define APIC_INT_VECT1 0xd8 89 #define APIC_ERR_VECT 0xdc 90 91 /* IPL for performance counter interrupts */ 92 #define APIC_PCINT_IPL 0xe 93 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 94 95 /* Initial Count register */ 96 #define APIC_INIT_COUNT 0xe0 97 98 /* Current Count Register */ 99 #define APIC_CURR_COUNT 0xe4 100 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 101 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 102 103 /* Divider Configuration Register */ 104 #define APIC_DIVIDE_REG 0xf8 105 106 /* Various mode for local APIC. Modes are mutually exclusive */ 107 typedef enum apic_mode { 108 APIC_IS_DISABLED = 0, 109 APIC_MODE_NOTSET, 110 LOCAL_APIC, 111 LOCAL_X2APIC 112 } apic_mode_t; 113 114 /* x2APIC SELF IPI Register */ 115 #define X2APIC_SELF_IPI 0xFC 116 117 /* General x2APIC constants used at various places */ 118 #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000 119 #define APIC_DIRECTED_EOI_BIT 0x1000000 120 121 /* x2APIC enable bit in REG_APIC_BASE_MSR */ 122 #define X2APIC_ENABLE_BIT 10 123 124 /* IRR register */ 125 #define APIC_IRR_REG 0x80 126 127 /* ISR register */ 128 #define APIC_ISR_REG 0x40 129 130 #define APIC_IO_REG 0x0 131 #define APIC_IO_DATA 0x4 132 #define APIC_IO_EOI 0x10 133 134 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 135 #define APIC_ID_BIT_OFFSET 24 136 #define APIC_ICR_ID_BIT_OFFSET 24 137 #define APIC_LDR_ID_BIT_OFFSET 24 138 139 /* 140 * Choose between flat and clustered models by writing the following to the 141 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 142 * disable logical destination mode. 143 * Does not seem to be in the docs for local APICs on the processors. 144 */ 145 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 146 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 147 148 /* 149 * The commands which follow are window selectors written to APIC_IO_REG 150 * before data can be read/written from/to APIC_IO_DATA 151 */ 152 153 #define APIC_ID_CMD 0x0 154 #define APIC_VERS_CMD 0x1 155 #define APIC_RDT_CMD 0x10 156 #define APIC_RDT_CMD2 0x11 157 158 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 159 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 160 161 #define APIC_INT_SPURIOUS -1 162 163 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 164 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 165 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 166 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 167 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 168 169 #define APIC_CT_VECT 0x4ac /* conf table vector */ 170 #define APIC_CT_SIZE 1024 /* conf table size */ 171 172 #define APIC_ID 'MPAT' /* conf table signature */ 173 174 #define VENID_AMD 0x1022 175 #define DEVID_8131_IOAPIC 0x7451 176 #define DEVID_8132_IOAPIC 0x7459 177 178 #define IOAPICS_NODE_NAME "ioapics" 179 #define IOAPICS_CHILD_NAME "ioapic" 180 #define IOAPICS_DEV_TYPE "ioapic" 181 #define IOAPICS_PROP_VENID "vendor-id" 182 #define IOAPICS_PROP_DEVID "device-id" 183 184 #define IS_CLASS_IOAPIC(b, s, p) \ 185 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 186 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 187 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 188 189 /* 190 * These macros are used in frequently called routines like 191 * apic_intr_enter(). 192 */ 193 #define X2APIC_WRITE(reg, v) \ 194 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v) 195 196 #define LOCAL_APIC_WRITE_REG(reg, v) \ 197 apicadr[reg] = v 198 199 /* 200 * MP floating pointer structure defined in Intel MP Spec 1.1 201 */ 202 struct apic_mpfps_hdr { 203 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 204 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 205 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 206 uchar_t mpfps_spec_rev; /* version number of MP spec */ 207 uchar_t mpfps_checksum; /* checksum of complete structure */ 208 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 209 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 210 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 211 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 212 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 213 }; 214 215 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 216 217 #define APIC_MPS_OEM_ID_LEN 8 218 #define APIC_MPS_PROD_ID_LEN 12 219 220 struct apic_mp_cnf_hdr { 221 uint_t mpcnf_sig; 222 223 uint_t mpcnf_tbl_length: 16, 224 mpcnf_spec: 8, 225 mpcnf_cksum: 8; 226 227 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 228 229 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 230 231 uint_t mpcnf_oem_ptr; 232 233 uint_t mpcnf_oem_tbl_size: 16, 234 mpcnf_entry_cnt: 16; 235 236 uint_t mpcnf_local_apic; 237 238 uint_t mpcnf_resv; 239 }; 240 241 struct apic_procent { 242 uint_t proc_entry: 8, 243 proc_apicid: 8, 244 proc_version: 8, 245 proc_cpuflags: 8; 246 247 uint_t proc_stepping: 4, 248 proc_model: 4, 249 proc_family: 4, 250 proc_type: 2, /* undocumented feature */ 251 proc_resv1: 18; 252 253 uint_t proc_feature; 254 255 uint_t proc_resv2; 256 257 uint_t proc_resv3; 258 }; 259 260 /* 261 * proc_cpuflags definitions 262 */ 263 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 264 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 265 266 267 struct apic_bus { 268 uchar_t bus_entry; 269 uchar_t bus_id; 270 ushort_t bus_str1; 271 uint_t bus_str2; 272 }; 273 274 struct apic_io_entry { 275 uint_t io_entry: 8, 276 io_apicid: 8, 277 io_version: 8, 278 io_flags: 8; 279 280 uint_t io_apic_addr; 281 }; 282 283 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 284 285 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 286 287 struct apic_io_intr { 288 uint_t intr_entry: 8, 289 intr_type: 8, 290 intr_po: 2, 291 intr_el: 2, 292 intr_resv: 12; 293 294 uint_t intr_busid: 8, 295 intr_irq: 8, 296 intr_destid: 8, 297 intr_destintin: 8; 298 }; 299 300 /* 301 * intr_type definitions 302 */ 303 #define IO_INTR_INT 0x00 304 #define IO_INTR_NMI 0x01 305 #define IO_INTR_SMI 0x02 306 #define IO_INTR_EXTINT 0x03 307 308 /* 309 * destination APIC ID 310 */ 311 #define INTR_ALL_APIC 0xff 312 313 314 /* local vector table */ 315 #define AV_MASK 0x10000 316 317 /* interrupt command register 32-63 */ 318 #define AV_TOALL 0x7fffffff 319 #define AV_HIGH_ORDER 0x40000000 320 #define AV_IM_OFF 0x40000000 321 322 /* interrupt command register 0-31 */ 323 #define AV_DELIV_MODE 0x700 324 325 #define AV_FIXED 0x000 326 #define AV_LOPRI 0x100 327 #define AV_SMI 0x200 328 #define AV_REMOTE 0x300 329 #define AV_NMI 0x400 330 #define AV_RESET 0x500 331 #define AV_STARTUP 0x600 332 #define AV_EXTINT 0x700 333 334 #define AV_PDEST 0x000 335 #define AV_LDEST 0x800 336 337 /* IO & Local APIC Bit Definitions */ 338 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 339 #define AV_PENDING 0x1000 340 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 341 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 342 #define AV_LEVEL 0x8000 343 #define AV_DEASSERT AV_LEVEL 344 #define AV_ASSERT 0xc000 345 346 #define AV_READ_PENDING 0x10000 347 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 348 349 #define AV_SH_SELF 0x40000 /* Short hand for self */ 350 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 351 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 352 /* spurious interrupt vector register */ 353 #define AV_UNIT_ENABLE 0x100 354 355 #define APIC_MAXVAL 0xffffffffUL 356 #define APIC_TIME_MIN 0x5000 357 #define APIC_TIME_COUNT 0x4000 358 359 /* 360 * Range of the low byte value in apic_tick before starting calibration 361 */ 362 #define APIC_LB_MIN 0x60 363 #define APIC_LB_MAX 0xe0 364 365 #define APIC_MAX_VECTOR 255 366 #define APIC_RESV_VECT 0x00 367 #define APIC_RESV_IRQ 0xfe 368 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 369 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 370 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 371 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 372 #define APIC_VECTOR_MASK 0x0f 373 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 374 #define APIC_IPL_MASK 0xf0 375 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 376 #define APIC_FIRST_FREE_IRQ 0x10 377 #define APIC_MAX_ISA_IRQ 15 378 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 379 #define APIC_IDLE_IPL 0x00 380 381 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 382 383 /* spurious interrupt vector */ 384 #define APIC_SPUR_INTR 0xFF 385 386 /* special or reserve vectors */ 387 #define APIC_CHECK_RESERVE_VECTORS(v) \ 388 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 389 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET)) 390 391 /* cmos shutdown code for BIOS */ 392 #define BIOS_SHUTDOWN 0x0a 393 394 /* define the entry types for BIOS information tables as defined in PC+MP */ 395 #define APIC_CPU_ENTRY 0 396 #define APIC_BUS_ENTRY 1 397 #define APIC_IO_ENTRY 2 398 #define APIC_IO_INTR_ENTRY 3 399 #define APIC_LOCAL_INTR_ENTRY 4 400 #define APIC_MPTBL_ADDR (639 * 1024) 401 /* 402 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 403 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 404 */ 405 #define MPFPS_RAM_WIN_LEN 1024 406 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 407 #define MPFPS_ROM_WIN_LEN 0x10000 408 409 #define EISA_LEVEL_CNTL 0x4D0 410 411 /* definitions for apic_irq_table */ 412 #define FREE_INDEX (short)-1 /* empty slot */ 413 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 414 #define ACPI_INDEX (short)-3 /* ACPI */ 415 #define MSI_INDEX (short)-4 /* MSI */ 416 #define MSIX_INDEX (short)-5 /* MSI-X */ 417 #define DEFAULT_INDEX (short)0x7FFF 418 /* biggest positive no. to avoid conflict with actual index */ 419 420 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 421 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 422 423 /* 424 * definitions for MSI Address 425 */ 426 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 427 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 428 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 429 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 430 #define MSI_ADDR_RH_SHIFT 3 431 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 432 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 433 #define MSI_ADDR_DM_SHIFT 2 434 435 /* 436 * TM is either edge or level. 437 */ 438 #define TRIGGER_MODE_EDGE 0x0 /* edge sensitive */ 439 #define TRIGGER_MODE_LEVEL 0x1 /* level sensitive */ 440 441 /* 442 * definitions for MSI Data 443 */ 444 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 445 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 446 #define MSI_DATA_DELIVERY_SMI 0x2 447 #define MSI_DATA_DELIVERY_NMI 0x4 448 #define MSI_DATA_DELIVERY_INIT 0x5 449 #define MSI_DATA_DELIVERY_EXTINT 0x7 450 #define MSI_DATA_DELIVERY_SHIFT 8 451 #define MSI_DATA_TM_EDGE TRIGGER_MODE_EDGE 452 #define MSI_DATA_TM_LEVEL TRIGGER_MODE_LEVEL 453 #define MSI_DATA_TM_SHIFT 15 454 #define MSI_DATA_LEVEL_DEASSERT 0x0 455 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 456 #define MSI_DATA_LEVEL_SHIFT 14 457 458 /* 459 * use to define each irq setup by the apic 460 */ 461 typedef struct apic_irq { 462 short airq_mps_intr_index; /* index into mps interrupt entries */ 463 /* table */ 464 uchar_t airq_intin_no; 465 uchar_t airq_ioapicindex; 466 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 467 /* 468 * IRQ could be shared (in H/W) in which case dip & major will be 469 * for the one that was last added at this level. We cannot keep a 470 * linked list as delspl does not tell us which device has just 471 * been unloaded. For most servers where we are worried about 472 * performance, interrupt should not be shared & should not be 473 * a problem. This does not cause any correctness issue - dip is 474 * used only as an optimisation to avoid going thru all the tables 475 * in translate IRQ (which is always called twice due to brokenness 476 * in the way IPLs are determined for devices). major is used only 477 * to bind interrupts corresponding to the same device on the same 478 * CPU. Not finding major will just cause it to be potentially bound 479 * to another CPU. 480 */ 481 major_t airq_major; /* major number corresponding to the device */ 482 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 483 uint32_t airq_cpu; /* target CPU, non-reserved IRQ only */ 484 uint32_t airq_temp_cpu; /* non-reserved IRQ only, for disable_intr */ 485 uchar_t airq_vector; /* Vector chosen for this irq */ 486 uchar_t airq_share; /* number of interrupts at this irq */ 487 uchar_t airq_share_id; /* id to identify source from irqno */ 488 uchar_t airq_ipl; /* The ipl at which this is handled */ 489 iflag_t airq_iflag; /* interrupt flag */ 490 uchar_t airq_origirq; /* original irq passed in */ 491 uint_t airq_busy; /* How frequently did clock find */ 492 /* us in this */ 493 struct apic_irq *airq_next; /* chain of intpts sharing a vector */ 494 void *airq_intrmap_private; /* intr remap private data */ 495 } apic_irq_t; 496 497 #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */ 498 #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */ 499 #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */ 500 501 /* Macros to help deal with shared interrupts */ 502 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 503 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 504 505 /* 506 * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we 507 * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also 508 * don't want the compiler to optimize apic_cpus_info. 509 */ 510 #define APIC_PADSZ 15 511 512 #pragma pack(1) 513 typedef struct apic_cpus_info { 514 uint32_t aci_local_id; 515 uchar_t aci_local_ver; 516 uchar_t aci_status; 517 uchar_t aci_redistribute; /* Selected for redistribution */ 518 uint_t aci_busy; /* Number of ticks we were in ISR */ 519 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 520 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 521 uchar_t aci_curipl; /* IPL of current ISR */ 522 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 523 uint32_t aci_bound; /* # of user requested binds ? */ 524 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 525 uint32_t aci_processor_id; /* Only used in ACPI mode. */ 526 uchar_t aci_idle; /* The CPU is idle */ 527 /* 528 * Fill to make sure each struct is in separate 64-byte cache line. 529 */ 530 uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */ 531 } apic_cpus_info_t; 532 #pragma pack() 533 534 #define APIC_CPU_ONLINE 0x1 535 #define APIC_CPU_INTR_ENABLE 0x2 536 #define APIC_CPU_FREE 0x4 /* APIC CPU slot is free */ 537 #define APIC_CPU_DIRTY 0x8 /* Slot was once used */ 538 #define APIC_CPU_SUSPEND 0x10 539 540 /* 541 * APIC ops to support various flavors of APIC like APIC and x2APIC. 542 */ 543 typedef struct apic_regs_ops { 544 uint64_t (*apic_read)(uint32_t); 545 void (*apic_write)(uint32_t, uint64_t); 546 int (*apic_get_pri)(void); 547 void (*apic_write_task_reg)(uint64_t); 548 void (*apic_write_int_cmd)(uint32_t, uint32_t); 549 void (*apic_send_eoi)(uint32_t); 550 } apic_reg_ops_t; 551 552 /* 553 * interrupt structure for ioapic and msi 554 */ 555 typedef struct ioapic_rdt { 556 uint32_t ir_lo; 557 uint32_t ir_hi; 558 } ioapic_rdt_t; 559 560 typedef struct msi_regs { 561 uint32_t mr_data; 562 uint64_t mr_addr; 563 }msi_regs_t; 564 565 /* 566 * APIC ops to support intel interrupt remapping 567 */ 568 typedef struct apic_intrmap_ops { 569 int (*apic_intrmap_init)(int); 570 void (*apic_intrmap_enable)(int); 571 void (*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t, 572 int, uchar_t); 573 void (*apic_intrmap_map_entry)(void *, void *, uint16_t, int); 574 void (*apic_intrmap_free_entry)(void **); 575 void (*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *); 576 void (*apic_intrmap_record_msi)(void *, msi_regs_t *); 577 } apic_intrmap_ops_t; 578 579 /* 580 * Various poweroff methods and ports & bits for them 581 */ 582 #define APIC_POWEROFF_NONE 0 583 #define APIC_POWEROFF_VIA_RTC 1 584 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 585 #define APIC_POWEROFF_VIA_SITKA_BMC 3 586 587 /* For RTC */ 588 #define RTC_REGA 0x0a 589 #define PFR_REG 0x4a /* extended control register */ 590 #define PAB_CBIT 0x08 591 #define WF_FLAG 0x02 592 #define KS_FLAG 0x01 593 #define EXT_BANK 0x10 594 595 /* For Aspen/Drake BMC */ 596 597 #define CC_SMS_GET_STATUS 0x40 598 #define CC_SMS_WR_START 0x41 599 #define CC_SMS_WR_NEXT 0x42 600 #define CC_SMS_WR_END 0x43 601 602 #define MISMIC_DATA_REGISTER 0x0ca9 603 #define MISMIC_CNTL_REGISTER 0x0caa 604 #define MISMIC_FLAG_REGISTER 0x0cab 605 606 #define MISMIC_BUSY_MASK 0x01 607 608 /* For Sitka/Cabrillo BMC */ 609 610 #define SMS_GET_STATUS 0x60 611 #define SMS_WRITE_START 0x61 612 #define SMS_WRITE_END 0x62 613 614 #define SMS_DATA_REGISTER 0x0ca2 615 #define SMS_STATUS_REGISTER 0x0ca3 616 #define SMS_COMMAND_REGISTER 0x0ca3 617 618 #define SMS_IBF_MASK 0x02 619 #define SMS_STATE_MASK 0xc0 620 621 #define SMS_IDLE_STATE 0x00 622 #define SMS_READ_STATE 0x40 623 #define SMS_WRITE_STATE 0x80 624 #define SMS_ERROR_STATE 0xc0 625 626 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 627 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 628 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value); 629 630 /* Macros for reading/writing the IOAPIC RDT entries */ 631 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 632 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 633 634 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 635 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 636 637 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 638 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 639 640 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 641 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 642 643 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 644 typedef struct { 645 uint16_t avgi_req_flags; /* request flags - to kernel */ 646 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 647 uint8_t avgi_vector; /* vector */ 648 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 649 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 650 /* Contains num_devs elements. */ 651 } apic_get_intr_t; 652 653 /* Used by PSM_INTR_OP_GET_TYPE to return platform information. */ 654 typedef struct { 655 char *avgi_type; /* platform type - from kernel */ 656 uint32_t avgi_num_intr; /* max intr number - from kernel */ 657 uint32_t avgi_num_cpu; /* max cpu number - from kernel */ 658 } apic_get_type_t; 659 660 /* Masks for avgi_req_flags. */ 661 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 662 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 663 #define PSMGI_REQ_VECTOR 0x4 664 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 665 #define PSMGI_REQ_ALL 0xf /* Request everything */ 666 667 /* Other flags */ 668 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 669 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 670 #define PSMGI_INTRBY_DEFAULT 0x4000 /* PSM specific default value */ 671 #define PSMGI_INTRBY_FLAGS 0xc000 /* Mask for this flag */ 672 673 extern int apic_verbose; 674 675 /* Flag definitions for apic_verbose */ 676 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 677 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 678 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 679 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 680 #define APIC_VERBOSE_INIT 0x00000010 681 #define APIC_VERBOSE_REBIND 0x00000020 682 #define APIC_VERBOSE_ALLOC 0x00000040 683 #define APIC_VERBOSE_IPI 0x00000080 684 #define APIC_VERBOSE_INTR 0x00000100 685 686 /* required test to wait until APIC command is sent on the bus */ 687 #define APIC_AV_PENDING_SET() \ 688 while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \ 689 apic_ret(); 690 691 #ifdef DEBUG 692 693 #define DENT 0x0001 694 extern int apic_debug; 695 /* 696 * set apic_restrict_vector to the # of vectors we want to allow per range 697 * useful in testing shared interrupt logic by setting it to 2 or 3 698 */ 699 extern int apic_restrict_vector; 700 701 #define APIC_DEBUG_MSGBUFSIZE 2048 702 extern int apic_debug_msgbuf[]; 703 extern int apic_debug_msgbufindex; 704 705 /* 706 * Put "int" info into debug buffer. No MP consistency, but light weight. 707 * Good enough for most debugging. 708 */ 709 #define APIC_DEBUG_BUF_PUT(x) \ 710 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 711 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 712 apic_debug_msgbufindex = 0; 713 714 #define APIC_VERBOSE(flag, fmt) \ 715 if (apic_verbose & APIC_VERBOSE_##flag) \ 716 cmn_err fmt; 717 718 #define APIC_VERBOSE_POWEROFF(fmt) \ 719 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 720 prom_printf fmt; 721 722 #else /* DEBUG */ 723 724 #define APIC_VERBOSE(flag, fmt) 725 #define APIC_VERBOSE_POWEROFF(fmt) 726 727 #endif /* DEBUG */ 728 729 #define APIC_VERBOSE_IOAPIC(fmt) APIC_VERBOSE(IOAPIC_FLAG, fmt) 730 #define APIC_VERBOSE_IRQ(fmt) APIC_VERBOSE(IRQ_FLAG, fmt) 731 732 extern int apic_error; 733 /* values which apic_error can take. Not catastrophic, but may help debug */ 734 #define APIC_ERR_BOOT_EOI 0x1 735 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 736 #define APIC_ERR_INVALID_INDEX 0x4 737 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 738 #define APIC_ERR_APIC_ERROR 0x40000000 739 #define APIC_ERR_NMI 0x80000000 740 741 /* 742 * ACPI definitions 743 */ 744 /* _PIC method arguments */ 745 #define ACPI_PIC_MODE 0 746 #define ACPI_APIC_MODE 1 747 748 /* APIC error flags we care about */ 749 #define APIC_SEND_CS_ERROR 0x01 750 #define APIC_RECV_CS_ERROR 0x02 751 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 752 753 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 754 #define APIC_REPROGRAM_MAX_TRIES 10000 755 756 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 757 #define IOAPIC_MASK 1 758 #define IOAPIC_NOMASK 0 759 760 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 761 #define INTR_ROUND_ROBIN 1 762 #define INTR_LOWEST_PRIORITY 2 763 764 struct ioapic_reprogram_data { 765 boolean_t done; 766 apic_irq_t *irqp; 767 /* The CPU to which the int will be bound */ 768 int bindcpu; 769 /* # times the reprogram timeout was called */ 770 unsigned tries; 771 }; 772 773 /* The irq # is implicit in the array index: */ 774 extern struct ioapic_reprogram_data apic_reprogram_info[]; 775 776 extern void apic_intr_exit(int ipl, int irq); 777 extern void x2apic_intr_exit(int ipl, int irq); 778 extern int apic_probe_common(); 779 extern void apic_init_common(); 780 extern void ioapic_init_intr(); 781 extern void ioapic_disable_redirection(); 782 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 783 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 784 extern void apic_cleanup_busy(); 785 extern void apic_intr_redistribute(); 786 extern uchar_t apic_xlate_vector(uchar_t vector); 787 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 788 extern void apic_free_vector(uchar_t vector); 789 extern int apic_allocate_irq(int irq); 790 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 791 uchar_t intin); 792 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 793 struct ioapic_reprogram_data *drep); 794 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 795 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 796 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 797 psm_intr_op_t intr_op, int *result); 798 extern int apic_state(psm_state_request_t *); 799 extern boolean_t apic_cpu_in_range(int cpu); 800 extern int apic_check_msi_support(); 801 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 802 int type); 803 extern int apic_navail_vector(dev_info_t *dip, int pri); 804 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 805 int pri, int behavior); 806 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 807 int pri, int behavior); 808 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 809 int type); 810 extern int apic_get_vector_intr_info(int vecirq, 811 apic_get_intr_t *intr_params_p); 812 extern uchar_t apic_find_multi_vectors(int pri, int count); 813 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 814 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 815 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 816 extern void mapout_apic(caddr_t addr, size_t len); 817 extern void mapout_ioapic(caddr_t addr, size_t len); 818 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 819 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 820 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 821 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 822 extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum, 823 int vector, int count, int target_apic_id); 824 extern char *apic_get_apic_type(); 825 extern uint16_t apic_get_apic_version(); 826 extern void x2apic_send_ipi(); 827 extern void apic_ret(); 828 extern int apic_detect_x2apic(); 829 extern void apic_enable_x2apic(); 830 extern int apic_local_mode(); 831 extern void apic_change_eoi(); 832 extern void apic_send_EOI(uint32_t); 833 extern void apic_send_directed_EOI(uint32_t); 834 extern uint64_t apic_calibrate(); 835 extern void x2apic_send_pir_ipi(processorid_t); 836 837 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 838 extern int apic_forceload; 839 extern apic_cpus_info_t *apic_cpus; 840 #ifdef _MACHDEP 841 extern cpuset_t apic_cpumask; 842 #endif 843 extern uint_t apic_picinit_called; 844 extern uchar_t apic_ipltopri[MAXIPL+1]; 845 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 846 extern int apic_max_device_irq; 847 extern int apic_min_device_irq; 848 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 849 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 850 extern uchar_t apic_io_id[MAX_IO_APIC]; 851 extern lock_t apic_ioapic_lock; 852 extern uint32_t apic_physaddr[MAX_IO_APIC]; 853 extern kmutex_t airq_mutex; 854 extern int apic_first_avail_irq; 855 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 856 extern int apic_imcrp; 857 extern int apic_revector_pending; 858 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 859 extern uchar_t apic_resv_vector[MAXIPL+1]; 860 extern int apic_sample_factor_redistribution; 861 extern int apic_int_busy_mark; 862 extern int apic_int_free_mark; 863 extern int apic_diff_for_redistribution; 864 extern int apic_poweroff_method; 865 extern int apic_enable_acpi; 866 extern int apic_nproc; 867 extern int apic_max_nproc; 868 extern int apic_next_bind_cpu; 869 extern int apic_redistribute_sample_interval; 870 extern int apic_multi_msi_enable; 871 extern int apic_sci_vect; 872 extern int apic_hpet_vect; 873 extern uchar_t apic_ipls[]; 874 extern apic_reg_ops_t *apic_reg_ops; 875 extern apic_reg_ops_t local_apic_regs_ops; 876 extern apic_mode_t apic_mode; 877 extern void x2apic_update_psm(); 878 extern void apic_change_ops(); 879 extern void apic_common_send_ipi(int, int); 880 extern void apic_set_directed_EOI_handler(); 881 extern int apic_directed_EOI_supported(); 882 extern void apic_common_send_pir_ipi(processorid_t); 883 884 extern apic_intrmap_ops_t *apic_vt_ops; 885 886 #ifdef __cplusplus 887 } 888 #endif 889 890 #endif /* _SYS_APIC_APIC_H */ 891