1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #define PSMI_1_5 30 #include <sys/smp_impldefs.h> 31 #include <sys/psm.h> 32 #include <sys/psm_modctl.h> 33 #include <sys/pit.h> 34 #include <sys/cmn_err.h> 35 #include <sys/strlog.h> 36 #include <sys/clock.h> 37 #include <sys/debug.h> 38 #include <sys/rtc.h> 39 #include <sys/x86_archext.h> 40 #include <sys/cpupart.h> 41 #include <sys/cpuvar.h> 42 #include <sys/chip.h> 43 #include <sys/disp.h> 44 #include <sys/cpu.h> 45 #include <sys/archsystm.h> 46 47 #define OFFSETOF(s, m) (size_t)(&(((s *)0)->m)) 48 49 /* 50 * Local function prototypes 51 */ 52 static int mp_disable_intr(processorid_t cpun); 53 static void mp_enable_intr(processorid_t cpun); 54 static void mach_init(); 55 static void mach_picinit(); 56 static uint64_t mach_calchz(uint32_t pit_counter, uint64_t *processor_clks); 57 static int machhztomhz(uint64_t cpu_freq_hz); 58 static uint64_t mach_getcpufreq(void); 59 static void mach_fixcpufreq(void); 60 static int mach_clkinit(int, int *); 61 static void mach_smpinit(void); 62 static void mach_set_softintr(int ipl); 63 static void mach_cpu_start(int cpun); 64 static int mach_softlvl_to_vect(int ipl); 65 static void mach_get_platform(int owner); 66 static void mach_construct_info(); 67 static int mach_translate_irq(dev_info_t *dip, int irqno); 68 static int mach_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, 69 psm_intr_op_t, int *); 70 static timestruc_t mach_tod_get(void); 71 static void mach_tod_set(timestruc_t ts); 72 static void mach_notify_error(int level, char *errmsg); 73 static hrtime_t dummy_hrtime(void); 74 static void dummy_scalehrtime(hrtime_t *); 75 static void cpu_halt(void); 76 static void cpu_wakeup(cpu_t *, int); 77 /* 78 * External reference functions 79 */ 80 extern void return_instr(); 81 extern timestruc_t (*todgetf)(void); 82 extern void (*todsetf)(timestruc_t); 83 extern long gmt_lag; 84 extern uint64_t freq_tsc(uint32_t *); 85 #if defined(__i386) 86 extern uint64_t freq_notsc(uint32_t *); 87 #endif 88 extern void pc_gethrestime(timestruc_t *); 89 90 /* 91 * PSM functions initialization 92 */ 93 void (*psm_shutdownf)(int, int) = return_instr; 94 void (*psm_preshutdownf)(int, int) = return_instr; 95 void (*psm_notifyf)(int) = return_instr; 96 void (*psm_set_idle_cpuf)(int) = return_instr; 97 void (*psm_unset_idle_cpuf)(int) = return_instr; 98 void (*psminitf)() = mach_init; 99 void (*picinitf)() = return_instr; 100 int (*clkinitf)(int, int *) = (int (*)(int, int *))return_instr; 101 void (*cpu_startf)() = return_instr; 102 int (*ap_mlsetup)() = (int (*)(void))return_instr; 103 void (*send_dirintf)() = return_instr; 104 void (*setspl)(int) = return_instr; 105 int (*addspl)(int, int, int, int) = (int (*)(int, int, int, int))return_instr; 106 int (*delspl)(int, int, int, int) = (int (*)(int, int, int, int))return_instr; 107 void (*setsoftint)(int) = (void (*)(int))return_instr; 108 int (*slvltovect)(int) = (int (*)(int))return_instr; 109 int (*setlvl)(int, int *) = (int (*)(int, int *))return_instr; 110 void (*setlvlx)(int, int) = (void (*)(int, int))return_instr; 111 int (*psm_disable_intr)(int) = mp_disable_intr; 112 void (*psm_enable_intr)(int) = mp_enable_intr; 113 hrtime_t (*gethrtimef)(void) = dummy_hrtime; 114 hrtime_t (*gethrtimeunscaledf)(void) = dummy_hrtime; 115 void (*scalehrtimef)(hrtime_t *) = dummy_scalehrtime; 116 int (*psm_translate_irq)(dev_info_t *, int) = mach_translate_irq; 117 void (*gethrestimef)(timestruc_t *) = pc_gethrestime; 118 int (*psm_todgetf)(todinfo_t *) = (int (*)(todinfo_t *))return_instr; 119 int (*psm_todsetf)(todinfo_t *) = (int (*)(todinfo_t *))return_instr; 120 void (*psm_notify_error)(int, char *) = (void (*)(int, char *))NULL; 121 int (*psm_get_clockirq)(int) = NULL; 122 int (*psm_get_ipivect)(int, int) = NULL; 123 124 int (*psm_clkinit)(int) = NULL; 125 void (*psm_timer_reprogram)(hrtime_t) = NULL; 126 void (*psm_timer_enable)(void) = NULL; 127 void (*psm_timer_disable)(void) = NULL; 128 void (*psm_post_cyclic_setup)(void *arg) = NULL; 129 int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, psm_intr_op_t, 130 int *) = mach_intr_ops; 131 132 void (*notify_error)(int, char *) = (void (*)(int, char *))return_instr; 133 void (*hrtime_tick)(void) = return_instr; 134 135 int tsc_gethrtime_enable = 1; 136 int tsc_gethrtime_initted = 0; 137 138 /* 139 * Local Static Data 140 */ 141 static struct psm_ops mach_ops; 142 static struct psm_ops *mach_set[4] = {&mach_ops, NULL, NULL, NULL}; 143 static ushort_t mach_ver[4] = {0, 0, 0, 0}; 144 145 /* 146 * If non-zero, idle cpus will "halted" when there's 147 * no work to do. 148 */ 149 int halt_idle_cpus = 1; 150 151 #if defined(__amd64) 152 /* 153 * If non-zero, will use cr8 for interrupt priority masking 154 * We declare this here since install_spl is called from here 155 * (where this is checked). 156 */ 157 int intpri_use_cr8 = 0; 158 #endif /* __amd64 */ 159 160 #ifdef _SIMULATOR_SUPPORT 161 162 int simulator_run = 0; /* patch to non-zero if running under simics */ 163 164 #endif /* _SIMULATOR_SUPPORT */ 165 166 /* ARGSUSED */ 167 void 168 chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 169 { 170 if (x86_feature & (X86_HTT|X86_CMP)) 171 /* 172 * Hyperthreading is SMT 173 */ 174 cd->chipd_type = CHIP_SMT; 175 else 176 cd->chipd_type = CHIP_DEFAULT; 177 178 cd->chipd_rechoose_adj = 0; 179 } 180 181 /* 182 * Routine to ensure initial callers to hrtime gets 0 as return 183 */ 184 static hrtime_t 185 dummy_hrtime(void) 186 { 187 return (0); 188 } 189 190 /* ARGSUSED */ 191 static void 192 dummy_scalehrtime(hrtime_t *ticks) 193 {} 194 195 /* 196 * Halt the present CPU until awoken via an interrupt 197 */ 198 static void 199 cpu_halt(void) 200 { 201 cpu_t *cpup = CPU; 202 processorid_t cpun = cpup->cpu_id; 203 cpupart_t *cp; 204 int hset_update = 1; 205 206 /* 207 * If this CPU is online, and there's multiple CPUs 208 * in the system, then we should notate our halting 209 * by adding ourselves to the partition's halted CPU 210 * bitmap. This allows other CPUs to find/awaken us when 211 * work becomes available. 212 */ 213 if (cpup->cpu_flags & CPU_OFFLINE || ncpus == 1) 214 hset_update = 0; 215 /* 216 * We're on our way to being halted. 217 * Disable interrupts now, so that we'll awaken immediately 218 * after halting if someone tries to poke us between now and 219 * the time we actually halt. 220 */ 221 cli(); 222 223 /* 224 * Add ourselves to the partition's halted CPUs bitmask 225 * and set our HALTED flag, if necessary. 226 * 227 * Note that memory barriers after updating the HALTED flag 228 * are not necessary since an atomic operation (updating the bitmap) 229 * immediately follows. On x86 the atomic operation acts as a 230 * memory barrier for the update of cpu_disp_flags. 231 * If and when this code is made common (running on SPARC), 232 * membar_producer()s will be needed after the update of 233 * cpu_disp_flags to propagate the HALTED flag to global visibility. 234 */ 235 if (hset_update) { 236 cpup->cpu_disp_flags |= CPU_DISP_HALTED; 237 cp = cpup->cpu_part; 238 CPUSET_ATOMIC_ADD(cp->cp_haltset, cpun); 239 } 240 241 /* 242 * Check to make sure there's really nothing to do. 243 * If work becomes available *after* we do this check 244 * and it's determined that the work should be ours, 245 * we won't miss it since we'll be notified with a "poke" 246 * ...which will pop us right back out of the halted state. 247 */ 248 if (disp_anywork()) { 249 if (hset_update) { 250 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 251 CPUSET_ATOMIC_DEL(cp->cp_haltset, cpun); 252 } 253 sti(); 254 return; 255 } 256 257 /* 258 * Call the halt sequence: 259 * sti 260 * hlt 261 */ 262 i86_halt(); 263 264 /* 265 * We're no longer halted 266 */ 267 if (hset_update) { 268 cpup->cpu_disp_flags &= ~CPU_DISP_HALTED; 269 CPUSET_ATOMIC_DEL(cp->cp_haltset, cpun); 270 } 271 } 272 273 274 /* 275 * If "cpu" is halted, then wake it up clearing its halted bit in advance. 276 * Otherwise, see if other CPUs in the cpu partition are halted and need to 277 * be woken up so that they can steal the thread we placed on this CPU. 278 * This function is only used on MP systems. 279 */ 280 static void 281 cpu_wakeup(cpu_t *cpu, int bound) 282 { 283 uint_t cpu_found; 284 int result; 285 cpupart_t *cp; 286 287 cp = cpu->cpu_part; 288 if (CPU_IN_SET(cp->cp_haltset, cpu->cpu_id)) { 289 /* 290 * Clear the halted bit for that CPU since it will be 291 * poked in a moment. 292 */ 293 CPUSET_ATOMIC_DEL(cp->cp_haltset, cpu->cpu_id); 294 /* 295 * We may find the current CPU present in the halted cpuset 296 * if we're in the context of an interrupt that occurred 297 * before we had a chance to clear our bit in cpu_halt(). 298 * Poking ourself is obviously unnecessary, since if 299 * we're here, we're not halted. 300 */ 301 if (cpu != CPU) 302 poke_cpu(cpu->cpu_id); 303 return; 304 } else { 305 /* 306 * This cpu isn't halted, but it's idle or undergoing a 307 * context switch. No need to awaken anyone else. 308 */ 309 if (cpu->cpu_thread == cpu->cpu_idle_thread || 310 cpu->cpu_disp_flags & CPU_DISP_DONTSTEAL) 311 return; 312 } 313 314 /* 315 * No need to wake up other CPUs if the thread we just enqueued 316 * is bound. 317 */ 318 if (bound) 319 return; 320 321 322 /* 323 * See if there's any other halted CPUs. If there are, then 324 * select one, and awaken it. 325 * It's possible that after we find a CPU, somebody else 326 * will awaken it before we get the chance. 327 * In that case, look again. 328 */ 329 do { 330 CPUSET_FIND(cp->cp_haltset, cpu_found); 331 if (cpu_found == CPUSET_NOTINSET) 332 return; 333 334 ASSERT(cpu_found >= 0 && cpu_found < NCPU); 335 CPUSET_ATOMIC_XDEL(cp->cp_haltset, cpu_found, result); 336 } while (result < 0); 337 338 if (cpu_found != CPU->cpu_id) 339 poke_cpu(cpu_found); 340 } 341 342 static int 343 mp_disable_intr(int cpun) 344 { 345 /* 346 * switch to the offline cpu 347 */ 348 affinity_set(cpun); 349 /* 350 * raise ipl to just below cross call 351 */ 352 splx(XC_MED_PIL-1); 353 /* 354 * set base spl to prevent the next swtch to idle from 355 * lowering back to ipl 0 356 */ 357 CPU->cpu_intr_actv |= (1 << (XC_MED_PIL-1)); 358 set_base_spl(); 359 affinity_clear(); 360 return (DDI_SUCCESS); 361 } 362 363 static void 364 mp_enable_intr(int cpun) 365 { 366 /* 367 * switch to the online cpu 368 */ 369 affinity_set(cpun); 370 /* 371 * clear the interrupt active mask 372 */ 373 CPU->cpu_intr_actv &= ~(1 << (XC_MED_PIL-1)); 374 set_base_spl(); 375 (void) spl0(); 376 affinity_clear(); 377 } 378 379 static void 380 mach_get_platform(int owner) 381 { 382 void **srv_opsp; 383 void **clt_opsp; 384 int i; 385 int total_ops; 386 387 /* fix up psm ops */ 388 srv_opsp = (void **)mach_set[0]; 389 clt_opsp = (void **)mach_set[owner]; 390 if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01) 391 total_ops = sizeof (struct psm_ops_ver01) / 392 sizeof (void (*)(void)); 393 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_1) 394 /* no psm_notify_func */ 395 total_ops = OFFSETOF(struct psm_ops, psm_notify_func) / 396 sizeof (void (*)(void)); 397 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_2) 398 /* no psm_timer funcs */ 399 total_ops = OFFSETOF(struct psm_ops, psm_timer_reprogram) / 400 sizeof (void (*)(void)); 401 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_3) 402 /* no psm_preshutdown function */ 403 total_ops = OFFSETOF(struct psm_ops, psm_preshutdown) / 404 sizeof (void (*)(void)); 405 else if (mach_ver[owner] == (ushort_t)PSM_INFO_VER01_4) 406 /* no psm_preshutdown function */ 407 total_ops = OFFSETOF(struct psm_ops, psm_intr_ops) / 408 sizeof (void (*)(void)); 409 else 410 total_ops = sizeof (struct psm_ops) / sizeof (void (*)(void)); 411 412 /* 413 * Save the version of the PSM module, in case we need to 414 * bahave differently based on version. 415 */ 416 mach_ver[0] = mach_ver[owner]; 417 418 for (i = 0; i < total_ops; i++) 419 if (clt_opsp[i] != NULL) 420 srv_opsp[i] = clt_opsp[i]; 421 } 422 423 static void 424 mach_construct_info() 425 { 426 register struct psm_sw *swp; 427 int mach_cnt[PSM_OWN_OVERRIDE+1] = {0}; 428 int conflict_owner = 0; 429 430 if (psmsw->psw_forw == psmsw) 431 panic("No valid PSM modules found"); 432 mutex_enter(&psmsw_lock); 433 for (swp = psmsw->psw_forw; swp != psmsw; swp = swp->psw_forw) { 434 if (!(swp->psw_flag & PSM_MOD_IDENTIFY)) 435 continue; 436 mach_set[swp->psw_infop->p_owner] = swp->psw_infop->p_ops; 437 mach_ver[swp->psw_infop->p_owner] = swp->psw_infop->p_version; 438 mach_cnt[swp->psw_infop->p_owner]++; 439 } 440 mutex_exit(&psmsw_lock); 441 442 mach_get_platform(PSM_OWN_SYS_DEFAULT); 443 444 /* check to see are there any conflicts */ 445 if (mach_cnt[PSM_OWN_EXCLUSIVE] > 1) 446 conflict_owner = PSM_OWN_EXCLUSIVE; 447 if (mach_cnt[PSM_OWN_OVERRIDE] > 1) 448 conflict_owner = PSM_OWN_OVERRIDE; 449 if (conflict_owner) { 450 /* remove all psm modules except uppc */ 451 cmn_err(CE_WARN, 452 "Conflicts detected on the following PSM modules:"); 453 mutex_enter(&psmsw_lock); 454 for (swp = psmsw->psw_forw; swp != psmsw; swp = swp->psw_forw) { 455 if (swp->psw_infop->p_owner == conflict_owner) 456 cmn_err(CE_WARN, "%s ", 457 swp->psw_infop->p_mach_idstring); 458 } 459 mutex_exit(&psmsw_lock); 460 cmn_err(CE_WARN, 461 "Setting the system back to SINGLE processor mode!"); 462 cmn_err(CE_WARN, 463 "Please edit /etc/mach to remove the invalid PSM module."); 464 return; 465 } 466 467 if (mach_set[PSM_OWN_EXCLUSIVE]) 468 mach_get_platform(PSM_OWN_EXCLUSIVE); 469 470 if (mach_set[PSM_OWN_OVERRIDE]) 471 mach_get_platform(PSM_OWN_OVERRIDE); 472 } 473 474 static void 475 mach_init() 476 { 477 register struct psm_ops *pops; 478 479 mach_construct_info(); 480 481 pops = mach_set[0]; 482 483 /* register the interrupt and clock initialization rotuines */ 484 picinitf = mach_picinit; 485 clkinitf = mach_clkinit; 486 psm_get_clockirq = pops->psm_get_clockirq; 487 488 /* register the interrupt setup code */ 489 slvltovect = mach_softlvl_to_vect; 490 addspl = pops->psm_addspl; 491 delspl = pops->psm_delspl; 492 493 if (pops->psm_translate_irq) 494 psm_translate_irq = pops->psm_translate_irq; 495 if (pops->psm_intr_ops) 496 psm_intr_ops = pops->psm_intr_ops; 497 if (pops->psm_tod_get) { 498 todgetf = mach_tod_get; 499 psm_todgetf = pops->psm_tod_get; 500 } 501 if (pops->psm_tod_set) { 502 todsetf = mach_tod_set; 503 psm_todsetf = pops->psm_tod_set; 504 } 505 if (pops->psm_notify_error) { 506 psm_notify_error = mach_notify_error; 507 notify_error = pops->psm_notify_error; 508 } 509 510 (*pops->psm_softinit)(); 511 512 /* 513 * Initialize the dispatcher's function hooks 514 * to enable CPU halting when idle 515 */ 516 #if defined(_SIMULATOR_SUPPORT) 517 if (halt_idle_cpus && !simulator_run) 518 idle_cpu = cpu_halt; 519 #else 520 if (halt_idle_cpus) 521 idle_cpu = cpu_halt; 522 #endif /* _SIMULATOR_SUPPORT */ 523 524 mach_smpinit(); 525 } 526 527 static void 528 mach_smpinit(void) 529 { 530 register struct psm_ops *pops; 531 register processorid_t cpu_id; 532 int cnt; 533 int cpumask; 534 535 pops = mach_set[0]; 536 537 cpu_id = -1; 538 cpu_id = (*pops->psm_get_next_processorid)(cpu_id); 539 for (cnt = 0, cpumask = 0; cpu_id != -1; cnt++) { 540 cpumask |= 1 << cpu_id; 541 cpu_id = (*pops->psm_get_next_processorid)(cpu_id); 542 } 543 544 mp_cpus = cpumask; 545 546 /* MP related routines */ 547 cpu_startf = mach_cpu_start; 548 ap_mlsetup = pops->psm_post_cpu_start; 549 send_dirintf = pops->psm_send_ipi; 550 551 /* optional MP related routines */ 552 if (pops->psm_shutdown) 553 psm_shutdownf = pops->psm_shutdown; 554 if (pops->psm_preshutdown) 555 psm_preshutdownf = pops->psm_preshutdown; 556 if (pops->psm_notify_func) 557 psm_notifyf = pops->psm_notify_func; 558 if (pops->psm_set_idlecpu) 559 psm_set_idle_cpuf = pops->psm_set_idlecpu; 560 if (pops->psm_unset_idlecpu) 561 psm_unset_idle_cpuf = pops->psm_unset_idlecpu; 562 563 psm_clkinit = pops->psm_clkinit; 564 565 if (pops->psm_timer_reprogram) 566 psm_timer_reprogram = pops->psm_timer_reprogram; 567 568 if (pops->psm_timer_enable) 569 psm_timer_enable = pops->psm_timer_enable; 570 571 if (pops->psm_timer_disable) 572 psm_timer_disable = pops->psm_timer_disable; 573 574 if (pops->psm_post_cyclic_setup) 575 psm_post_cyclic_setup = pops->psm_post_cyclic_setup; 576 577 /* check for multiple cpu's */ 578 if (cnt < 2) 579 return; 580 581 /* check for MP platforms */ 582 if (pops->psm_cpu_start == NULL) 583 return; 584 585 /* 586 * Set the dispatcher hook to enable cpu "wake up" 587 * when a thread becomes runnable. 588 */ 589 #if defined(_SIMULATOR_SUPPORT) 590 if (halt_idle_cpus && !simulator_run) { 591 disp_enq_thread = cpu_wakeup; 592 } 593 #else 594 if (halt_idle_cpus) { 595 disp_enq_thread = cpu_wakeup; 596 } 597 #endif /* _SIMULATOR_SUPPORT */ 598 599 if (pops->psm_disable_intr) 600 psm_disable_intr = pops->psm_disable_intr; 601 if (pops->psm_enable_intr) 602 psm_enable_intr = pops->psm_enable_intr; 603 604 psm_get_ipivect = pops->psm_get_ipivect; 605 606 (void) add_avintr((void *)NULL, XC_HI_PIL, xc_serv, "xc_hi_intr", 607 (*pops->psm_get_ipivect)(XC_HI_PIL, PSM_INTR_IPI_HI), 608 (caddr_t)X_CALL_HIPRI, NULL, NULL); 609 (void) add_avintr((void *)NULL, XC_MED_PIL, xc_serv, "xc_med_intr", 610 (*pops->psm_get_ipivect)(XC_MED_PIL, PSM_INTR_IPI_LO), 611 (caddr_t)X_CALL_MEDPRI, NULL, NULL); 612 613 (void) (*pops->psm_get_ipivect)(XC_CPUPOKE_PIL, PSM_INTR_POKE); 614 } 615 616 static void 617 mach_picinit() 618 { 619 register struct psm_ops *pops; 620 extern void install_spl(void); /* XXX: belongs in a header file */ 621 #if defined(__amd64) && defined(DEBUG) 622 extern void *spl_patch, *slow_spl, *setsplhi_patch, *slow_setsplhi; 623 #endif 624 625 pops = mach_set[0]; 626 627 /* register the interrupt handlers */ 628 setlvl = pops->psm_intr_enter; 629 setlvlx = pops->psm_intr_exit; 630 631 /* initialize the interrupt hardware */ 632 (*pops->psm_picinit)(); 633 634 /* set interrupt mask for current ipl */ 635 setspl = pops->psm_setspl; 636 setspl(CPU->cpu_pri); 637 638 /* Install proper spl routine now that we can Program the PIC */ 639 #if defined(__amd64) 640 /* 641 * It would be better if we could check this at compile time 642 */ 643 ASSERT(((uintptr_t)&slow_setsplhi - (uintptr_t)&setsplhi_patch < 128) && 644 ((uintptr_t)&slow_spl - (uintptr_t)&spl_patch < 128)); 645 #endif 646 install_spl(); 647 } 648 649 uint_t cpu_freq; /* MHz */ 650 uint64_t cpu_freq_hz; /* measured (in hertz) */ 651 652 #define MEGA_HZ 1000000 653 654 static uint64_t 655 mach_calchz(uint32_t pit_counter, uint64_t *processor_clks) 656 { 657 uint64_t cpu_hz; 658 659 if ((pit_counter == 0) || (*processor_clks == 0) || 660 (*processor_clks > (((uint64_t)-1) / PIT_HZ))) 661 return (0); 662 663 cpu_hz = ((uint64_t)PIT_HZ * *processor_clks) / pit_counter; 664 665 return (cpu_hz); 666 } 667 668 static uint64_t 669 mach_getcpufreq(void) 670 { 671 uint32_t pit_counter; 672 uint64_t processor_clks; 673 674 if (x86_feature & X86_TSC) { 675 /* 676 * We have a TSC. freq_tsc() knows how to measure the number 677 * of clock cycles sampled against the PIT. 678 */ 679 processor_clks = freq_tsc(&pit_counter); 680 return (mach_calchz(pit_counter, &processor_clks)); 681 } else if (x86_vendor == X86_VENDOR_Cyrix || x86_type == X86_TYPE_P5) { 682 #if defined(__amd64) 683 panic("mach_getcpufreq: no TSC!"); 684 #elif defined(__i386) 685 /* 686 * We are a Cyrix based on a 6x86 core or an Intel Pentium 687 * for which freq_notsc() knows how to measure the number of 688 * elapsed clock cycles sampled against the PIT 689 */ 690 processor_clks = freq_notsc(&pit_counter); 691 return (mach_calchz(pit_counter, &processor_clks)); 692 #endif /* __i386 */ 693 } 694 695 /* We do not know how to calculate cpu frequency for this cpu. */ 696 return (0); 697 } 698 699 /* 700 * If the clock speed of a cpu is found to be reported incorrectly, do not add 701 * to this array, instead improve the accuracy of the algorithm that determines 702 * the clock speed of the processor or extend the implementation to support the 703 * vendor as appropriate. This is here only to support adjusting the speed on 704 * older slower processors that mach_fixcpufreq() would not be able to account 705 * for otherwise. 706 */ 707 static int x86_cpu_freq[] = { 60, 75, 80, 90, 120, 160, 166, 175, 180, 233 }; 708 709 /* 710 * On fast processors the clock frequency that is measured may be off by 711 * a few MHz from the value printed on the part. This is a combination of 712 * the factors that for such fast parts being off by this much is within 713 * the tolerances for manufacture and because of the difficulties in the 714 * measurement that can lead to small error. This function uses some 715 * heuristics in order to tweak the value that was measured to match what 716 * is most likely printed on the part. 717 * 718 * Some examples: 719 * AMD Athlon 1000 mhz measured as 998 mhz 720 * Intel Pentium III Xeon 733 mhz measured as 731 mhz 721 * Intel Pentium IV 1500 mhz measured as 1495mhz 722 * 723 * If in the future this function is no longer sufficient to correct 724 * for the error in the measurement, then the algorithm used to perform 725 * the measurement will have to be improved in order to increase accuracy 726 * rather than adding horrible and questionable kludges here. 727 * 728 * This is called after the cyclics subsystem because of the potential 729 * that the heuristics within may give a worse estimate of the clock 730 * frequency than the value that was measured. 731 */ 732 static void 733 mach_fixcpufreq(void) 734 { 735 uint32_t freq, mul, near66, delta66, near50, delta50, fixed, delta, i; 736 737 freq = (uint32_t)cpu_freq; 738 739 /* 740 * Find the nearest integer multiple of 200/3 (about 66) MHz to the 741 * measured speed taking into account that the 667 MHz parts were 742 * the first to round-up. 743 */ 744 mul = (uint32_t)((3 * (uint64_t)freq + 100) / 200); 745 near66 = (uint32_t)((200 * (uint64_t)mul + ((mul >= 10) ? 1 : 0)) / 3); 746 delta66 = (near66 > freq) ? (near66 - freq) : (freq - near66); 747 748 /* Find the nearest integer multiple of 50 MHz to the measured speed */ 749 mul = (freq + 25) / 50; 750 near50 = mul * 50; 751 delta50 = (near50 > freq) ? (near50 - freq) : (freq - near50); 752 753 /* Find the closer of the two */ 754 if (delta66 < delta50) { 755 fixed = near66; 756 delta = delta66; 757 } else { 758 fixed = near50; 759 delta = delta50; 760 } 761 762 if (fixed > INT_MAX) 763 return; 764 765 /* 766 * Some older parts have a core clock frequency that is not an 767 * integral multiple of 50 or 66 MHz. Check if one of the old 768 * clock frequencies is closer to the measured value than any 769 * of the integral multiples of 50 an 66, and if so set fixed 770 * and delta appropriately to represent the closest value. 771 */ 772 i = sizeof (x86_cpu_freq) / sizeof (int); 773 while (i > 0) { 774 i--; 775 776 if (x86_cpu_freq[i] <= freq) { 777 mul = freq - x86_cpu_freq[i]; 778 779 if (mul < delta) { 780 fixed = x86_cpu_freq[i]; 781 delta = mul; 782 } 783 784 break; 785 } 786 787 mul = x86_cpu_freq[i] - freq; 788 789 if (mul < delta) { 790 fixed = x86_cpu_freq[i]; 791 delta = mul; 792 } 793 } 794 795 /* 796 * Set a reasonable maximum for how much to correct the measured 797 * result by. This check is here to prevent the adjustment made 798 * by this function from being more harm than good. It is entirely 799 * possible that in the future parts will be made that are not 800 * integral multiples of 66 or 50 in clock frequency or that 801 * someone may overclock a part to some odd frequency. If the 802 * measured value is farther from the corrected value than 803 * allowed, then assume the corrected value is in error and use 804 * the measured value. 805 */ 806 if (6 < delta) 807 return; 808 809 cpu_freq = (int)fixed; 810 } 811 812 813 static int 814 machhztomhz(uint64_t cpu_freq_hz) 815 { 816 uint64_t cpu_mhz; 817 818 /* Round to nearest MHZ */ 819 cpu_mhz = (cpu_freq_hz + (MEGA_HZ / 2)) / MEGA_HZ; 820 821 if (cpu_mhz > INT_MAX) 822 return (0); 823 824 return ((int)cpu_mhz); 825 826 } 827 828 829 static int 830 mach_clkinit(int preferred_mode, int *set_mode) 831 { 832 register struct psm_ops *pops; 833 int resolution; 834 835 pops = mach_set[0]; 836 837 #ifdef _SIMULATOR_SUPPORT 838 if (!simulator_run) 839 cpu_freq_hz = mach_getcpufreq(); 840 else 841 cpu_freq_hz = 40000000; /* use 40 Mhz (hack for simulator) */ 842 #else 843 cpu_freq_hz = mach_getcpufreq(); 844 #endif /* _SIMULATOR_SUPPORT */ 845 846 cpu_freq = machhztomhz(cpu_freq_hz); 847 848 if (!(x86_feature & X86_TSC) || (cpu_freq == 0)) 849 tsc_gethrtime_enable = 0; 850 851 if (tsc_gethrtime_enable) { 852 tsc_hrtimeinit(cpu_freq_hz); 853 gethrtimef = tsc_gethrtime; 854 gethrtimeunscaledf = tsc_gethrtimeunscaled; 855 scalehrtimef = tsc_scalehrtime; 856 hrtime_tick = tsc_tick; 857 tsc_gethrtime_initted = 1; 858 } else { 859 if (pops->psm_hrtimeinit) 860 (*pops->psm_hrtimeinit)(); 861 gethrtimef = pops->psm_gethrtime; 862 gethrtimeunscaledf = gethrtimef; 863 /* scalehrtimef will remain dummy */ 864 } 865 866 mach_fixcpufreq(); 867 868 if (mach_ver[0] >= PSM_INFO_VER01_3) { 869 if ((preferred_mode == TIMER_ONESHOT) && 870 (tsc_gethrtime_enable)) { 871 872 resolution = (*pops->psm_clkinit)(0); 873 if (resolution != 0) { 874 *set_mode = TIMER_ONESHOT; 875 return (resolution); 876 } 877 878 } 879 880 /* 881 * either periodic mode was requested or could not set to 882 * one-shot mode 883 */ 884 resolution = (*pops->psm_clkinit)(hz); 885 /* 886 * psm should be able to do periodic, so we do not check 887 * for return value of psm_clkinit here. 888 */ 889 *set_mode = TIMER_PERIODIC; 890 return (resolution); 891 } else { 892 /* 893 * PSMI interface prior to PSMI_3 does not define a return 894 * value for psm_clkinit, so the return value is ignored. 895 */ 896 (void) (*pops->psm_clkinit)(hz); 897 *set_mode = TIMER_PERIODIC; 898 return (nsec_per_tick); 899 } 900 } 901 902 static int 903 mach_softlvl_to_vect(register int ipl) 904 { 905 register int softvect; 906 register struct psm_ops *pops; 907 908 pops = mach_set[0]; 909 910 /* check for null handler for set soft interrupt call */ 911 if (pops->psm_set_softintr == NULL) { 912 setsoftint = set_pending; 913 return (PSM_SV_SOFTWARE); 914 } 915 916 softvect = (*pops->psm_softlvl_to_irq)(ipl); 917 /* check for hardware scheme */ 918 if (softvect > PSM_SV_SOFTWARE) { 919 setsoftint = pops->psm_set_softintr; 920 return (softvect); 921 } 922 923 if (softvect == PSM_SV_SOFTWARE) 924 setsoftint = set_pending; 925 else /* hardware and software mixed scheme */ 926 setsoftint = mach_set_softintr; 927 928 return (PSM_SV_SOFTWARE); 929 } 930 931 static void 932 mach_set_softintr(register int ipl) 933 { 934 register struct psm_ops *pops; 935 936 /* set software pending bits */ 937 set_pending(ipl); 938 939 /* check if dosoftint will be called at the end of intr */ 940 if (CPU_ON_INTR(CPU) || (curthread->t_intr)) 941 return; 942 943 /* invoke hardware interrupt */ 944 pops = mach_set[0]; 945 (*pops->psm_set_softintr)(ipl); 946 } 947 948 static void 949 mach_cpu_start(register int cpun) 950 { 951 register struct psm_ops *pops; 952 int i; 953 954 pops = mach_set[0]; 955 956 (*pops->psm_cpu_start)(cpun, rm_platter_va); 957 958 /* wait for the auxillary cpu to be ready */ 959 for (i = 20000; i; i--) { 960 if (cpu[cpun]->cpu_flags & CPU_READY) 961 return; 962 drv_usecwait(100); 963 } 964 } 965 966 /*ARGSUSED*/ 967 static int 968 mach_translate_irq(dev_info_t *dip, int irqno) 969 { 970 return (irqno); /* default to NO translation */ 971 } 972 973 static timestruc_t 974 mach_tod_get(void) 975 { 976 timestruc_t ts; 977 todinfo_t tod; 978 static int mach_range_warn = 1; /* warn only once */ 979 980 ASSERT(MUTEX_HELD(&tod_lock)); 981 982 /* The year returned from is the last 2 digit only */ 983 if ((*psm_todgetf)(&tod)) { 984 ts.tv_sec = 0; 985 ts.tv_nsec = 0; 986 tod_fault_reset(); 987 return (ts); 988 } 989 990 /* assume that we wrap the rtc year back to zero at 2000 */ 991 if (tod.tod_year < 69) { 992 if (mach_range_warn && tod.tod_year > 38) { 993 cmn_err(CE_WARN, "hardware real-time clock is out " 994 "of range -- time needs to be reset"); 995 mach_range_warn = 0; 996 } 997 tod.tod_year += 100; 998 } 999 1000 /* tod_to_utc uses 1900 as base for the year */ 1001 ts.tv_sec = tod_to_utc(tod) + gmt_lag; 1002 ts.tv_nsec = 0; 1003 1004 return (ts); 1005 } 1006 1007 static void 1008 mach_tod_set(timestruc_t ts) 1009 { 1010 todinfo_t tod = utc_to_tod(ts.tv_sec - gmt_lag); 1011 1012 ASSERT(MUTEX_HELD(&tod_lock)); 1013 1014 if (tod.tod_year >= 100) 1015 tod.tod_year -= 100; 1016 1017 (*psm_todsetf)(&tod); 1018 } 1019 1020 static void 1021 mach_notify_error(int level, char *errmsg) 1022 { 1023 /* 1024 * SL_FATAL is pass in once panicstr is set, deliver it 1025 * as CE_PANIC. Also, translate SL_ codes back to CE_ 1026 * codes for the psmi handler 1027 */ 1028 if (level & SL_FATAL) 1029 (*notify_error)(CE_PANIC, errmsg); 1030 else if (level & SL_WARN) 1031 (*notify_error)(CE_WARN, errmsg); 1032 else if (level & SL_NOTE) 1033 (*notify_error)(CE_NOTE, errmsg); 1034 else if (level & SL_CONSOLE) 1035 (*notify_error)(CE_CONT, errmsg); 1036 } 1037 1038 /* 1039 * It provides the default basic intr_ops interface for the new DDI 1040 * interrupt framework if the PSM doesn't have one. 1041 * 1042 * Input: 1043 * dip - pointer to the dev_info structure of the requested device 1044 * hdlp - pointer to the internal interrupt handle structure for the 1045 * requested interrupt 1046 * intr_op - opcode for this call 1047 * result - pointer to the integer that will hold the result to be 1048 * passed back if return value is PSM_SUCCESS 1049 * 1050 * Output: 1051 * return value is either PSM_SUCCESS or PSM_FAILURE 1052 */ 1053 static int 1054 mach_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 1055 psm_intr_op_t intr_op, int *result) 1056 { 1057 struct intrspec *ispec; 1058 1059 switch (intr_op) { 1060 case PSM_INTR_OP_CHECK_MSI: 1061 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI | 1062 DDI_INTR_TYPE_MSIX); 1063 break; 1064 case PSM_INTR_OP_ALLOC_VECTORS: 1065 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 1066 *result = 1; 1067 else 1068 *result = 0; 1069 break; 1070 case PSM_INTR_OP_FREE_VECTORS: 1071 break; 1072 case PSM_INTR_OP_NAVAIL_VECTORS: 1073 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 1074 *result = 1; 1075 else 1076 *result = 0; 1077 break; 1078 case PSM_INTR_OP_XLATE_VECTOR: 1079 ispec = (struct intrspec *)hdlp->ih_private; 1080 *result = psm_translate_irq(dip, ispec->intrspec_vec); 1081 break; 1082 case PSM_INTR_OP_GET_CAP: 1083 *result = 0; 1084 break; 1085 case PSM_INTR_OP_GET_PENDING: 1086 case PSM_INTR_OP_CLEAR_MASK: 1087 case PSM_INTR_OP_SET_MASK: 1088 case PSM_INTR_OP_GET_SHARED: 1089 case PSM_INTR_OP_SET_PRI: 1090 case PSM_INTR_OP_SET_CAP: 1091 default: 1092 return (PSM_FAILURE); 1093 } 1094 return (PSM_SUCCESS); 1095 } 1096