xref: /illumos-gate/usr/src/uts/common/sys/vgareg.h (revision 9b40c3052b9b0d91120c568df0c5211c131c8da1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_VGAREG_H
28 #define	_SYS_VGAREG_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #define	VGA_REG_ADDR	0x3c0
35 #define	VGA_REG_SIZE	0x20
36 
37 #define	VGA_MEM_ADDR	0xa0000
38 #define	VGA_MEM_SIZE	0x20000
39 
40 /*
41  * VGA frame buffer hardware definitions.
42  */
43 
44 #define	VGA8_DEPTH		8
45 #define	VGA8_CMAP_ENTRIES	256
46 #define	VGA_TEXT_CMAP_ENTRIES	64
47 
48 /*
49  * General VGA registers
50  * These are relative to their register set, which
51  * the 3c0-3df set.
52  */
53 #define	VGA_ATR_AD	0x00
54 #define	VGA_ATR_DATA	0x01
55 #define	VGA_MISC_W	0x02
56 #define	VGA_SEQ_ADR	0x04
57 #define	VGA_SEQ_DATA	0x05
58 #define	VGA_DAC_BASE	0x06
59 #define	VGA_DAC_AD_MK	0x06
60 #define	VGA_DAC_RD_AD	0x07
61 #define	VGA_DAC_STS	0x07
62 #define	VGA_DAC_WR_AD	0x08
63 #define	VGA_DAC_DATA	0x09
64 #define	VGA_MISC_R	0x0c
65 #define	VGA_GRC_ADR	0x0e
66 #define	VGA_GRC_DATA	0x0f
67 #define	VGA_CRTC_ADR	0x14
68 #define	VGA_CRTC_DATA	0x15
69 #define	CGA_STAT	0x1a
70 
71 /*
72  * Attribute controller index bits
73  */
74 #define	VGA_ATR_ENB_PLT	0x20
75 
76 /*
77  * Miscellaneous output bits
78  */
79 #define	VGA_MISC_IOA_SEL	0x01
80 #define	VGA_MISC_ENB_RAM	0x02
81 #define	VGA_MISC_VCLK		0x0c
82 #define		VGA_MISC_VCLK0		0x00
83 #define		VGA_MISC_VCLK1		0x04
84 #define		VGA_MISC_VCLK2		0x08
85 #define		VGA_MISC_VCLK3		0x0c
86 #define	VGA_MISC_PGSL		0x20
87 #define	VGA_MISC_HSP		0x40
88 #define	VGA_MISC_VSP		0x80
89 
90 /*
91  * CRT Controller registers
92  */
93 #define	VGA_CRTC_H_TOTAL	0x00
94 #define	VGA_CRTC_H_D_END	0x01
95 #define	VGA_CRTC_S_H_BLNK	0x02
96 #define	VGA_CRTC_E_H_BLNK	0x03
97 #define		VGA_CRTC_E_H_BLNK_PUT_EHB(n) \
98 			((n)&0x1f)
99 #define	VGA_CRTC_S_H_SY_P	0x04
100 #define	VGA_CRTC_E_H_SY_P	0x05
101 #define		VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT	5
102 #define		VGA_CRTC_E_H_SY_P_HOR_SKW	0x60
103 #define		VGA_CRTC_E_H_SY_P_EHB5		7
104 #define		VGA_CRTC_E_H_SY_P_PUT_HOR_SKW(skew) \
105 			((skew)<<VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT)
106 #define		VGA_CRTC_E_H_SY_P_PUT_EHB(n) \
107 			((((n)>>5)&1)<<VGA_CRTC_E_H_SY_P_EHB5)
108 #define		VGA_CRTC_E_H_SY_P_PUT_EHS(n) \
109 			((n)&0x1f)
110 #define	VGA_CRTC_V_TOTAL	0x06
111 #define	VGA_CRTC_OVFL_REG	0x07
112 #define		VGA_CRTC_OVFL_REG_VT8	0
113 #define		VGA_CRTC_OVFL_REG_VDE8	1
114 #define		VGA_CRTC_OVFL_REG_VRS8	2
115 #define		VGA_CRTC_OVFL_REG_SVB8	3
116 #define		VGA_CRTC_OVFL_REG_LCM8	4
117 #define		VGA_CRTC_OVFL_REG_VT9	5
118 #define		VGA_CRTC_OVFL_REG_VDE9	6
119 #define		VGA_CRTC_OVFL_REG_VRS9	7
120 #define		VGA_CRTC_OVFL_REG_PUT_VT(n)	\
121 			((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VT8) \
122 			| ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VT9)
123 #define		VGA_CRTC_OVFL_REG_PUT_VDE(n)	\
124 			((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VDE8) \
125 			| ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VDE9)
126 #define		VGA_CRTC_OVFL_REG_PUT_VRS(n)	\
127 			((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VRS8) \
128 			| ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VRS9)
129 #define		VGA_CRTC_OVFL_REG_PUT_LCM(n)	\
130 			((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_LCM8)
131 #define		VGA_CRTC_OVFL_REG_PUT_SVB(n)	\
132 			((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_SVB8)
133 #define	VGA_CRTC_P_R_SCAN	0x08
134 #define	VGA_CRTC_MAX_S_LN	0x09
135 #define		VGA_CRTC_MAX_S_LN_SVB9	5
136 #define		VGA_CRTC_MAX_S_LN_LCM9	6
137 #define		VGA_CRTC_MAX_S_LN_PUT_SVB(n)	\
138 			((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_SVB9)
139 #define		VGA_CRTC_MAX_S_LN_PUT_LCM(n)	\
140 			((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_LCM9)
141 #define	VGA_CRTC_CSSL		0x0a
142 #define	VGA_CRTC_CESL		0x0b
143 #define	VGA_CRTC_STAH		0x0c
144 #define	VGA_CRTC_STAL		0x0d
145 #define	VGA_CRTC_CLAH		0x0e
146 #define	VGA_CRTC_CLAL		0x0f
147 #define	VGA_CRTC_VRS		0x10
148 #define	VGA_CRTC_VRE		0x11
149 #define		VGA_CRTC_VRE_LOCK	0x80
150 #define		VGA_CRTC_VRE_DIS_VINT	0x20
151 #define		VGA_CRTC_VRE_PUT_VRE(n) \
152 			((n)&0x0f)
153 #define	VGA_CRTC_VDE		0x12
154 #define	VGA_CRTC_SCREEN_OFFSET	0x13
155 #define	VGA_CRTC_ULL		0x14
156 #define	VGA_CRTC_SVB		0x15
157 #define	VGA_CRTC_EVB		0x16
158 #define	VGA_CRTC_CRT_MD		0x17
159 #define		VGA_CRTC_CRT_MD_2BK_CGA		0x01
160 #define		VGA_CRTC_CRT_MD_4BK_HGC		0x02
161 #define		VGA_CRTC_CRT_MD_VT_X2		0x04
162 #define		VGA_CRTC_CRT_MD_WRD_MODE	0x08
163 #define		VGA_CRTC_CRT_MD_ADW_16K		0x20
164 #define		VGA_CRTC_CRT_MD_BYTE_MODE	0x40
165 #define		VGA_CRTC_CRT_MD_NO_RESET	0x80
166 #define	VGA_CRTC_LCM		0x18
167 
168 /*
169  * Sequencer registers
170  */
171 #define	VGA_SEQ_RST_SYN		0x00
172 #define		VGA_SEQ_RST_SYN_ASYNC_RESET	0x00
173 #define		VGA_SEQ_RST_SYN_NO_ASYNC_RESET	0x01
174 #define		VGA_SEQ_RST_SYN_SYNC_RESET	0x00
175 #define		VGA_SEQ_RST_SYN_NO_SYNC_RESET	0x02
176 #define	VGA_SEQ_CLK_MODE	0x01
177 #define		VGA_SEQ_CLK_MODE_8DC		0x01
178 #define	VGA_SEQ_EN_WT_PL	0x02
179 #define		VGA_SEQ_EN_WT_PL_ALL		0x0f
180 #define	VGA_SEQ_MEM_MODE	0x04
181 #define		VGA_SEQ_MEM_MODE_EXT_MEM	0x02
182 #define		VGA_SEQ_MEM_MODE_SEQ_MODE	0x04
183 #define		VGA_SEQ_MEM_MODE_CHN_4M		0x08
184 
185 /*
186  * Graphics Controller
187  */
188 #define	VGA_GRC_SET_RST_DT	0x00
189 #define	VGA_GRC_EN_S_R_DT	0x01
190 #define	VGA_GRC_COLOR_CMP	0x02
191 #define	VGA_GRC_WT_ROP_RTC	0x03
192 #define	VGA_GRC_RD_PL_SL	0x04
193 #define	VGA_GRC_GRP_MODE	0x05
194 #define		VGA_GRC_GRP_MODE_SHF_MODE_256	0x40
195 #define	VGA_GRC_MISC_GM		0x06
196 #define		VGA_GRC_MISC_GM_GRAPH		0x01
197 #define		VGA_GRC_MISC_GM_MEM_MAP_1	0x04
198 #define	VGA_GRC_CMP_DNTC	0x07
199 #define		VGA_GRC_CMP_DNTC_ALL		0x0f
200 #define	VGA_GRC_BIT_MASK	0x08
201 
202 /*
203  * Attribute controller registers
204  */
205 #define	VGA_ATR_PLT_REG		0x00
206 #define	VGA_ATR_NUM_PLT		0x10
207 #define	VGA_ATR_MODE		0x10
208 #define		VGA_ATR_MODE_GRAPH	0x01
209 #define		VGA_ATR_MODE_9WIDE	0x04
210 #define		VGA_ATR_MODE_BLINK	0x08
211 #define		VGA_ATR_MODE_256CLR	0x40
212 #define	VGA_ATR_BDR_CLR		0x11
213 #define	VGA_ATR_DISP_PLN	0x12
214 #define		VGA_ATR_DISP_PLN_ALL	0x0f
215 #define	VGA_ATR_H_PX_PAN	0x13
216 #define	VGA_ATR_PX_PADD		0x14
217 
218 /*
219  * Low-memory frame buffer definitions.  These are relative to the
220  * A0000 register set.
221  */
222 #define	VGA_MONO_BASE		0x10000	/* Base of monochrome text */
223 #define	VGA_COLOR_BASE		0x18000	/* Base of color text */
224 #define	VGA_TEXT_SIZE		0x8000	/* Size of text frame buffer */
225 
226 #ifdef	__cplusplus
227 }
228 #endif
229 
230 #endif /* _SYS_VGAREG_H */
231