1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * This file is the principle header file for the PMCS driver 27 */ 28 #ifndef _PMCS_H 29 #define _PMCS_H 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 #include <sys/cpuvar.h> 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/modctl.h> 39 #include <sys/pci.h> 40 #include <sys/pcie.h> 41 #include <sys/isa_defs.h> 42 #include <sys/sunmdi.h> 43 #include <sys/mdi_impldefs.h> 44 #include <sys/scsi/scsi.h> 45 #include <sys/scsi/impl/scsi_reset_notify.h> 46 #include <sys/scsi/impl/sas_transport.h> 47 #include <sys/scsi/generic/sas.h> 48 #include <sys/atomic.h> 49 #include <sys/byteorder.h> 50 #include <sys/bitmap.h> 51 #include <sys/queue.h> 52 #include <sys/sdt.h> 53 #include <sys/ddifm.h> 54 #include <sys/fm/protocol.h> 55 #include <sys/fm/util.h> 56 #include <sys/fm/io/ddi.h> 57 #include <sys/scsi/impl/spc3_types.h> 58 59 typedef struct pmcs_hw pmcs_hw_t; 60 typedef struct pmcs_iport pmcs_iport_t; 61 typedef struct pmcs_phy pmcs_phy_t; 62 typedef struct lsas_cmd lsas_cmd_t; 63 typedef struct lsas_result lsas_result_t; 64 typedef struct lsata_cmd lsata_cmd_t; 65 typedef struct lsata_result lsata_result_t; 66 typedef struct pmcwork pmcwork_t; 67 typedef struct pmcs_cmd pmcs_cmd_t; 68 typedef struct pmcs_xscsi pmcs_xscsi_t; 69 typedef struct pmcs_lun pmcs_lun_t; 70 typedef struct pmcs_chunk pmcs_chunk_t; 71 72 #include <sys/scsi/adapters/pmcs/pmcs_param.h> 73 #include <sys/scsi/adapters/pmcs/pmcs_reg.h> 74 #include <sys/scsi/adapters/pmcs/pmcs_mpi.h> 75 #include <sys/scsi/adapters/pmcs/pmcs_iomb.h> 76 #include <sys/scsi/adapters/pmcs/pmcs_sgl.h> 77 78 #include <sys/scsi/adapters/pmcs/smp_defs.h> 79 #include <sys/scsi/adapters/pmcs/ata.h> 80 #include <sys/scsi/adapters/pmcs/pmcs_def.h> 81 #include <sys/scsi/adapters/pmcs/pmcs_proto.h> 82 #include <sys/scsi/adapters/pmcs/pmcs_scsa.h> 83 #include <sys/scsi/adapters/pmcs/pmcs_smhba.h> 84 85 #define PMCS_MAX_UA_SIZE 32 86 87 struct pmcs_xscsi { 88 uint32_t 89 ca : 1, /* SATA specific */ 90 ncq : 1, /* SATA specific */ 91 pio : 1, /* SATA specific */ 92 special_needed : 1, /* SATA specific */ 93 special_running : 1, /* SATA specific */ 94 reset_success : 1, /* last reset ok */ 95 reset_wait : 1, /* wait for reset */ 96 resetting : 1, /* now resetting */ 97 recover_wait : 1, /* wait for recovery */ 98 recovering : 1, /* now recovering */ 99 event_recovery : 1, /* event recovery */ 100 draining : 1, 101 new : 1, 102 assigned : 1, 103 dev_gone : 1, 104 phy_addressable : 1, /* Direct attach SATA */ 105 dev_state : 4; 106 uint16_t maxdepth; 107 uint16_t qdepth; 108 uint16_t actv_cnt; 109 uint16_t target_num; 110 /* statlock protects both target stats and the special queue (sq) */ 111 kmutex_t statlock; 112 int32_t ref_count; 113 dev_info_t *dip; /* Solaris device dip */ 114 pmcs_phy_t *phy; 115 STAILQ_HEAD(wqh, pmcs_cmd) wq; 116 pmcs_cmd_t *wq_recovery_tail; /* See below */ 117 kmutex_t wqlock; 118 STAILQ_HEAD(aqh, pmcs_cmd) aq; 119 kmutex_t aqlock; 120 STAILQ_HEAD(sqh, pmcs_cmd) sq; /* SATA specific */ 121 uint32_t tagmap; /* SATA specific */ 122 pmcs_hw_t *pwp; 123 ddi_soft_state_bystr *lun_sstate; 124 uint64_t capacity; /* SATA specific */ 125 char unit_address[PMCS_MAX_UA_SIZE]; 126 kcondvar_t reset_cv; 127 kcondvar_t abort_cv; 128 char *ua; 129 pmcs_dtype_t dtype; 130 }; 131 132 /* 133 * wq_recovery_tail in the pmcs_xscsi structure is a pointer to a command in 134 * the wait queue (wq). That pointer is the last command in the wait queue 135 * that needs to be reissued after device state recovery is complete. Commands 136 * that need to be retried are reinserted into the wq after wq_recovery_tail 137 * to maintain the order in which the commands were originally submitted. 138 */ 139 140 #define PMCS_INVALID_TARGET_NUM (uint16_t)-1 141 142 #define PMCS_TGT_WAIT_QUEUE 0x01 143 #define PMCS_TGT_ACTIVE_QUEUE 0x02 144 #define PMCS_TGT_SPECIAL_QUEUE 0x04 145 #define PMCS_TGT_ALL_QUEUES 0xff 146 147 /* 148 * LUN representation. Just a LUN (number) and pointer to the target 149 * structure (pmcs_xscsi). 150 */ 151 152 struct pmcs_lun { 153 pmcs_xscsi_t *target; 154 uint64_t lun_num; /* lun64 */ 155 scsi_lun_t scsi_lun; /* Wire format */ 156 char unit_address[PMCS_MAX_UA_SIZE]; 157 }; 158 159 /* 160 * Interrupt coalescing values 161 */ 162 #define PMCS_MAX_IO_COMPS_PER_INTR 12 163 #define PMCS_MAX_IO_COMPS_HIWAT_SHIFT 6 164 #define PMCS_MAX_IO_COMPS_LOWAT_SHIFT 10 165 #define PMCS_QUANTUM_TIME_USECS (1000000 / 10) /* 1/10th sec. */ 166 #define PMCS_MAX_COAL_TIMER 0x200 /* Don't set > than this */ 167 #define PMCS_MAX_CQ_THREADS 4 168 #define PMCS_COAL_TIMER_GRAN 2 /* Go up/down by 2 usecs */ 169 #define PMCS_INTR_THRESHOLD(x) ((x) * 6 / 10) 170 171 /* 172 * This structure is used to maintain state with regard to I/O interrupt 173 * coalescing. 174 */ 175 176 typedef struct pmcs_io_intr_coal_s { 177 hrtime_t nsecs_between_intrs; 178 hrtime_t last_io_comp; 179 clock_t quantum; 180 uint32_t num_io_completions; 181 uint32_t num_intrs; 182 uint32_t max_io_completions; 183 uint32_t intr_latency; 184 uint32_t intr_threshold; 185 uint16_t intr_coal_timer; 186 boolean_t timer_on; 187 boolean_t stop_thread; 188 boolean_t int_cleared; 189 } pmcs_io_intr_coal_t; 190 191 typedef struct pmcs_cq_thr_info_s { 192 kthread_t *cq_thread; 193 kmutex_t cq_thr_lock; 194 kcondvar_t cq_cv; 195 pmcs_hw_t *cq_pwp; 196 } pmcs_cq_thr_info_t; 197 198 typedef struct pmcs_cq_info_s { 199 uint32_t cq_threads; 200 uint32_t cq_next_disp_thr; 201 boolean_t cq_stop; 202 pmcs_cq_thr_info_t *cq_thr_info; 203 } pmcs_cq_info_t; 204 205 typedef struct pmcs_iocomp_cb_s { 206 pmcwork_t *pwrk; 207 char iomb[PMCS_QENTRY_SIZE << 1]; 208 struct pmcs_iocomp_cb_s *next; 209 } pmcs_iocomp_cb_t; 210 211 typedef struct pmcs_iqp_trace_s { 212 char *head; 213 char *curpos; 214 uint32_t size_left; 215 } pmcs_iqp_trace_t; 216 217 /* 218 * Used by string-based softstate as hint to possible size. 219 */ 220 221 #define PMCS_TGT_SSTATE_SZ 64 222 #define PMCS_LUN_SSTATE_SZ 4 223 224 /* 225 * HBA iport node softstate 226 */ 227 #define PMCS_IPORT_INVALID_PORT_ID 0xffff 228 229 struct pmcs_iport { 230 kmutex_t lock; /* iport lock */ 231 list_node_t list_node; /* list node for pwp->iports list_t */ 232 kmutex_t refcnt_lock; /* refcnt lock */ 233 kcondvar_t refcnt_cv; /* refcnt cv */ 234 int refcnt; /* refcnt for this iport */ 235 dev_info_t *dip; /* iport dip */ 236 pmcs_hw_t *pwp; /* back pointer to HBA state */ 237 pmcs_phy_t *pptr; /* pointer to this port's primary phy */ 238 enum { /* unit address state in the phymap */ 239 UA_INACTIVE, 240 UA_PEND_ACTIVATE, 241 UA_ACTIVE, 242 UA_PEND_DEACTIVATE 243 } ua_state; 244 char *ua; /* unit address (phy mask) */ 245 int portid; /* portid */ 246 int report_skip; /* skip or report during discovery */ 247 list_t phys; /* list of phys on this port */ 248 int nphy; /* number of phys in this port */ 249 scsi_hba_tgtmap_t *iss_tgtmap; /* tgtmap */ 250 ddi_soft_state_bystr *tgt_sstate; /* tgt softstate */ 251 }; 252 253 struct pmcs_chunk { 254 pmcs_chunk_t *next; 255 ddi_acc_handle_t acc_handle; 256 ddi_dma_handle_t dma_handle; 257 uint8_t *addrp; 258 uint64_t dma_addr; 259 }; 260 261 /* 262 * HBA node (i.e. non-iport) softstate 263 */ 264 struct pmcs_hw { 265 /* 266 * Identity 267 */ 268 dev_info_t *dip; 269 270 /* 271 * 16 possible initiator PHY WWNs 272 */ 273 uint64_t sas_wwns[PMCS_MAX_PORTS]; 274 275 /* 276 * Card State 277 */ 278 enum pwpstate { 279 STATE_NIL, 280 STATE_PROBING, 281 STATE_RUNNING, 282 STATE_UNPROBING, 283 STATE_DEAD 284 } state; 285 286 uint32_t 287 fw_disable_update : 1, 288 fw_force_update : 1, 289 blocked : 1, 290 stuck : 1, 291 locks_initted : 1, 292 mpi_table_setup : 1, 293 hba_attached : 1, 294 iports_attached : 1, 295 suspended : 1, 296 separate_ports : 1, 297 fwlog : 4, 298 phymode : 3, 299 physpeed : 3, 300 resource_limited : 1, 301 configuring : 1, 302 ds_err_recovering : 1; 303 304 /* 305 * This HBA instance's iportmap and list of iport states. 306 * Note: iports_lock protects iports, iports_attached, and 307 * num_iports on the HBA softstate. 308 */ 309 krwlock_t iports_lock; 310 scsi_hba_iportmap_t *hss_iportmap; 311 list_t iports; 312 int num_iports; 313 314 sas_phymap_t *hss_phymap; 315 int phymap_active; 316 317 /* 318 * Locks 319 */ 320 kmutex_t lock; 321 kmutex_t dma_lock; 322 kmutex_t axil_lock; 323 kcondvar_t drain_cv; 324 325 /* 326 * FMA Capabilities 327 */ 328 int fm_capabilities; 329 330 /* 331 * Register Access Handles 332 */ 333 ddi_device_acc_attr_t dev_acc_attr; 334 ddi_device_acc_attr_t reg_acc_attr; 335 ddi_acc_handle_t pci_acc_handle; 336 ddi_acc_handle_t msg_acc_handle; 337 ddi_acc_handle_t top_acc_handle; 338 ddi_acc_handle_t mpi_acc_handle; 339 ddi_acc_handle_t gsm_acc_handle; 340 ddi_acc_handle_t iqp_acchdls[PMCS_MAX_IQ]; 341 ddi_acc_handle_t oqp_acchdls[PMCS_MAX_IQ]; 342 ddi_acc_handle_t cip_acchdls; 343 ddi_acc_handle_t fwlog_acchdl; 344 ddi_acc_handle_t regdump_acchdl; 345 346 /* 347 * DMA Handles 348 */ 349 ddi_dma_attr_t iqp_dma_attr; 350 ddi_dma_attr_t oqp_dma_attr; 351 ddi_dma_attr_t cip_dma_attr; 352 ddi_dma_attr_t fwlog_dma_attr; 353 ddi_dma_attr_t regdump_dma_attr; 354 ddi_dma_handle_t iqp_handles[PMCS_MAX_IQ]; 355 ddi_dma_handle_t oqp_handles[PMCS_MAX_OQ]; 356 ddi_dma_handle_t cip_handles; 357 ddi_dma_handle_t fwlog_hndl; 358 ddi_dma_handle_t regdump_hndl; 359 360 /* 361 * Register Pointers 362 */ 363 uint32_t *msg_regs; /* message unit registers */ 364 uint32_t *top_regs; /* top unit registers */ 365 uint32_t *mpi_regs; /* message passing unit registers */ 366 uint32_t *gsm_regs; /* GSM registers */ 367 368 /* 369 * Message Passing and other offsets. 370 * 371 * mpi_offset is the offset within the fourth register set (mpi_regs) 372 * that contains the base of the MPI structures. Since this is actually 373 * set by the card firmware, it can change from startup to startup. 374 * 375 * The other offsets (gst, iqc, oqc) are for similar tables in 376 * MPI space, typically only accessed during setup. 377 */ 378 uint32_t mpi_offset; 379 uint32_t mpi_gst_offset; 380 uint32_t mpi_iqc_offset; 381 uint32_t mpi_oqc_offset; 382 383 /* 384 * Inbound and outbound queue depth 385 */ 386 uint32_t ioq_depth; 387 388 /* 389 * Kernel addresses and offsets for Inbound Queue Producer Indices 390 * 391 * See comments in pmcs_iomb.h about Inbound Queues. Since it 392 * is relatively expensive to go across the PCIe bus to read or 393 * write inside the card, we maintain shadow copies in kernel 394 * memory and update the card as needed. 395 */ 396 uint32_t shadow_iqpi[PMCS_MAX_IQ]; 397 uint32_t iqpi_offset[PMCS_MAX_IQ]; 398 uint32_t *iqp[PMCS_MAX_IQ]; 399 kmutex_t iqp_lock[PMCS_NIQ]; 400 401 pmcs_iqp_trace_t *iqpt; 402 403 /* 404 * Kernel addresses and offsets for Outbound Queue Consumer Indices 405 */ 406 uint32_t *oqp[PMCS_MAX_OQ]; 407 uint32_t oqci_offset[PMCS_MAX_OQ]; 408 409 /* 410 * Driver's copy of the outbound queue indices 411 */ 412 413 uint32_t oqci[PMCS_NOQ]; 414 uint32_t oqpi[PMCS_NOQ]; 415 416 /* 417 * DMA addresses for both Inbound and Outbound queues. 418 */ 419 uint64_t oqaddr[PMCS_MAX_OQ]; 420 uint64_t iqaddr[PMCS_MAX_IQ]; 421 422 /* 423 * Producer/Queue Host Memory Pointers and scratch areas, 424 * as well as DMA scatter/gather chunk areas. 425 * 426 * See discussion in pmcs_def.h about how this is laid out. 427 */ 428 uint8_t *cip; 429 uint64_t ciaddr; 430 431 /* 432 * Scratch area pointer and DMA addrress for SATA and SMP operations. 433 */ 434 void *scratch; 435 uint64_t scratch_dma; 436 volatile uint8_t scratch_locked; /* Scratch area ownership */ 437 438 /* 439 * Firmware log pointer 440 */ 441 uint32_t *fwlogp; 442 uint64_t fwaddr; 443 444 /* 445 * Internal register dump region and flash chunk DMA info 446 */ 447 448 caddr_t regdumpp; 449 uint32_t *flash_chunkp; 450 uint64_t flash_chunk_addr; 451 452 /* 453 * Card information, some determined during MPI setup 454 */ 455 uint32_t fw; /* firmware version */ 456 uint8_t max_iq; /* maximum inbound queues this card */ 457 uint8_t max_oq; /* "" outbound "" */ 458 uint8_t nphy; /* number of phys this card */ 459 uint8_t chiprev; /* chip revision */ 460 uint16_t max_cmd; /* max number of commands supported */ 461 uint16_t max_dev; /* max number of devices supported */ 462 uint16_t last_wq_dev; /* last dev whose wq was serviced */ 463 464 465 /* 466 * Interrupt Setup stuff. 467 * 468 * int_type defines the kind of interrupt we're using with this card. 469 * oqvec defines the relationship between an Outbound Queue Number and 470 * a MSI-X vector. 471 */ 472 enum { 473 PMCS_INT_NONE, 474 PMCS_INT_TIMER, 475 PMCS_INT_MSI, 476 PMCS_INT_MSIX, 477 PMCS_INT_FIXED 478 } int_type; 479 uint8_t oqvec[PMCS_NOQ]; 480 481 /* 482 * Interrupt handle table and size 483 */ 484 ddi_intr_handle_t *ih_table; 485 size_t ih_table_size; 486 487 timeout_id_t wdhandle; 488 uint32_t intr_mask; 489 int intr_cnt; 490 int intr_cap; 491 uint32_t odb_auto_clear; 492 493 /* 494 * DMA S/G chunk list 495 */ 496 int nchunks; 497 pmcs_chunk_t *dma_chunklist; 498 499 /* 500 * Front of the DMA S/G chunk freelist 501 */ 502 pmcs_dmachunk_t *dma_freelist; 503 504 /* 505 * PHY and Discovery Related Stuff 506 * 507 * The PMC chip can have up to 16 local phys. We build a level-first 508 * traversal tree of phys starting with the physical phys on the 509 * chip itself (i.e., treating the chip as if it were an expander). 510 * 511 * Our discovery process goes through a level and discovers what 512 * each entity is (and it's phy number within that expander's 513 * address space). It then configures each non-empty item (SAS, 514 * SATA/STP, EXPANDER). For expanders, it then performs 515 * discover on that expander itself via REPORT GENERAL and 516 * DISCOVERY SMP commands, attaching the discovered entities 517 * to the next level. Then we step down a level and continue 518 * (and so on). 519 * 520 * The PMC chip maintains an I_T_NEXUS notion based upon our 521 * registering each new device found (getting back a device handle). 522 * 523 * Like with the number of physical PHYS being a maximum of 16, 524 * there are a maximum number of PORTS also being 16. Some 525 * events apply to PORTS entirely, so we track PORTS as well. 526 */ 527 pmcs_phy_t *root_phys; /* HBA PHYs (level 0) */ 528 pmcs_phy_t *ports[PMCS_MAX_PORTS]; 529 kmutex_t dead_phylist_lock; /* Protects dead_phys */ 530 pmcs_phy_t *dead_phys; /* PHYs waiting to be freed */ 531 532 kmem_cache_t *phy_cache; 533 534 /* 535 * Discovery-related items. 536 * config_lock: Protects config_changed and should never be held 537 * outside of getting or setting the value of config_changed. 538 * config_changed: Boolean indicating whether discovery needs to 539 * be restarted. 540 * configuring: 1 = discovery is running, 0 = discovery not running. 541 * NOTE: configuring is now in the bitfield above. 542 */ 543 kmutex_t config_lock; 544 volatile boolean_t config_changed; 545 546 /* 547 * Work Related Stuff 548 * 549 * Each command given to the PMC chip has an associated work structure. 550 * See the discussion in pmcs_def.h about work structures. 551 */ 552 pmcwork_t *work; /* pool of work structures */ 553 STAILQ_HEAD(wfh, pmcwork) wf; /* current freelist */ 554 STAILQ_HEAD(pfh, pmcwork) pf; /* current pending freelist */ 555 uint16_t wserno; /* rolling serial number */ 556 kmutex_t wfree_lock; /* freelist/actvlist/wserno lock */ 557 kmutex_t pfree_lock; /* freelist/actvlist/wserno lock */ 558 559 /* 560 * Solaris/SCSA items. 561 */ 562 scsi_hba_tran_t *tran; 563 sas_hba_tran_t *smp_tran; 564 struct scsi_reset_notify_entry *reset_notify_listf; 565 566 /* 567 * Thread Level stuff. 568 * 569 * A number of tasks are done off worker thread taskq. 570 */ 571 ddi_taskq_t *tq; /* For the worker thread */ 572 volatile ulong_t work_flags; 573 574 /* 575 * Solaris target representation. 576 * targets = array of pointers to xscsi structures 577 * allocated by ssoftstate. 578 */ 579 pmcs_xscsi_t **targets; 580 581 STAILQ_HEAD(dqh, pmcs_cmd) dq; /* dead commands */ 582 STAILQ_HEAD(cqh, pmcs_cmd) cq; /* completed commands */ 583 kmutex_t cq_lock; 584 kmem_cache_t *iocomp_cb_cache; 585 pmcs_iocomp_cb_t *iocomp_cb_head; 586 pmcs_iocomp_cb_t *iocomp_cb_tail; 587 588 uint16_t debug_mask; 589 uint16_t phyid_block_mask; 590 uint16_t phys_started; 591 uint32_t hipri_queue; 592 uint32_t mpibar; 593 uint32_t intr_pri; 594 595 pmcs_io_intr_coal_t io_intr_coal; 596 pmcs_cq_info_t cq_info; 597 kmutex_t ict_lock; 598 kcondvar_t ict_cv; 599 kthread_t *ict_thread; 600 601 #ifdef DEBUG 602 kmutex_t dbglock; 603 uint32_t ltags[256]; 604 uint32_t ftags[256]; 605 hrtime_t ltime[256]; 606 hrtime_t ftime[256]; 607 uint16_t ftag_lines[256]; 608 uint8_t lti; /* last tag index */ 609 uint8_t fti; /* first tag index */ 610 #endif 611 }; 612 613 extern void *pmcs_softc_state; 614 extern void *pmcs_iport_softstate; 615 616 /* 617 * Some miscellaneous, oft used strings 618 */ 619 extern const char pmcs_nowrk[]; 620 extern const char pmcs_nomsg[]; 621 extern const char pmcs_timeo[]; 622 623 #ifdef __cplusplus 624 } 625 #endif 626 #endif /* _PMCS_H */ 627