1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Copyright (c) 2000-2015 LSI Corporation. 33 * Copyright (c) 2013-2016 Avago Technologies 34 * All rights reserved. 35 * 36 * 37 * Name: mpi2.h 38 * Title: MPI Message independent structures and definitions 39 * including System Interface Register Set and 40 * scatter/gather formats. 41 * Creation Date: June 21, 2006 42 * 43 * mpi2.h Version: 02.00.46 44 * 45 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 46 * prefix are for use only on MPI v2.5 products, and must not be used 47 * with MPI v2.0 products. Unless otherwise noted, names beginning with 48 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 49 * 50 * Version History 51 * --------------- 52 * 53 * Date Version Description 54 * -------- -------- ------------------------------------------------------ 55 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 56 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 57 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 58 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 59 * Moved ReplyPostHostIndex register to offset 0x6C of the 60 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 61 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 62 * Added union of request descriptors. 63 * Added union of reply descriptors. 64 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 65 * Added define for MPI2_VERSION_02_00. 66 * Fixed the size of the FunctionDependent5 field in the 67 * MPI2_DEFAULT_REPLY structure. 68 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 69 * Removed the MPI-defined Fault Codes and extended the 70 * product specific codes up to 0xEFFF. 71 * Added a sixth key value for the WriteSequence register 72 * and changed the flush value to 0x0. 73 * Added message function codes for Diagnostic Buffer Post 74 * and Diagnsotic Release. 75 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 76 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 77 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Added #defines for marking a reply descriptor as unused. 81 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 83 * Moved LUN field defines from mpi2_init.h. 84 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 85 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 86 * In all request and reply descriptors, replaced VF_ID 87 * field with MSIxIndex field. 88 * Removed DevHandle field from 89 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 90 * bytes reserved. 91 * Added RAID Accelerator functionality. 92 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 94 * Added MSI-x index mask and shift for Reply Post Host 95 * Index register. 96 * Added function code for Host Based Discovery Action. 97 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 99 * Added defines for product-specific range of message 100 * function codes, 0xF0 to 0xFF. 101 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added alternative defines for the SGE Direction bit. 103 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 104 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 105 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 106 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 107 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 108 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 109 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 110 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 111 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 112 * Incorporating additions for MPI v2.5. 113 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 115 * Added Hard Reset delay timings. 116 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 119 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 120 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 121 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 123 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 124 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 125 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 126 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 127 * 11-18-14 02.00.36 Updated copyright information. 128 * Bumped MPI2_HEADER_VERSION_UNIT. 129 * 03-16-15 02.00.37 Updated for MPI v2.6. 130 * Bumped MPI2_HEADER_VERSION_UNIT. 131 * Added Scratchpad registers and 132 * AtomicRequestDescriptorPost register to 133 * MPI2_SYSTEM_INTERFACE_REGS. 134 * Added MPI2_DIAG_SBR_RELOAD. 135 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 136 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 137 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 138 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 139 * Added V7 HostDiagnostic register defines 140 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 141 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 142 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 143 * to be unique within first 32 characters. 144 * Removed AHCI support. 145 * Removed SOP support. 146 * Bumped MPI2_HEADER_VERSION_UNIT. 147 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 148 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 149 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 150 * -------------------------------------------------------------------------- 151 */ 152 153 #ifndef MPI2_H 154 #define MPI2_H 155 156 157 /***************************************************************************** 158 * 159 * MPI Version Definitions 160 * 161 *****************************************************************************/ 162 163 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 164 #define MPI2_VERSION_MAJOR_SHIFT (8) 165 #define MPI2_VERSION_MINOR_MASK (0x00FF) 166 #define MPI2_VERSION_MINOR_SHIFT (0) 167 168 /* major version for all MPI v2.x */ 169 #define MPI2_VERSION_MAJOR (0x02) 170 171 /* minor version for MPI v2.0 compatible products */ 172 #define MPI2_VERSION_MINOR (0x00) 173 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 174 MPI2_VERSION_MINOR) 175 #define MPI2_VERSION_02_00 (0x0200) 176 177 178 /* minor version for MPI v2.5 compatible products */ 179 #define MPI25_VERSION_MINOR (0x05) 180 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 181 MPI25_VERSION_MINOR) 182 #define MPI2_VERSION_02_05 (0x0205) 183 184 185 /* minor version for MPI v2.6 compatible products */ 186 #define MPI26_VERSION_MINOR (0x06) 187 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 188 MPI26_VERSION_MINOR) 189 #define MPI2_VERSION_02_06 (0x0206) 190 191 192 /* Unit and Dev versioning for this MPI header set */ 193 #define MPI2_HEADER_VERSION_UNIT (0x2E) 194 #define MPI2_HEADER_VERSION_DEV (0x00) 195 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 196 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 197 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 198 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 199 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 200 201 202 /***************************************************************************** 203 * 204 * IOC State Definitions 205 * 206 *****************************************************************************/ 207 208 #define MPI2_IOC_STATE_RESET (0x00000000) 209 #define MPI2_IOC_STATE_READY (0x10000000) 210 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 211 #define MPI2_IOC_STATE_FAULT (0x40000000) 212 213 #define MPI2_IOC_STATE_MASK (0xF0000000) 214 #define MPI2_IOC_STATE_SHIFT (28) 215 216 /* Fault state range for prodcut specific codes */ 217 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 218 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 219 220 221 /***************************************************************************** 222 * 223 * System Interface Register Definitions 224 * 225 *****************************************************************************/ 226 227 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 228 { 229 U32 Doorbell; /* 0x00 */ 230 U32 WriteSequence; /* 0x04 */ 231 U32 HostDiagnostic; /* 0x08 */ 232 U32 Reserved1; /* 0x0C */ 233 U32 DiagRWData; /* 0x10 */ 234 U32 DiagRWAddressLow; /* 0x14 */ 235 U32 DiagRWAddressHigh; /* 0x18 */ 236 U32 Reserved2[5]; /* 0x1C */ 237 U32 HostInterruptStatus; /* 0x30 */ 238 U32 HostInterruptMask; /* 0x34 */ 239 U32 DCRData; /* 0x38 */ 240 U32 DCRAddress; /* 0x3C */ 241 U32 Reserved3[2]; /* 0x40 */ 242 U32 ReplyFreeHostIndex; /* 0x48 */ 243 U32 Reserved4[8]; /* 0x4C */ 244 U32 ReplyPostHostIndex; /* 0x6C */ 245 U32 Reserved5; /* 0x70 */ 246 U32 HCBSize; /* 0x74 */ 247 U32 HCBAddressLow; /* 0x78 */ 248 U32 HCBAddressHigh; /* 0x7C */ 249 U32 Reserved6[12]; /* 0x80 */ 250 U32 Scratchpad[4]; /* 0xB0 */ 251 U32 RequestDescriptorPostLow; /* 0xC0 */ 252 U32 RequestDescriptorPostHigh; /* 0xC4 */ 253 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 254 U32 Reserved7[13]; /* 0xCC */ 255 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 256 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 257 258 /* 259 * Defines for working with the Doorbell register. 260 */ 261 #define MPI2_DOORBELL_OFFSET (0x00000000) 262 263 /* IOC --> System values */ 264 #define MPI2_DOORBELL_USED (0x08000000) 265 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 266 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 267 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 268 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 269 270 /* System --> IOC values */ 271 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 272 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 273 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 274 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 275 276 277 /* 278 * Defines for the WriteSequence register 279 */ 280 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 281 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 282 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 283 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 284 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 285 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 286 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 287 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 288 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 289 290 /* 291 * Defines for the HostDiagnostic register 292 */ 293 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 294 295 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 296 297 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 298 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 300 301 /* Defines for V7A/V7R HostDiagnostic Register */ 302 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 303 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 304 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 305 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 306 307 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 308 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 309 #define MPI2_DIAG_HCB_MODE (0x00000100) 310 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 311 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 312 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 313 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 314 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 315 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 316 317 /* 318 * Offsets for DiagRWData and address 319 */ 320 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 321 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 322 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 323 324 /* 325 * Defines for the HostInterruptStatus register 326 */ 327 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 328 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 329 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 330 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 331 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 332 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 333 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 334 335 /* 336 * Defines for the HostInterruptMask register 337 */ 338 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 339 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 340 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 341 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 342 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 343 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 344 345 /* 346 * Offsets for DCRData and address 347 */ 348 #define MPI2_DCR_DATA_OFFSET (0x00000038) 349 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 350 351 /* 352 * Offset for the Reply Free Queue 353 */ 354 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 355 356 /* 357 * Defines for the Reply Descriptor Post Queue 358 */ 359 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 360 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 361 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 362 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 363 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 364 365 366 /* 367 * Defines for the HCBSize and address 368 */ 369 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 370 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 371 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 372 373 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 374 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 375 376 /* 377 * Offsets for the Scratchpad registers 378 */ 379 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 380 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 381 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 382 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 383 384 /* 385 * Offsets for the Request Descriptor Post Queue 386 */ 387 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 388 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 389 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 390 391 392 /* Hard Reset delay timings */ 393 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 394 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 395 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 396 397 /***************************************************************************** 398 * 399 * Message Descriptors 400 * 401 *****************************************************************************/ 402 403 /* Request Descriptors */ 404 405 /* Default Request Descriptor */ 406 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 407 { 408 U8 RequestFlags; /* 0x00 */ 409 U8 MSIxIndex; /* 0x01 */ 410 U16 SMID; /* 0x02 */ 411 U16 LMID; /* 0x04 */ 412 U16 DescriptorTypeDependent; /* 0x06 */ 413 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 414 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 415 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 416 417 /* defines for the RequestFlags field */ 418 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 419 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 420 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 421 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 422 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 423 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 424 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 425 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 426 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 427 428 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 429 430 431 /* High Priority Request Descriptor */ 432 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 433 { 434 U8 RequestFlags; /* 0x00 */ 435 U8 MSIxIndex; /* 0x01 */ 436 U16 SMID; /* 0x02 */ 437 U16 LMID; /* 0x04 */ 438 U16 Reserved1; /* 0x06 */ 439 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 440 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 441 Mpi2HighPriorityRequestDescriptor_t, 442 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 443 444 445 /* SCSI IO Request Descriptor */ 446 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 447 { 448 U8 RequestFlags; /* 0x00 */ 449 U8 MSIxIndex; /* 0x01 */ 450 U16 SMID; /* 0x02 */ 451 U16 LMID; /* 0x04 */ 452 U16 DevHandle; /* 0x06 */ 453 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 454 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 455 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 456 457 458 /* SCSI Target Request Descriptor */ 459 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 460 { 461 U8 RequestFlags; /* 0x00 */ 462 U8 MSIxIndex; /* 0x01 */ 463 U16 SMID; /* 0x02 */ 464 U16 LMID; /* 0x04 */ 465 U16 IoIndex; /* 0x06 */ 466 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 467 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 468 Mpi2SCSITargetRequestDescriptor_t, 469 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 470 471 472 /* RAID Accelerator Request Descriptor */ 473 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 474 { 475 U8 RequestFlags; /* 0x00 */ 476 U8 MSIxIndex; /* 0x01 */ 477 U16 SMID; /* 0x02 */ 478 U16 LMID; /* 0x04 */ 479 U16 Reserved; /* 0x06 */ 480 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 481 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 482 Mpi2RAIDAcceleratorRequestDescriptor_t, 483 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 484 485 486 /* Fast Path SCSI IO Request Descriptor */ 487 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 488 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 489 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 490 Mpi25FastPathSCSIIORequestDescriptor_t, 491 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 492 493 494 /* PCIe Encapsulated Request Descriptor */ 495 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 496 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 497 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 498 Mpi26PCIeEncapsulatedRequestDescriptor_t, 499 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 500 501 502 /* union of Request Descriptors */ 503 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 504 { 505 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 506 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 507 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 508 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 509 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 510 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 511 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 512 U64 Words; 513 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 514 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 515 516 517 /* Atomic Request Descriptors */ 518 519 /* 520 * All Atomic Request Descriptors have the same format, so the following 521 * structure is used for all Atomic Request Descriptors: 522 * Atomic Default Request Descriptor 523 * Atomic High Priority Request Descriptor 524 * Atomic SCSI IO Request Descriptor 525 * Atomic SCSI Target Request Descriptor 526 * Atomic RAID Accelerator Request Descriptor 527 * Atomic Fast Path SCSI IO Request Descriptor 528 * Atomic PCIe Encapsulated Request Descriptor 529 */ 530 531 /* Atomic Request Descriptor */ 532 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 533 { 534 U8 RequestFlags; /* 0x00 */ 535 U8 MSIxIndex; /* 0x01 */ 536 U16 SMID; /* 0x02 */ 537 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 538 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 539 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 540 541 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 542 543 544 /* Reply Descriptors */ 545 546 /* Default Reply Descriptor */ 547 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 548 { 549 U8 ReplyFlags; /* 0x00 */ 550 U8 MSIxIndex; /* 0x01 */ 551 U16 DescriptorTypeDependent1; /* 0x02 */ 552 U32 DescriptorTypeDependent2; /* 0x04 */ 553 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 554 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 555 556 /* defines for the ReplyFlags field */ 557 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 558 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 559 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 560 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 561 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 562 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 563 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 564 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 565 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 566 567 /* values for marking a reply descriptor as unused */ 568 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 569 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 570 571 /* Address Reply Descriptor */ 572 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 573 { 574 U8 ReplyFlags; /* 0x00 */ 575 U8 MSIxIndex; /* 0x01 */ 576 U16 SMID; /* 0x02 */ 577 U32 ReplyFrameAddress; /* 0x04 */ 578 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 579 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 580 581 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 582 583 584 /* SCSI IO Success Reply Descriptor */ 585 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 586 { 587 U8 ReplyFlags; /* 0x00 */ 588 U8 MSIxIndex; /* 0x01 */ 589 U16 SMID; /* 0x02 */ 590 U16 TaskTag; /* 0x04 */ 591 U16 Reserved1; /* 0x06 */ 592 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 593 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 594 Mpi2SCSIIOSuccessReplyDescriptor_t, 595 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 596 597 598 /* TargetAssist Success Reply Descriptor */ 599 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 600 { 601 U8 ReplyFlags; /* 0x00 */ 602 U8 MSIxIndex; /* 0x01 */ 603 U16 SMID; /* 0x02 */ 604 U8 SequenceNumber; /* 0x04 */ 605 U8 Reserved1; /* 0x05 */ 606 U16 IoIndex; /* 0x06 */ 607 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 608 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 609 Mpi2TargetAssistSuccessReplyDescriptor_t, 610 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 611 612 613 /* Target Command Buffer Reply Descriptor */ 614 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 615 { 616 U8 ReplyFlags; /* 0x00 */ 617 U8 MSIxIndex; /* 0x01 */ 618 U8 VP_ID; /* 0x02 */ 619 U8 Flags; /* 0x03 */ 620 U16 InitiatorDevHandle; /* 0x04 */ 621 U16 IoIndex; /* 0x06 */ 622 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 623 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 624 Mpi2TargetCommandBufferReplyDescriptor_t, 625 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 626 627 /* defines for Flags field */ 628 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 629 630 631 /* RAID Accelerator Success Reply Descriptor */ 632 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 633 { 634 U8 ReplyFlags; /* 0x00 */ 635 U8 MSIxIndex; /* 0x01 */ 636 U16 SMID; /* 0x02 */ 637 U32 Reserved; /* 0x04 */ 638 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 639 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 640 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 641 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 642 643 644 /* Fast Path SCSI IO Success Reply Descriptor */ 645 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 646 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 647 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 648 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 649 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 650 651 652 /* PCIe Encapsulated Success Reply Descriptor */ 653 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 654 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 655 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 656 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 657 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 658 659 660 /* union of Reply Descriptors */ 661 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 662 { 663 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 664 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 665 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 666 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 667 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 668 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 669 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 670 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 671 U64 Words; 672 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 673 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 674 675 676 677 /***************************************************************************** 678 * 679 * Message Functions 680 * 681 *****************************************************************************/ 682 683 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 684 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 685 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 686 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 687 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 688 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 689 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 690 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 691 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 692 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 693 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 694 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 695 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 696 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 697 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 698 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 699 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 700 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 701 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 702 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 703 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 704 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 705 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 706 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 707 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 708 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 709 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 710 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 711 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 712 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 713 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 714 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 715 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 716 717 718 719 /* Doorbell functions */ 720 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 721 #define MPI2_FUNCTION_HANDSHAKE (0x42) 722 723 724 /***************************************************************************** 725 * 726 * IOC Status Values 727 * 728 *****************************************************************************/ 729 730 /* mask for IOCStatus status value */ 731 #define MPI2_IOCSTATUS_MASK (0x7FFF) 732 733 /**************************************************************************** 734 * Common IOCStatus values for all replies 735 ****************************************************************************/ 736 737 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 738 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 739 #define MPI2_IOCSTATUS_BUSY (0x0002) 740 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 741 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 742 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 743 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 744 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 745 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 746 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 747 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 748 749 /**************************************************************************** 750 * Config IOCStatus values 751 ****************************************************************************/ 752 753 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 754 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 755 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 756 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 757 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 758 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 759 760 /**************************************************************************** 761 * SCSI IO Reply 762 ****************************************************************************/ 763 764 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 765 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 766 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 767 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 768 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 769 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 770 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 771 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 772 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 773 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 774 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 775 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 776 777 /**************************************************************************** 778 * For use by SCSI Initiator and SCSI Target end-to-end data protection 779 ****************************************************************************/ 780 781 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 782 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 783 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 784 785 /**************************************************************************** 786 * SCSI Target values 787 ****************************************************************************/ 788 789 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 790 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 791 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 792 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 793 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 794 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 795 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 796 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 797 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 798 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 799 800 /**************************************************************************** 801 * Serial Attached SCSI values 802 ****************************************************************************/ 803 804 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 805 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 806 807 /**************************************************************************** 808 * Diagnostic Buffer Post / Diagnostic Release values 809 ****************************************************************************/ 810 811 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 812 813 /**************************************************************************** 814 * RAID Accelerator values 815 ****************************************************************************/ 816 817 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 818 819 /**************************************************************************** 820 * IOCStatus flag to indicate that log info is available 821 ****************************************************************************/ 822 823 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 824 825 /**************************************************************************** 826 * IOCLogInfo Types 827 ****************************************************************************/ 828 829 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 830 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 831 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 832 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 833 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 834 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 835 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 836 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 837 838 839 /***************************************************************************** 840 * 841 * Standard Message Structures 842 * 843 *****************************************************************************/ 844 845 /**************************************************************************** 846 * Request Message Header for all request messages 847 ****************************************************************************/ 848 849 typedef struct _MPI2_REQUEST_HEADER 850 { 851 U16 FunctionDependent1; /* 0x00 */ 852 U8 ChainOffset; /* 0x02 */ 853 U8 Function; /* 0x03 */ 854 U16 FunctionDependent2; /* 0x04 */ 855 U8 FunctionDependent3; /* 0x06 */ 856 U8 MsgFlags; /* 0x07 */ 857 U8 VP_ID; /* 0x08 */ 858 U8 VF_ID; /* 0x09 */ 859 U16 Reserved1; /* 0x0A */ 860 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 861 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 862 863 864 /**************************************************************************** 865 * Default Reply 866 ****************************************************************************/ 867 868 typedef struct _MPI2_DEFAULT_REPLY 869 { 870 U16 FunctionDependent1; /* 0x00 */ 871 U8 MsgLength; /* 0x02 */ 872 U8 Function; /* 0x03 */ 873 U16 FunctionDependent2; /* 0x04 */ 874 U8 FunctionDependent3; /* 0x06 */ 875 U8 MsgFlags; /* 0x07 */ 876 U8 VP_ID; /* 0x08 */ 877 U8 VF_ID; /* 0x09 */ 878 U16 Reserved1; /* 0x0A */ 879 U16 FunctionDependent5; /* 0x0C */ 880 U16 IOCStatus; /* 0x0E */ 881 U32 IOCLogInfo; /* 0x10 */ 882 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 883 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 884 885 886 /* common version structure/union used in messages and configuration pages */ 887 888 typedef struct _MPI2_VERSION_STRUCT 889 { 890 U8 Dev; /* 0x00 */ 891 U8 Unit; /* 0x01 */ 892 U8 Minor; /* 0x02 */ 893 U8 Major; /* 0x03 */ 894 } MPI2_VERSION_STRUCT; 895 896 typedef union _MPI2_VERSION_UNION 897 { 898 MPI2_VERSION_STRUCT Struct; 899 U32 Word; 900 } MPI2_VERSION_UNION; 901 902 903 /* LUN field defines, common to many structures */ 904 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 905 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 906 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 907 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 908 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 909 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 910 911 912 /***************************************************************************** 913 * 914 * Fusion-MPT MPI Scatter Gather Elements 915 * 916 *****************************************************************************/ 917 918 /**************************************************************************** 919 * MPI Simple Element structures 920 ****************************************************************************/ 921 922 typedef struct _MPI2_SGE_SIMPLE32 923 { 924 U32 FlagsLength; 925 U32 Address; 926 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 927 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 928 929 typedef struct _MPI2_SGE_SIMPLE64 930 { 931 U32 FlagsLength; 932 U64 Address; 933 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 934 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 935 936 typedef struct _MPI2_SGE_SIMPLE_UNION 937 { 938 U32 FlagsLength; 939 union 940 { 941 U32 Address32; 942 U64 Address64; 943 } u; 944 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 945 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 946 947 948 /**************************************************************************** 949 * MPI Chain Element structures - for MPI v2.0 products only 950 ****************************************************************************/ 951 952 typedef struct _MPI2_SGE_CHAIN32 953 { 954 U16 Length; 955 U8 NextChainOffset; 956 U8 Flags; 957 U32 Address; 958 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 959 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 960 961 typedef struct _MPI2_SGE_CHAIN64 962 { 963 U16 Length; 964 U8 NextChainOffset; 965 U8 Flags; 966 U64 Address; 967 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 968 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 969 970 typedef struct _MPI2_SGE_CHAIN_UNION 971 { 972 U16 Length; 973 U8 NextChainOffset; 974 U8 Flags; 975 union 976 { 977 U32 Address32; 978 U64 Address64; 979 } u; 980 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 981 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 982 983 984 /**************************************************************************** 985 * MPI Transaction Context Element structures - for MPI v2.0 products only 986 ****************************************************************************/ 987 988 typedef struct _MPI2_SGE_TRANSACTION32 989 { 990 U8 Reserved; 991 U8 ContextSize; 992 U8 DetailsLength; 993 U8 Flags; 994 U32 TransactionContext[1]; 995 U32 TransactionDetails[1]; 996 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 997 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 998 999 typedef struct _MPI2_SGE_TRANSACTION64 1000 { 1001 U8 Reserved; 1002 U8 ContextSize; 1003 U8 DetailsLength; 1004 U8 Flags; 1005 U32 TransactionContext[2]; 1006 U32 TransactionDetails[1]; 1007 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 1008 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 1009 1010 typedef struct _MPI2_SGE_TRANSACTION96 1011 { 1012 U8 Reserved; 1013 U8 ContextSize; 1014 U8 DetailsLength; 1015 U8 Flags; 1016 U32 TransactionContext[3]; 1017 U32 TransactionDetails[1]; 1018 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 1019 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 1020 1021 typedef struct _MPI2_SGE_TRANSACTION128 1022 { 1023 U8 Reserved; 1024 U8 ContextSize; 1025 U8 DetailsLength; 1026 U8 Flags; 1027 U32 TransactionContext[4]; 1028 U32 TransactionDetails[1]; 1029 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1030 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1031 1032 typedef struct _MPI2_SGE_TRANSACTION_UNION 1033 { 1034 U8 Reserved; 1035 U8 ContextSize; 1036 U8 DetailsLength; 1037 U8 Flags; 1038 union 1039 { 1040 U32 TransactionContext32[1]; 1041 U32 TransactionContext64[2]; 1042 U32 TransactionContext96[3]; 1043 U32 TransactionContext128[4]; 1044 } u; 1045 U32 TransactionDetails[1]; 1046 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1047 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1048 1049 1050 /**************************************************************************** 1051 * MPI SGE union for IO SGL's - for MPI v2.0 products only 1052 ****************************************************************************/ 1053 1054 typedef struct _MPI2_MPI_SGE_IO_UNION 1055 { 1056 union 1057 { 1058 MPI2_SGE_SIMPLE_UNION Simple; 1059 MPI2_SGE_CHAIN_UNION Chain; 1060 } u; 1061 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1062 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1063 1064 1065 /**************************************************************************** 1066 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1067 ****************************************************************************/ 1068 1069 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1070 { 1071 union 1072 { 1073 MPI2_SGE_SIMPLE_UNION Simple; 1074 MPI2_SGE_TRANSACTION_UNION Transaction; 1075 } u; 1076 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1077 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1078 1079 1080 /**************************************************************************** 1081 * All MPI SGE types union 1082 ****************************************************************************/ 1083 1084 typedef struct _MPI2_MPI_SGE_UNION 1085 { 1086 union 1087 { 1088 MPI2_SGE_SIMPLE_UNION Simple; 1089 MPI2_SGE_CHAIN_UNION Chain; 1090 MPI2_SGE_TRANSACTION_UNION Transaction; 1091 } u; 1092 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1093 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1094 1095 1096 /**************************************************************************** 1097 * MPI SGE field definition and masks 1098 ****************************************************************************/ 1099 1100 /* Flags field bit definitions */ 1101 1102 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1103 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1104 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1105 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1106 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1107 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1108 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1109 1110 #define MPI2_SGE_FLAGS_SHIFT (24) 1111 1112 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1113 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1114 1115 /* Element Type */ 1116 1117 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1118 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1119 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1120 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1121 1122 /* Address location */ 1123 1124 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1125 1126 /* Direction */ 1127 1128 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1129 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1130 1131 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1132 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1133 1134 /* Address Size */ 1135 1136 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1137 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1138 1139 /* Context Size */ 1140 1141 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1142 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1143 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1144 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1145 1146 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1147 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1148 1149 /**************************************************************************** 1150 * MPI SGE operation Macros 1151 ****************************************************************************/ 1152 1153 /* SIMPLE FlagsLength manipulations... */ 1154 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1155 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1156 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1157 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1158 1159 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1160 1161 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1162 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1163 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1164 1165 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1166 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1167 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1168 1169 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1170 1171 1172 /***************************************************************************** 1173 * 1174 * Fusion-MPT IEEE Scatter Gather Elements 1175 * 1176 *****************************************************************************/ 1177 1178 /**************************************************************************** 1179 * IEEE Simple Element structures 1180 ****************************************************************************/ 1181 1182 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1183 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1184 { 1185 U32 Address; 1186 U32 FlagsLength; 1187 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1188 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1189 1190 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1191 { 1192 U64 Address; 1193 U32 Length; 1194 U16 Reserved1; 1195 U8 Reserved2; 1196 U8 Flags; 1197 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1198 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1199 1200 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1201 { 1202 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1203 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1204 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1205 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1206 1207 1208 /**************************************************************************** 1209 * IEEE Chain Element structures 1210 ****************************************************************************/ 1211 1212 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1213 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1214 1215 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1216 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1217 1218 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1219 { 1220 MPI2_IEEE_SGE_CHAIN32 Chain32; 1221 MPI2_IEEE_SGE_CHAIN64 Chain64; 1222 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1223 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1224 1225 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1226 typedef struct _MPI25_IEEE_SGE_CHAIN64 1227 { 1228 U64 Address; 1229 U32 Length; 1230 U16 Reserved1; 1231 U8 NextChainOffset; 1232 U8 Flags; 1233 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1234 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1235 1236 1237 /**************************************************************************** 1238 * All IEEE SGE types union 1239 ****************************************************************************/ 1240 1241 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1242 typedef struct _MPI2_IEEE_SGE_UNION 1243 { 1244 union 1245 { 1246 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1247 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1248 } u; 1249 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1250 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1251 1252 1253 /**************************************************************************** 1254 * IEEE SGE union for IO SGL's 1255 ****************************************************************************/ 1256 1257 typedef union _MPI25_SGE_IO_UNION 1258 { 1259 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1260 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1261 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1262 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1263 1264 1265 /**************************************************************************** 1266 * IEEE SGE field definitions and masks 1267 ****************************************************************************/ 1268 1269 /* Flags field bit definitions */ 1270 1271 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1272 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1273 1274 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1275 1276 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1277 1278 /* Element Type */ 1279 1280 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1281 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1282 1283 /* Next Segment Format */ 1284 1285 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1286 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1287 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1288 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1289 1290 /* Data Location Address Space */ 1291 1292 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1293 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1294 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1295 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1296 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1297 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1298 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1299 1300 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1301 1302 /**************************************************************************** 1303 * IEEE SGE operation Macros 1304 ****************************************************************************/ 1305 1306 /* SIMPLE FlagsLength manipulations... */ 1307 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1308 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1309 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1310 1311 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1312 1313 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1314 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1315 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1316 1317 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1318 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1319 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1320 1321 1322 1323 /***************************************************************************** 1324 * 1325 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1326 * 1327 *****************************************************************************/ 1328 1329 typedef union _MPI2_SIMPLE_SGE_UNION 1330 { 1331 MPI2_SGE_SIMPLE_UNION MpiSimple; 1332 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1333 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1334 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1335 1336 1337 typedef union _MPI2_SGE_IO_UNION 1338 { 1339 MPI2_SGE_SIMPLE_UNION MpiSimple; 1340 MPI2_SGE_CHAIN_UNION MpiChain; 1341 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1342 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1343 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1344 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1345 1346 1347 /**************************************************************************** 1348 * 1349 * Values for SGLFlags field, used in many request messages with an SGL 1350 * 1351 ****************************************************************************/ 1352 1353 /* values for MPI SGL Data Location Address Space subfield */ 1354 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1355 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1356 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1357 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1358 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1359 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1360 /* values for SGL Type subfield */ 1361 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1362 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1363 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1364 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1365 1366 1367 #endif 1368 1369