1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 QLogic Corporation. All rights reserved. 24 */ 25 26 #ifndef _QLGE_H 27 #define _QLGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/sunmdi.h> 36 #include <sys/modctl.h> 37 #include <sys/pci.h> 38 #include <sys/dlpi.h> 39 #include <sys/sdt.h> 40 #include <sys/mac_provider.h> 41 #include <sys/mac.h> 42 #include <sys/mac_flow.h> 43 #include <sys/mac_ether.h> 44 #include <sys/vlan.h> 45 #include <sys/netlb.h> 46 #include <sys/kmem.h> 47 #include <sys/file.h> 48 #include <sys/proc.h> 49 #include <sys/callb.h> 50 #include <sys/disp.h> 51 #include <sys/strsun.h> 52 #include <sys/ethernet.h> 53 #include <sys/miiregs.h> 54 #include <sys/kstat.h> 55 #include <sys/byteorder.h> 56 57 #include <qlge_hw.h> 58 #include <qlge_dbg.h> 59 #include <qlge_open.h> 60 61 #define ADAPTER_NAME "qlge" 62 63 /* 64 * Local Macro Definitions. 65 */ 66 #ifdef TRUE 67 #undef TRUE 68 #endif 69 #define TRUE 1 70 71 #ifdef FALSE 72 #undef FALSE 73 #endif 74 #define FALSE 0 75 76 /* #define QLGE_TRACK_BUFFER_USAGE */ 77 /* 78 * byte order, sparc is big endian, x86 is little endian, 79 * but PCI is little endian only 80 */ 81 #ifdef sparc 82 #define cpu_to_le64(x) BSWAP_64(x) 83 #define cpu_to_le32(x) BSWAP_32(x) 84 #define cpu_to_le16(x) BSWAP_16(x) 85 #define le64_to_cpu(x) cpu_to_le64(x) 86 #define le32_to_cpu(x) cpu_to_le32(x) 87 #define le16_to_cpu(x) cpu_to_le16(x) 88 #else 89 #define cpu_to_le64(x) (x) 90 #define cpu_to_le32(x) (x) 91 #define cpu_to_le16(x) (x) 92 #define le64_to_cpu(x) (x) 93 #define le32_to_cpu(x) (x) 94 #define le16_to_cpu(x) (x) 95 #endif 96 97 /* 98 * Macros to help code, maintain, etc. 99 */ 100 101 #define LSB(x) (uint8_t)(x) 102 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 103 104 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 105 #define LSW(x) (uint16_t)(x) 106 107 #define MS32(x) (uint32_t)((uint32_t)(x) >> 32) 108 #define LS32(x) (uint32_t)(x) 109 110 #define MSW_LSB(x) (uint8_t)(LSB(MSW(x))) 111 #define MSW_MSB(x) (uint8_t)(MSB(MSW(x))) 112 113 #define LSD(x) (uint32_t)(x) 114 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 115 116 #define SHORT_TO_LONG(a, b) (uint32_t)((uint16_t)b << 16 | (uint16_t)a) 117 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a) 118 119 #define SWAP_ENDIAN_16(x) ((LSB(x) << 8) | MSB(x)) 120 121 #define SWAP_ENDIAN_32(x) ((SWAP_ENDIAN_16(LSW(x)) << 16) | \ 122 SWAP_ENDIAN_16(MSW(x))) 123 124 #define SWAP_ENDIAN_64(x) ((SWAP_ENDIAN_32(LS32(x)) << 32) | \ 125 SWAP_ENDIAN_32(MS32(x))) 126 127 #define QL_MIN(x, y) ((x < y) ? x : y) 128 129 #define CARRIER_ON(qlge) mac_link_update((qlge)->mh, LINK_STATE_UP) 130 #define CARRIER_OFF(qlge) mac_link_update((qlge)->mh, LINK_STATE_DOWN) 131 132 /* 133 * qlge local function return status codes 134 */ 135 #define QL_ERROR 1 136 #define QL_SUCCESS 0 137 /* 138 * Solaris version compatibility definitions. 139 */ 140 #define QL_GET_LBOLT(timer) timer = ddi_get_lbolt() 141 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff 142 #define QL_DRIVER_NAME(dip) ddi_driver_name(ddi_get_parent(dip)) 143 144 #define MINOR_NODE_FLAG 8 145 146 /* 147 * Host adapter default definitions. 148 */ 149 150 /* Timeout timer counts in seconds (must greater than 1 second). */ 151 #define USEC_PER_TICK drv_hztousec(1) 152 #define TICKS_PER_SEC drv_usectohz(1000000) 153 #define QL_ONE_SEC_DELAY 1000000 154 #define QL_ONE_MSEC_DELAY 1000 155 #define TX_TIMEOUT 3*TICKS_PER_SEC 156 /* 157 * DMA attributes definitions. 158 */ 159 #define QL_DMA_LOW_ADDRESS (uint64_t)0 160 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffffull 161 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff 162 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8 163 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3 164 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64 165 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6 166 #define QL_DMA_BURSTSIZES 0xfff 167 #define QL_DMA_MIN_XFER_SIZE 1 168 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff 169 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff 170 #define QL_DMA_GRANULARITY 1 171 #define QL_DMA_XFER_FLAGS 0 172 #define QL_MAX_COOKIES 16 173 174 /* 175 * ISP PCI Configuration. 176 */ 177 #define QL_INTR_INTERVAL 128 /* default interrupt interval 128us */ 178 #define QL_INTR_PKTS 8 /* default packet count threshold 8us */ 179 180 /* GLD */ 181 #define QL_STREAM_OPS(dev_ops, attach, detach) \ 182 DDI_DEFINE_STREAM_OPS(dev_ops, nulldev, nulldev, attach, detach, \ 183 nodev, NULL, D_MP, NULL, ql_quiesce) 184 185 #define QL_GET_DEV(dip) ((qlge_t *)(ddi_get_driver_private(dip))) 186 #define RESUME_TX(tx_ring) mac_tx_update(tx_ring->qlge->mh); 187 #define RX_UPSTREAM(rx_ring, mp) mac_rx(rx_ring->qlge->mh, \ 188 rx_ring->qlge->handle, mp); 189 190 /* GLD DMA */ 191 extern ddi_device_acc_attr_t ql_dev_acc_attr; 192 extern ddi_device_acc_attr_t ql_desc_acc_attr; 193 extern ddi_device_acc_attr_t ql_buf_acc_attr; 194 195 struct dma_info { 196 void *vaddr; 197 ddi_dma_handle_t dma_handle; 198 ddi_acc_handle_t acc_handle; 199 uint64_t dma_addr; 200 size_t mem_len; /* allocated size */ 201 offset_t offset; /* relative to handle */ 202 }; 203 204 /* 205 * Sync a DMA area described by a dma_info 206 */ 207 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle, \ 208 (area).offset, (area).mem_len, (flag))) 209 210 /* 211 * Find the (kernel virtual) address of block of memory 212 * described by a dma_info 213 */ 214 #define DMA_VPTR(area) ((area).vaddr) 215 216 /* 217 * Zero a block of memory described by a dma_info 218 */ 219 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).mem_len) 220 221 #define MAX_SG_ELEMENTS 16 222 #define QL_MAX_TX_DMA_HANDLES MAX_SG_ELEMENTS 223 #define TOTAL_SG_ELEMENTS (MAX_SG_ELEMENTS + TX_DESC_PER_IOCB) 224 225 /* 226 * ISP PCI Configuration. 227 */ 228 229 /* Initialize steps */ 230 #define INIT_SOFTSTATE_ALLOC BIT_0 231 #define INIT_REGS_SETUP BIT_1 232 #define INIT_DOORBELL_REGS_SETUP BIT_2 233 #define INIT_MAC_ALLOC BIT_3 234 #define INIT_PCI_CONFIG_SETUP BIT_4 235 #define INIT_SETUP_RINGS BIT_5 236 #define INIT_MEMORY_ALLOC BIT_6 237 #define INIT_INTR_ALLOC BIT_7 238 #define INIT_ADD_INTERRUPT BIT_8 239 #define INIT_LOCKS_CREATED BIT_9 240 #define INIT_ADD_SOFT_INTERRUPT BIT_10 241 #define INIT_MUTEX BIT_11 242 #define ADAPTER_INIT BIT_12 243 #define INIT_MAC_REGISTERED BIT_13 244 #define INIT_KSTATS BIT_14 245 #define INIT_ADAPTER_UP BIT_15 246 #define INIT_ALLOC_RX_BUF BIT_16 247 #define INIT_INTR_ENABLED BIT_17 248 249 250 #define LS_64BITS(x) (uint32_t)(0xffffffff & ((uint64_t)x)) 251 #define MS_64BITS(x) (uint32_t)(0xffffffff & (((uint64_t)x)>>16>>16)) 252 253 typedef uint64_t dma_addr_t; 254 extern int ql_quiesce(dev_info_t *dip); 255 256 /* 257 * LSO can support up to 65536 bytes of data, but can not be sent in one IOCB 258 * which only has 8 TX OALs, additional OALs must be applied separately. 259 */ 260 #define QL_LSO_MAX 65536 /* Maximum supported LSO data Length */ 261 262 enum tx_mode_t { 263 USE_DMA, 264 USE_COPY 265 }; 266 267 #define QL_MAX_COPY_LENGTH 256 268 269 #define MAX_FRAGMENTS_IN_IOCB 7 270 271 #ifndef VLAN_ID_MASK 272 #define VLAN_ID_MASK 0x0fffu 273 #endif 274 #ifndef VLAN_TAGSZ 275 #define VLAN_TAGSZ 4 276 #endif 277 278 #ifndef ETHERTYPE_VLAN 279 #define ETHERTYPE_VLAN 0x8100 280 #endif 281 282 #ifndef MBLKL 283 #define MBLKL(mp) ((uintptr_t)(mp)->b_wptr - (uintptr_t)(mp)->b_rptr) 284 #endif 285 /* 286 * Checksum Offload 287 */ 288 #define TCP_CKSUM_OFFSET 16 289 #define UDP_CKSUM_OFFSET 6 290 #define IPPROTO_IPv6OVERv4 41 291 292 /* 293 * Driver must be in one of these states 294 */ 295 enum mac_state { 296 QL_MAC_INIT, /* in the initialization stage */ 297 QL_MAC_ATTACHED, /* driver attached */ 298 QL_MAC_STARTED, /* interrupt enabled, driver is ready */ 299 QL_MAC_BRINGDOWN, /* in the bring down process */ 300 QL_MAC_STOPPED, /* stoped, no more interrupts */ 301 QL_MAC_DETACH, /* to be detached */ 302 QL_MAC_SUSPENDED 303 }; 304 305 /* 306 * Soft Request Flag 307 */ 308 #define NEED_HW_RESET BIT_0 /* need hardware reset */ 309 #define NEED_MPI_RESET BIT_1 /* need MPI RISC reset */ 310 311 /* 312 * (Internal) return values from ioctl subroutines 313 */ 314 enum ioc_reply { 315 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 316 IOC_DONE, /* OK, reply sent */ 317 IOC_ACK, /* OK, just send ACK */ 318 IOC_REPLY, /* OK, just send reply */ 319 IOC_RESTART_ACK, /* OK, restart & ACK */ 320 IOC_RESTART_REPLY /* OK, restart & reply */ 321 }; 322 323 /* 324 * Link Speed,in Mbps 325 */ 326 #define SPEED_10 10 327 #define SPEED_100 100 328 #define SPEED_1000 1000 329 #define SPEED_10G 10000 330 331 /* 332 * Multicast List 333 */ 334 typedef struct { 335 struct ether_addr addr; 336 unsigned char reserved[2]; 337 } ql_multicast_addr; 338 339 #define MAX_MULTICAST_LIST_SIZE 128 340 341 typedef struct { 342 struct ether_addr addr; /* in canonical form */ 343 boolean_t set; /* B_TRUE => valid */ 344 } qlge_mac_addr_t; 345 346 #define MAX_UNICAST_LIST_SIZE 128 347 348 /* 349 * Device kstate structure. 350 */ 351 enum { 352 QL_KSTAT_CHIP = 0, 353 QL_KSTAT_LINK, 354 QL_KSTAT_REG, 355 QL_KSTAT_COUNT 356 }; 357 358 /* 359 * Register Bit Set/Reset 360 */ 361 enum { 362 BIT_SET = 0, 363 BIT_RESET 364 }; 365 366 /* 367 * Flash Image Search State 368 */ 369 enum { STOP_SEARCH, /* Image address bad, no more search */ 370 CONTINUE_SEARCH, /* Image address ok, continue search */ 371 LAST_IMAGE_FOUND /* Found last image and FLTDS address */ 372 }; 373 374 /* 375 * Loop Back Modes 376 */ 377 enum { QLGE_LOOP_NONE, 378 QLGE_LOOP_INTERNAL_PARALLEL, 379 QLGE_LOOP_INTERNAL_SERIAL, 380 QLGE_LOOP_EXTERNAL_PHY 381 }; 382 383 /* for soft state routine */ 384 typedef struct { 385 offset_t index; 386 char *name; 387 } ql_ksindex_t; 388 389 struct bq_desc { 390 struct dma_info bd_dma; 391 struct bq_desc *next; 392 struct rx_ring *rx_ring; 393 mblk_t *mp; 394 frtn_t rx_recycle; /* recycle function - called after mp */ 395 /* is to be freed by OS */ 396 uint16_t index; 397 uint16_t free_buf; /* Set to indicate the buffer is */ 398 /* being freed, new one should not */ 399 /* be allocated */ 400 uint32_t upl_inuse; /* buffer in use by upper layers */ 401 }; 402 403 #define VM_PAGE_SIZE 4096 404 405 #define QLGE_POLL_ALL -1 406 407 #define SMALL_BUFFER_SIZE 512 408 #define LARGE_BUFFER_SIZE 4096 409 410 #define MAX_TX_WAIT_COUNT 1000 411 #define MAX_RX_WAIT_COUNT 25 /* 25 second */ 412 413 #define MIN_BUFFERS_ARM_COUNT 16 414 #define MIN_BUFFERS_FREE_COUNT 32 /* If free buffer count go over this */ 415 /* value, arm the chip */ 416 /* if less than 16 free lrg buf nodes in the free list, then */ 417 /* rx has to use copy method to send packets upstream */ 418 #define RX_COPY_MODE_THRESHOLD (MIN_BUFFERS_ARM_COUNT/4) 419 /* if there are more than TX_STOP_THRESHOLD free tx buffers, try to send it */ 420 #define TX_STOP_THRESHOLD 16 421 #define TX_RESUME_THRESHOLD 8 422 423 struct tx_ring_desc { 424 struct ob_mac_iocb_req *queue_entry; /* tx descriptor of this */ 425 struct dma_info dma_mem_area; /* tx buffer */ 426 ddi_dma_handle_t tx_dma_handle[QL_MAX_TX_DMA_HANDLES]; 427 int tx_dma_handle_used; 428 enum tx_mode_t tx_type; /* map mode or copy mode */ 429 mblk_t *mp; /* requested sending packet */ 430 uint32_t index; 431 caddr_t copy_buffer; 432 uint64_t copy_buffer_dma_addr; 433 struct dma_info oal_dma; /* oal is premapped */ 434 uint64_t oal_dma_addr; /* oal dma address premapped */ 435 uint32_t tx_bytes; 436 void *oal; 437 }; 438 439 struct tx_ring { 440 struct qlge *qlge; 441 struct dma_info wqicb_dma; 442 uint16_t cq_id; /* completion (rx) queue for */ 443 /* tx completions */ 444 uint8_t wq_id; 445 uint32_t wq_size; 446 uint32_t wq_len; 447 kmutex_t tx_lock; 448 struct dma_info wq_dma; 449 volatile uint32_t tx_free_count; 450 uint32_t tx_mode; 451 boolean_t queue_stopped; /* Tx no resource */ 452 uint32_t *prod_idx_db_reg; 453 uint16_t prod_idx; 454 uint32_t *valid_db_reg; /* PCI doorbell mem area + 4 */ 455 struct tx_ring_desc *wq_desc; 456 /* shadow copy of consumer idx */ 457 uint32_t *cnsmr_idx_sh_reg; 458 /* dma-shadow copy consumer */ 459 uint64_t cnsmr_idx_sh_reg_dma; 460 uint32_t defer; /* tx no resource */ 461 uint64_t obytes; 462 uint64_t opackets; 463 uint32_t errxmt; 464 uint64_t brdcstxmt; 465 uint64_t multixmt; 466 uint64_t tx_fail_dma_bind; 467 uint64_t tx_no_dma_handle; 468 uint64_t tx_no_dma_cookie; 469 470 enum mac_state mac_flags; 471 }; 472 473 struct bq_element { 474 uint32_t addr_lo; 475 uint32_t addr_hi; 476 }; 477 478 /* 479 * Type of inbound queue. 480 */ 481 enum { 482 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */ 483 TX_Q = 3, /* Handles outbound completions. */ 484 RX_Q = 4, /* Handles inbound completions. */ 485 }; 486 487 struct rx_ring { 488 struct dma_info cqicb_dma; 489 490 /* GLD required flags */ 491 uint64_t ring_gen_num; 492 /* statistics */ 493 uint64_t rx_packets; 494 uint64_t rx_bytes; 495 uint32_t frame_too_long; 496 uint32_t frame_too_short; 497 uint32_t fcs_err; 498 uint32_t rx_packets_dropped_no_buffer; 499 uint32_t rx_pkt_dropped_mac_unenabled; 500 volatile uint32_t rx_indicate; 501 502 /* miscellaneous */ 503 int type; /* DEFAULT_Q, TX_Q, RX_Q */ 504 kmutex_t rx_lock; 505 uint32_t irq; 506 struct qlge *qlge; 507 uint32_t cpu; /* Which CPU this should run on. */ 508 enum mac_state mac_flags; 509 /* completion queue */ 510 struct dma_info cq_dma; /* virtual addr and phy addr */ 511 uint32_t cq_size; 512 uint32_t cq_len; 513 uint16_t cq_id; 514 volatile uint32_t *prod_idx_sh_reg; /* Shadowed prod reg */ 515 uint64_t prod_idx_sh_reg_dma; /* Physical address */ 516 uint32_t *cnsmr_idx_db_reg; /* PCI db mem area 0 */ 517 uint32_t cnsmr_idx; /* current sw idx */ 518 struct net_rsp_iocb *curr_entry; /* next entry on queue */ 519 uint32_t *valid_db_reg; /* PCI doorbell mem area + 4 */ 520 521 /* large buffer queue */ 522 uint32_t lbq_len; /* entry count */ 523 uint32_t lbq_size; /* size in bytes */ 524 uint32_t lbq_buf_size; 525 struct dma_info lbq_dma; /* lbq dma info */ 526 uint64_t *lbq_base_indirect; 527 uint64_t lbq_base_indirect_dma; 528 kmutex_t lbq_lock; 529 struct bq_desc **lbuf_in_use; 530 volatile uint32_t lbuf_in_use_count; 531 struct bq_desc **lbuf_free; 532 volatile uint32_t lbuf_free_count; /* free lbuf desc cnt */ 533 uint32_t *lbq_prod_idx_db_reg; /* PCI db mem area+0x18 */ 534 uint32_t lbq_prod_idx; /* current sw prod idx */ 535 uint32_t lbq_curr_idx; /* next entry we expect */ 536 uint32_t lbq_free_tail; /* free tail */ 537 uint32_t lbq_free_head; /* free head */ 538 uint32_t lbq_use_tail; /* inuse tail */ 539 uint32_t lbq_use_head; /* inuse head */ 540 541 struct bq_desc *lbq_desc; 542 543 /* small buffer queue */ 544 uint32_t sbq_len; /* entry count */ 545 uint32_t sbq_size; /* size in bytes of queue */ 546 uint32_t sbq_buf_size; 547 struct dma_info sbq_dma; /* sbq dma info */ 548 uint64_t *sbq_base_indirect; 549 uint64_t sbq_base_indirect_dma; 550 kmutex_t sbq_lock; 551 struct bq_desc **sbuf_in_use; 552 volatile uint32_t sbuf_in_use_count; 553 struct bq_desc **sbuf_free; 554 volatile uint32_t sbuf_free_count; /* free buffer desc cnt */ 555 uint32_t *sbq_prod_idx_db_reg; /* PCI db mem area+0x1c */ 556 uint32_t sbq_prod_idx; /* current sw prod idx */ 557 uint32_t sbq_curr_idx; /* next entry we expect */ 558 uint32_t sbq_free_tail; /* free tail */ 559 uint32_t sbq_free_head; /* free head */ 560 uint32_t sbq_use_tail; /* inuse tail */ 561 uint32_t sbq_use_head; /* inuse head */ 562 struct bq_desc *sbq_desc; 563 /* for test purpose */ 564 uint32_t rx_failed_sbq_allocs; 565 uint32_t rx_failed_lbq_allocs; 566 uint32_t sbuf_copy_count; 567 uint32_t lbuf_copy_count; 568 569 }; 570 571 struct intr_ctx { 572 struct qlge *qlge; 573 uint32_t intr; 574 uint32_t hooked; 575 uint32_t intr_en_mask; 576 uint32_t intr_dis_mask; 577 uint32_t intr_read_mask; 578 /* 579 * It's incremented for 580 * each irq handler that is scheduled. 581 * When each handler finishes it 582 * decrements irq_cnt and enables 583 * interrupts if it's zero. 584 */ 585 uint32_t irq_cnt; 586 uint_t (*handler)(caddr_t, caddr_t); 587 }; 588 589 struct tx_buf_desc { 590 uint64_t addr; 591 uint32_t len; 592 #define TX_DESC_LEN_MASK 0x000fffff 593 #define TX_DESC_C 0x40000000 594 #define TX_DESC_E 0x80000000 595 }; 596 597 typedef struct qlge { 598 /* 599 * Solaris adapter configuration data 600 */ 601 dev_info_t *dip; 602 int instance; 603 ddi_acc_handle_t dev_handle; 604 caddr_t iobase; 605 ddi_acc_handle_t dev_doorbell_reg_handle; 606 caddr_t doorbell_reg_iobase; 607 pci_cfg_t pci_cfg; 608 ddi_acc_handle_t pci_handle; 609 uint32_t page_size; 610 uint32_t sequence; 611 struct intr_ctx intr_ctx[MAX_RX_RINGS]; 612 struct dma_info ricb_dma; 613 614 enum mac_state mac_flags; 615 616 volatile uint32_t cfg_flags; 617 618 #define CFG_JUMBLE_PACKET BIT_1 619 #define CFG_RX_COPY_MODE BIT_2 620 #define CFG_SUPPORT_MULTICAST BIT_3 621 #define CFG_HW_UNABLE_PSEUDO_HDR_CKSUM BIT_4 622 #define CFG_CKSUM_HEADER_IPv4 BIT_5 623 #define CFG_CKSUM_PARTIAL BIT_6 624 #define CFG_CKSUM_FULL_IPv4 BIT_7 625 #define CFG_CKSUM_FULL_IPv6 BIT_8 626 #define CFG_LSO BIT_9 627 #define CFG_SUPPORT_SCATTER_GATHER BIT_10 628 #define CFG_ENABLE_SPLIT_HEADER BIT_11 629 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15 630 uint32_t chksum_cap; 631 volatile uint32_t flags; 632 #define CFG_CHIP_8100 BIT_16 633 634 #define CFG_IST(qlge, cfgflags) (qlge->cfg_flags & cfgflags) 635 636 /* For Shadow Registers, used by adapter to write to host memory */ 637 struct dma_info host_copy_shadow_dma_attr; 638 /* 639 * Extra 2x8 bytes memory saving large/small buf queue base address 640 * for each CQICB and read by chip, new request since 8100 641 */ 642 struct dma_info buf_q_ptr_base_addr_dma_attr; 643 /* 644 * Debugging 645 */ 646 uint32_t ql_dbgprnt; 647 /* 648 * GLD 649 */ 650 mac_handle_t mh; 651 mac_resource_handle_t handle; 652 ql_stats_t stats; 653 kstat_t *ql_kstats[QL_KSTAT_COUNT]; 654 /* 655 * mutex 656 */ 657 kmutex_t gen_mutex; /* general adapter mutex */ 658 kmutex_t hw_mutex; /* common hw(nvram)access */ 659 660 /* 661 * Generic timer 662 */ 663 timeout_id_t ql_timer_timeout_id; 664 clock_t ql_timer_ticks; 665 666 /* 667 * Interrupt 668 */ 669 int intr_type; 670 /* for legacy interrupt */ 671 ddi_iblock_cookie_t iblock_cookie; 672 /* for MSI and Fixed interrupts */ 673 ddi_intr_handle_t *htable; /* For array of interrupts */ 674 int intr_cnt; /* # of intrs actually allocated */ 675 uint_t intr_pri; /* Interrupt priority */ 676 int intr_cap; /* Interrupt capabilities */ 677 size_t intr_size; /* size of the allocated */ 678 /* interrupt handlers */ 679 /* Power management context. */ 680 uint8_t power_level; 681 #define LOW_POWER_LEVEL (BIT_1 | BIT_0) 682 #define MAX_POWER_LEVEL 0 683 684 /* 685 * General NIC 686 */ 687 uint32_t xgmac_sem_mask; 688 uint32_t xgmac_sem_bits; 689 uint32_t func_number; 690 uint32_t fn0_net; /* network function 0 port */ 691 uint32_t fn1_net; /* network function 1 port */ 692 693 uint32_t mtu; 694 uint32_t port_link_state; 695 uint32_t speed; 696 uint16_t link_type; 697 uint32_t duplex; 698 uint32_t pause; /* flow-control mode */ 699 uint32_t loop_back_mode; 700 uint32_t lso_enable; 701 /* 702 * PCI status 703 */ 704 uint16_t vendor_id; 705 uint16_t device_id; 706 707 /* 708 * Multicast list 709 */ 710 uint32_t multicast_list_count; 711 ql_multicast_addr multicast_list[MAX_MULTICAST_LIST_SIZE]; 712 boolean_t multicast_promisc; 713 /* 714 * MAC address information 715 */ 716 struct ether_addr dev_addr; /* ethernet address read from nvram */ 717 qlge_mac_addr_t unicst_addr[MAX_UNICAST_LIST_SIZE]; 718 uint32_t unicst_total; /* total unicst addresses */ 719 uint32_t unicst_avail; 720 /* 721 * Soft Interrupt handlers 722 */ 723 /* soft interrupt handle for MPI interrupt */ 724 ddi_softint_handle_t mpi_event_intr_hdl; 725 /* soft interrupt handle for asic reset */ 726 ddi_softint_handle_t asic_reset_intr_hdl; 727 /* soft interrupt handle for mpi reset */ 728 ddi_softint_handle_t mpi_reset_intr_hdl; 729 /* 730 * IOCTL 731 */ 732 /* new ioctl admin flags to work around the 1024 max data copy in&out */ 733 caddr_t ioctl_buf_ptr; 734 uint32_t ioctl_buf_lenth; 735 uint16_t expected_trans_times; 736 uint32_t ioctl_total_length; 737 uint32_t ioctl_transferred_bytes; 738 ql_mpi_coredump_t ql_mpi_coredump; 739 /* 740 * Mailbox lock and flags 741 */ 742 boolean_t fw_init_complete; 743 kmutex_t mbx_mutex; 744 boolean_t mbx_wait_completion; 745 kcondvar_t cv_mbx_intr; 746 mbx_data_t received_mbx_cmds; 747 uint_t max_read_mbx; 748 firmware_version_info_t fw_version_info; 749 phy_firmware_version_info_t phy_version_info; 750 port_cfg_info_t port_cfg_info; 751 struct dma_info ioctl_buf_dma_attr; 752 753 /* 754 * Flash 755 */ 756 uint32_t flash_fltds_addr; 757 uint32_t flash_flt_fdt_index; 758 uint32_t flash_fdt_addr; 759 uint32_t flash_fdt_size; 760 uint32_t flash_flt_nic_config_table_index; 761 uint32_t flash_nic_config_table_addr; 762 uint32_t flash_nic_config_table_size; 763 uint32_t flash_vpd_addr; 764 ql_flash_info_t flash_info; 765 ql_fltds_t fltds; 766 ql_flt_t flt; 767 uint16_t flash_len; /* size of Flash memory */ 768 ql_nic_config_t nic_config; 769 flash_desc_t fdesc; 770 /* 771 * TX / RX 772 */ 773 clock_t last_tx_time; 774 boolean_t rx_copy; 775 uint16_t rx_coalesce_usecs; 776 uint16_t rx_max_coalesced_frames; 777 uint16_t tx_coalesce_usecs; 778 uint16_t tx_max_coalesced_frames; 779 uint32_t payload_copy_thresh; 780 781 uint32_t xg_sem_mask; 782 783 uint32_t ip_hdr_offset; 784 uint32_t selected_tx_ring; 785 786 struct rx_ring rx_ring[MAX_RX_RINGS]; 787 struct tx_ring tx_ring[MAX_TX_RINGS]; 788 uint32_t rx_polls[MAX_RX_RINGS]; 789 uint32_t rx_interrupts[MAX_RX_RINGS]; 790 791 int tx_ring_size; 792 int rx_ring_size; 793 uint32_t rx_ring_count; 794 uint32_t rss_ring_count; 795 uint32_t tx_ring_first_cq_id; 796 uint32_t tx_ring_count; 797 #ifdef QLGE_TRACK_BUFFER_USAGE 798 /* Count no of times the buffers fell below 32 */ 799 uint32_t rx_sb_low_count[MAX_RX_RINGS]; 800 uint32_t rx_lb_low_count[MAX_RX_RINGS]; 801 uint32_t cq_low_count[MAX_RX_RINGS]; 802 #endif 803 } qlge_t; 804 805 806 /* 807 * Reconfiguring the network devices requires the net_config privilege 808 * in Solaris 10+. 809 */ 810 extern int secpolicy_net_config(const cred_t *, boolean_t); 811 812 /* 813 * Global Function Prototypes in qlge_dbg.c source file. 814 */ 815 extern int ql_fw_dump(qlge_t *); 816 extern uint8_t ql_get8(qlge_t *, uint32_t); 817 extern uint16_t ql_get16(qlge_t *, uint32_t); 818 extern uint32_t ql_get32(qlge_t *, uint32_t); 819 extern void ql_put8(qlge_t *, uint32_t, uint8_t); 820 extern void ql_put16(qlge_t *, uint32_t, uint16_t); 821 extern void ql_put32(qlge_t *, uint32_t, uint32_t); 822 extern uint32_t ql_read_reg(qlge_t *, uint32_t); 823 extern void ql_write_reg(qlge_t *, uint32_t, uint32_t); 824 extern void ql_dump_all_contrl_regs(qlge_t *); 825 extern int ql_wait_reg_bit(qlge_t *, uint32_t, uint32_t, int, uint32_t); 826 extern void ql_dump_pci_config(qlge_t *); 827 extern void ql_dump_host_pci_regs(qlge_t *); 828 extern void ql_dump_req_pkt(qlge_t *, struct ob_mac_iocb_req *, void *, int); 829 extern void ql_dump_cqicb(qlge_t *, struct cqicb_t *); 830 extern void ql_dump_wqicb(qlge_t *, struct wqicb_t *); 831 extern void ql_gld3_init(qlge_t *, mac_register_t *); 832 enum ioc_reply ql_chip_ioctl(qlge_t *, queue_t *, mblk_t *); 833 enum ioc_reply ql_loop_ioctl(qlge_t *, queue_t *, mblk_t *, struct iocblk *); 834 extern int ql_8xxx_binary_core_dump(qlge_t *, ql_mpi_coredump_t *); 835 /* 836 * Global Data in qlge.c source file. 837 */ 838 extern void qlge_delay(clock_t usecs); 839 extern int ql_sem_spinlock(qlge_t *, uint32_t); 840 extern void ql_sem_unlock(qlge_t *, uint32_t); 841 extern int ql_sem_lock(qlge_t *, uint32_t, uint32_t); 842 extern int ql_init_misc_registers(qlge_t *); 843 extern int ql_init_mem_resources(qlge_t *); 844 extern int ql_do_start(qlge_t *); 845 extern int ql_do_stop(qlge_t *); 846 extern int ql_add_to_multicast_list(qlge_t *, uint8_t *ep); 847 extern int ql_remove_from_multicast_list(qlge_t *, uint8_t *); 848 extern void ql_set_promiscuous(qlge_t *, int); 849 extern void ql_get_hw_stats(qlge_t *); 850 extern int ql_send_common(struct tx_ring *, mblk_t *); 851 extern void ql_wake_asic_reset_soft_intr(qlge_t *); 852 extern void ql_write_doorbell_reg(qlge_t *, uint32_t *, uint32_t); 853 extern uint32_t ql_read_doorbell_reg(qlge_t *, uint32_t *); 854 extern int ql_set_mac_addr_reg(qlge_t *, uint8_t *, uint32_t, uint16_t); 855 extern int ql_read_xgmac_reg(qlge_t *, uint32_t, uint32_t *); 856 extern void ql_enable_completion_interrupt(qlge_t *, uint32_t); 857 extern mblk_t *ql_ring_rx_poll(void *, int); 858 extern void ql_disable_completion_interrupt(qlge_t *qlge, uint32_t intr); 859 extern mblk_t *ql_ring_tx(void *arg, mblk_t *mp); 860 extern void ql_atomic_set_32(volatile uint32_t *target, uint32_t newval); 861 extern uint32_t ql_atomic_read_32(volatile uint32_t *target); 862 extern void ql_restart_timer(qlge_t *qlge); 863 /* 864 * Global Function Prototypes in qlge_flash.c source file. 865 */ 866 extern int ql_sem_flash_lock(qlge_t *); 867 extern void ql_sem_flash_unlock(qlge_t *); 868 extern int qlge_load_flash(qlge_t *, uint8_t *, uint32_t, uint32_t); 869 extern int qlge_dump_fcode(qlge_t *, uint8_t *, uint32_t, uint32_t); 870 extern int ql_flash_vpd(qlge_t *qlge, uint8_t *buf); 871 extern int ql_get_flash_params(qlge_t *qlge); 872 /* 873 * Global Function Prototypes in qlge_mpi.c source file. 874 */ 875 extern void ql_do_mpi_intr(qlge_t *qlge); 876 extern int ql_reset_mpi_risc(qlge_t *); 877 extern int ql_get_fw_state(qlge_t *, uint32_t *); 878 extern int qlge_get_link_status(qlge_t *, struct qlnic_link_status_info *); 879 extern int ql_mbx_test(qlge_t *qlge); 880 extern int ql_mbx_test2(qlge_t *qlge); 881 extern int ql_get_port_cfg(qlge_t *qlge); 882 extern int ql_set_port_cfg(qlge_t *qlge); 883 extern int ql_get_LED_config(qlge_t *); 884 extern int ql_dump_sfp(qlge_t *, void *bp, int mode); 885 extern int ql_set_IDC_Req(qlge_t *, uint8_t dest_functions, uint8_t timeout); 886 extern void ql_write_flash_test(qlge_t *qlge, uint32_t testAddr); 887 extern void ql_write_flash_test2(qlge_t *qlge, uint32_t testAddr); 888 extern int ql_get_firmware_version(qlge_t *, 889 struct qlnic_mpi_version_info *); 890 extern int ql_read_processor_data(qlge_t *, uint32_t, uint32_t *); 891 extern int ql_write_processor_data(qlge_t *, uint32_t, uint32_t); 892 extern int ql_read_risc_ram(qlge_t *, uint32_t, uint64_t, uint32_t); 893 extern int ql_trigger_system_error_event(qlge_t *qlge); 894 895 extern void ql_core_dump(qlge_t *); 896 extern void ql_dump_crash_record(qlge_t *); 897 extern void ql_dump_buf(char *, uint8_t *, uint8_t, uint32_t); 898 extern void ql_printf(const char *, ...); 899 900 #ifdef __cplusplus 901 } 902 #endif 903 904 #endif /* _QLGE_H */ 905