xref: /illumos-gate/usr/src/uts/common/io/xge/drv/xge_osdep.h (revision 92a0208178405fef708b0283ffcaa02fbc3468ff)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  *  Copyright (c) 2002-2005 Neterion, Inc.
29  *  All right Reserved.
30  *
31  *  FileName :    xge_osdep.h
32  *
33  *  Description:  OSPAL - Solaris
34  *
35  */
36 
37 #ifndef _SYS_XGE_OSDEP_H
38 #define	_SYS_XGE_OSDEP_H
39 
40 #pragma ident	"%Z%%M%	%I%	%E% SMI"
41 
42 #include <sys/ddi.h>
43 #include <sys/sunddi.h>
44 #include <sys/varargs.h>
45 #include <sys/atomic.h>
46 #include <sys/policy.h>
47 #include <sys/int_fmtio.h>
48 #include <sys/thread.h>
49 #include <sys/cpuvar.h>
50 
51 #include <inet/common.h>
52 #include <inet/ip.h>
53 #include <inet/mi.h>
54 #include <inet/nd.h>
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
60 /* ------------------------- includes and defines ------------------------- */
61 
62 #define	XGE_HAL_TX_MULTI_POST_IRQ	1
63 #define	XGE_HAL_TX_MULTI_RESERVE_IRQ	1
64 #define	XGE_HAL_TX_MULTI_FREE_IRQ	1
65 #define	XGE_HAL_DMA_DTR_CONSISTENT	1
66 #define	XGE_HAL_DMA_STATS_STREAMING	1
67 
68 #if defined(__sparc)
69 #define	XGE_OS_DMA_REQUIRES_SYNC	1
70 #endif
71 
72 #define	XGE_HAL_ALIGN_XMIT		1
73 
74 #ifdef _BIG_ENDIAN
75 #define	XGE_OS_HOST_BIG_ENDIAN		1
76 #else
77 #define	XGE_OS_HOST_LITTLE_ENDIAN	1
78 #endif
79 
80 #if defined(__sparc)
81 #define	XGE_OS_HOST_PAGE_SIZE		8192
82 #else
83 #define	XGE_OS_HOST_PAGE_SIZE		4096
84 #endif
85 
86 #if defined(_LP64)
87 #define	XGE_OS_PLATFORM_64BIT		1
88 #else
89 #define	XGE_OS_PLATFORM_32BIT		1
90 #endif
91 
92 #define	XGE_OS_HAS_SNPRINTF		1
93 
94 /* LRO defines */
95 #define	XGE_LL_IP_FAST_CSUM(hdr, len)	0 /* ip_ocsum(hdr, len>>1, 0); */
96 
97 /* ---------------------- fixed size primitive types ----------------------- */
98 
99 #define	u8			uint8_t
100 #define	u16			uint16_t
101 #define	u32			uint32_t
102 #define	u64			uint64_t
103 typedef	u64			dma_addr_t;
104 #define	ulong_t			ulong_t
105 #define	ptrdiff_t		ptrdiff_t
106 typedef	kmutex_t		spinlock_t;
107 typedef dev_info_t		*pci_dev_h;
108 typedef ddi_acc_handle_t	pci_reg_h;
109 typedef ddi_acc_handle_t	pci_cfg_h;
110 typedef uint_t			pci_irq_h;
111 typedef ddi_dma_handle_t	pci_dma_h;
112 typedef ddi_acc_handle_t	pci_dma_acc_h;
113 
114 /* LRO types */
115 #define	OS_NETSTACK_BUF		mblk_t *
116 #define	OS_LL_HEADER		uint8_t *
117 #define	OS_IP_HEADER		uint8_t *
118 #define	OS_TL_HEADER		uint8_t *
119 
120 /* -------------------------- "libc" functionality ------------------------- */
121 
122 #define	xge_os_strlcpy			(void) strlcpy
123 #define	xge_os_strlen			strlen
124 #define	xge_os_snprintf			snprintf
125 #define	xge_os_memzero(addr, size)	bzero(addr, size)
126 #define	xge_os_memcpy(dst, src, size)	bcopy(src, dst, size)
127 #define	xge_os_memcmp(src1, src2, size)	bcmp(src1, src2, size)
128 #define	xge_os_ntohl			ntohl
129 #define	xge_os_htons			htons
130 #define	xge_os_ntohs			ntohs
131 
132 #ifdef __GNUC__
133 #define	xge_os_printf(fmt...)		cmn_err(CE_CONT, fmt)
134 #define	xge_os_sprintf(buf, fmt...)	strlen(sprintf(buf, fmt))
135 #else
136 #define	xge_os_vaprintf(fmt) { \
137 	va_list va; \
138 	va_start(va, fmt); \
139 	vcmn_err(CE_CONT, fmt, va); \
140 	va_end(va); \
141 }
142 
143 static inline void xge_os_printf(char *fmt, ...) {
144 	xge_os_vaprintf(fmt);
145 }
146 
147 #define	xge_os_vasprintf(buf, fmt) { \
148 	va_list va; \
149 	va_start(va, fmt); \
150 	(void) vsprintf(buf, fmt, va); \
151 	va_end(va); \
152 }
153 
154 static inline int xge_os_sprintf(char *buf, char *fmt, ...) {
155 	xge_os_vasprintf(buf, fmt);
156 	return (strlen(buf));
157 }
158 #endif
159 
160 #define	xge_os_timestamp(buf) { \
161 	todinfo_t todinfo = utc_to_tod(ddi_get_time()); \
162 	(void) xge_os_sprintf(buf, "%02d/%02d/%02d.%02d:%02d:%02d: ", \
163 	    todinfo.tod_day, todinfo.tod_month, \
164 	    (1970 + todinfo.tod_year - 70), \
165 	    todinfo.tod_hour, todinfo.tod_min, todinfo.tod_sec); \
166 }
167 
168 #define	xge_os_println			xge_os_printf
169 
170 /* -------------------- synchronization primitives ------------------------- */
171 
172 #define	xge_os_spin_lock_init(lockp, ctxh) \
173 	mutex_init(lockp, NULL, MUTEX_DRIVER, NULL)
174 #define	xge_os_spin_lock_init_irq(lockp, irqh) \
175 	mutex_init(lockp, NULL, MUTEX_DRIVER, DDI_INTR_PRI(irqh))
176 #define	xge_os_spin_lock_destroy(lockp, cthx) \
177 	(cthx = cthx, mutex_destroy(lockp))
178 #define	xge_os_spin_lock_destroy_irq(lockp, cthx) \
179 	(cthx = cthx, mutex_destroy(lockp))
180 #define	xge_os_spin_lock(lockp)			mutex_enter(lockp)
181 #define	xge_os_spin_unlock(lockp)		mutex_exit(lockp)
182 #define	xge_os_spin_lock_irq(lockp, flags) (flags = flags, mutex_enter(lockp))
183 #define	xge_os_spin_unlock_irq(lockp, flags)	mutex_exit(lockp)
184 
185 /* x86 arch will never re-order writes, Sparc can */
186 #define	xge_os_wmb()				membar_producer()
187 
188 #define	xge_os_udelay(us)			drv_usecwait(us)
189 #define	xge_os_mdelay(ms)			drv_usecwait(ms * 1000)
190 
191 #define	xge_os_cmpxchg(targetp, cmp, newval)		\
192 	sizeof (*(targetp)) == 4 ?			\
193 	cas32((uint32_t *)targetp, cmp, newval) :	\
194 	cas64((uint64_t *)targetp, cmp, newval)
195 
196 /* ------------------------- misc primitives ------------------------------- */
197 
198 #define	xge_os_unlikely(x)		(x)
199 #define	xge_os_prefetch(a)		(a = a)
200 #define	xge_os_prefetchw
201 #ifdef __GNUC__
202 #define	xge_os_bug(fmt...)		cmn_err(CE_PANIC, fmt)
203 #else
204 static inline void xge_os_bug(char *fmt, ...) {
205 	va_list ap;
206 
207 	va_start(ap, fmt);
208 	vcmn_err(CE_PANIC, fmt, ap);
209 	va_end(ap);
210 }
211 #endif
212 
213 /* -------------------------- compiler stuffs ------------------------------ */
214 
215 #if defined(__i386)
216 #define	__xge_os_cacheline_size		64 /* L1-cache line size: x86_64 */
217 #else
218 #define	__xge_os_cacheline_size		64 /* L1-cache line size: sparcv9 */
219 #endif
220 
221 #ifdef __GNUC__
222 #define	__xge_os_attr_cacheline_aligned	\
223 	__attribute__((__aligned__(__xge_os_cacheline_size)))
224 #else
225 #define	__xge_os_attr_cacheline_aligned
226 #endif
227 
228 /* ---------------------- memory primitives -------------------------------- */
229 
230 static inline void *__xge_os_malloc(pci_dev_h pdev, unsigned long size,
231     char *file, int line)
232 {
233 	void *vaddr = kmem_alloc(size, KM_SLEEP);
234 
235 	XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line);
236 	return (vaddr);
237 }
238 
239 static inline void xge_os_free(pci_dev_h pdev, const void *vaddr,
240     unsigned long size)
241 {
242 	XGE_OS_MEMORY_CHECK_FREE(vaddr, size);
243 	kmem_free((void*)vaddr, size);
244 }
245 
246 #define	xge_os_malloc(pdev, size) \
247 	__xge_os_malloc(pdev, size, __FILE__, __LINE__)
248 
249 static inline void *__xge_os_dma_malloc(pci_dev_h pdev, unsigned long size,
250     int dma_flags, pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch, char *file,
251     int line)
252 {
253 	void *vaddr;
254 	int ret;
255 	size_t real_size;
256 	extern ddi_device_acc_attr_t *p_xge_dev_attr;
257 	extern struct ddi_dma_attr *p_hal_dma_attr;
258 
259 	ret = ddi_dma_alloc_handle(pdev, p_hal_dma_attr,
260 	    DDI_DMA_DONTWAIT, 0, p_dmah);
261 	if (ret != DDI_SUCCESS) {
262 		return (NULL);
263 	}
264 
265 	ret = ddi_dma_mem_alloc(*p_dmah, size, p_xge_dev_attr,
266 	    (dma_flags & XGE_OS_DMA_CONSISTENT ?
267 	    DDI_DMA_CONSISTENT : DDI_DMA_STREAMING), DDI_DMA_DONTWAIT, 0,
268 	    (caddr_t *)&vaddr, &real_size, p_dma_acch);
269 	if (ret != DDI_SUCCESS) {
270 		ddi_dma_free_handle(p_dmah);
271 		return (NULL);
272 	}
273 
274 	if (size > real_size) {
275 		ddi_dma_mem_free(p_dma_acch);
276 		ddi_dma_free_handle(p_dmah);
277 		return (NULL);
278 	}
279 
280 	XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line);
281 
282 	return (vaddr);
283 }
284 
285 #define	xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch) \
286 	__xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch, \
287 	    __FILE__, __LINE__)
288 
289 static inline void xge_os_dma_free(pci_dev_h pdev, const void *vaddr, int size,
290     pci_dma_acc_h *p_dma_acch, pci_dma_h *p_dmah)
291 {
292 	XGE_OS_MEMORY_CHECK_FREE(vaddr, 0);
293 	ddi_dma_mem_free(p_dma_acch);
294 	ddi_dma_free_handle(p_dmah);
295 }
296 
297 
298 /* --------------------------- pci primitives ------------------------------ */
299 
300 #define	xge_os_pci_read8(pdev, cfgh, where, val)	\
301 	(*(val) = pci_config_get8(cfgh, where))
302 
303 #define	xge_os_pci_write8(pdev, cfgh, where, val)	\
304 	pci_config_put8(cfgh, where, val)
305 
306 #define	xge_os_pci_read16(pdev, cfgh, where, val)	\
307 	(*(val) = pci_config_get16(cfgh, where))
308 
309 #define	xge_os_pci_write16(pdev, cfgh, where, val)	\
310 	pci_config_put16(cfgh, where, val)
311 
312 #define	xge_os_pci_read32(pdev, cfgh, where, val)	\
313 	(*(val) = pci_config_get32(cfgh, where))
314 
315 #define	xge_os_pci_write32(pdev, cfgh, where, val)	\
316 	pci_config_put32(cfgh, where, val)
317 
318 /* --------------------------- io primitives ------------------------------- */
319 
320 #define	xge_os_pio_mem_read8(pdev, regh, addr)		\
321 	(ddi_get8(regh, (uint8_t *)(addr)))
322 
323 #define	xge_os_pio_mem_write8(pdev, regh, val, addr)	\
324 	(ddi_put8(regh, (uint8_t *)(addr), val))
325 
326 #define	xge_os_pio_mem_read16(pdev, regh, addr)		\
327 	(ddi_get16(regh, (uint16_t *)(addr)))
328 
329 #define	xge_os_pio_mem_write16(pdev, regh, val, addr)	\
330 	(ddi_put16(regh, (uint16_t *)(addr), val))
331 
332 #define	xge_os_pio_mem_read32(pdev, regh, addr)		\
333 	(ddi_get32(regh, (uint32_t *)(addr)))
334 
335 #define	xge_os_pio_mem_write32(pdev, regh, val, addr)	\
336 	(ddi_put32(regh, (uint32_t *)(addr), val))
337 
338 #define	xge_os_pio_mem_read64(pdev, regh, addr)		\
339 	(ddi_get64(regh, (uint64_t *)(addr)))
340 
341 #define	xge_os_pio_mem_write64(pdev, regh, val, addr)	\
342 	(ddi_put64(regh, (uint64_t *)(addr), val))
343 
344 #define	xge_os_flush_bridge xge_os_pio_mem_read64
345 
346 /* --------------------------- dma primitives ----------------------------- */
347 
348 #define	XGE_OS_DMA_DIR_TODEVICE		DDI_DMA_SYNC_FORDEV
349 #define	XGE_OS_DMA_DIR_FROMDEVICE	DDI_DMA_SYNC_FORKERNEL
350 #define	XGE_OS_DMA_DIR_BIDIRECTIONAL	-1
351 #if defined(__x86)
352 #define	XGE_OS_DMA_USES_IOMMU		0
353 #else
354 #define	XGE_OS_DMA_USES_IOMMU		1
355 #endif
356 
357 #define	XGE_OS_INVALID_DMA_ADDR		((dma_addr_t)0)
358 
359 static inline dma_addr_t xge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah,
360     void *vaddr, size_t size, int dir, int dma_flags) {
361 	int ret;
362 	uint_t flags;
363 	uint_t ncookies;
364 	ddi_dma_cookie_t dma_cookie;
365 
366 	switch (dir) {
367 	case XGE_OS_DMA_DIR_TODEVICE:
368 		flags = DDI_DMA_WRITE;
369 		break;
370 	case XGE_OS_DMA_DIR_FROMDEVICE:
371 		flags = DDI_DMA_READ;
372 		break;
373 	case XGE_OS_DMA_DIR_BIDIRECTIONAL:
374 		flags = DDI_DMA_RDWR;
375 		break;
376 	default:
377 		return (0);
378 	}
379 
380 	flags |= (dma_flags & XGE_OS_DMA_CONSISTENT) ?
381 	    DDI_DMA_CONSISTENT : DDI_DMA_STREAMING;
382 
383 	ret = ddi_dma_addr_bind_handle(dmah, NULL, vaddr, size, flags,
384 	    DDI_DMA_SLEEP, 0, &dma_cookie, &ncookies);
385 	if (ret != DDI_SUCCESS) {
386 		return (0);
387 	}
388 
389 	if (ncookies != 1 || dma_cookie.dmac_size < size) {
390 		(void) ddi_dma_unbind_handle(dmah);
391 		return (0);
392 	}
393 
394 	return (dma_cookie.dmac_laddress);
395 }
396 
397 static inline void xge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah,
398     dma_addr_t dma_addr, size_t size, int dir)
399 {
400 	(void) ddi_dma_unbind_handle(dmah);
401 }
402 
403 static inline void xge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah,
404     dma_addr_t dma_addr, u64 dma_offset, size_t length, int dir)
405 {
406 	(void) ddi_dma_sync(dmah, dma_offset, length, dir);
407 }
408 
409 #ifdef __cplusplus
410 }
411 #endif
412 
413 #endif /* _SYS_XGE_OSDEP_H */
414