1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 * Copyright 2014 Pluribus Networks Inc. 29 * Copyright (c) 2017, Joyent, Inc. 30 */ 31 32 #ifndef _IGB_SW_H 33 #define _IGB_SW_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/types.h> 40 #include <sys/conf.h> 41 #include <sys/debug.h> 42 #include <sys/stropts.h> 43 #include <sys/stream.h> 44 #include <sys/strsun.h> 45 #include <sys/strlog.h> 46 #include <sys/kmem.h> 47 #include <sys/stat.h> 48 #include <sys/kstat.h> 49 #include <sys/modctl.h> 50 #include <sys/errno.h> 51 #include <sys/dlpi.h> 52 #include <sys/mac_provider.h> 53 #include <sys/mac_ether.h> 54 #include <sys/vlan.h> 55 #include <sys/ddi.h> 56 #include <sys/sunddi.h> 57 #include <sys/pci.h> 58 #include <sys/pcie.h> 59 #include <sys/sdt.h> 60 #include <sys/ethernet.h> 61 #include <sys/pattr.h> 62 #include <sys/strsubr.h> 63 #include <sys/netlb.h> 64 #include <sys/random.h> 65 #include <inet/common.h> 66 #include <inet/tcp.h> 67 #include <inet/ip.h> 68 #include <inet/mi.h> 69 #include <inet/nd.h> 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 #include "e1000_api.h" 75 #include "e1000_82575.h" 76 77 78 #define MODULE_NAME "igb" /* module name */ 79 80 #define IGB_SUCCESS DDI_SUCCESS 81 #define IGB_FAILURE DDI_FAILURE 82 83 #define IGB_UNKNOWN 0x00 84 #define IGB_INITIALIZED 0x01 85 #define IGB_STARTED 0x02 86 #define IGB_SUSPENDED 0x04 87 #define IGB_STALL 0x08 88 #define IGB_ERROR 0x80 89 90 #define IGB_RX_STOPPED 0x1 91 92 #define IGB_INTR_NONE 0 93 #define IGB_INTR_MSIX 1 94 #define IGB_INTR_MSI 2 95 #define IGB_INTR_LEGACY 3 96 97 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 98 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 99 100 #define IGB_NO_POLL -1 101 #define IGB_NO_FREE_SLOT -1 102 103 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 104 #define MCAST_ALLOC_COUNT 256 105 #define MAX_COOKIE 18 106 #define MIN_NUM_TX_DESC 2 107 108 /* 109 * Number of settings for interrupt throttle rate (ITR). There is one of 110 * these per msi-x vector and it needs to be the maximum of all silicon 111 * types supported by this driver. 112 */ 113 #define MAX_NUM_EITR 25 114 115 /* 116 * Maximum values for user configurable parameters 117 */ 118 #define MAX_TX_RING_SIZE 4096 119 #define MAX_RX_RING_SIZE 4096 120 #define MAX_RX_GROUP_NUM 4 121 122 #define MAX_MTU 9000 123 #define MAX_RX_LIMIT_PER_INTR 4096 124 125 #define MAX_RX_COPY_THRESHOLD 9216 126 #define MAX_TX_COPY_THRESHOLD 9216 127 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 128 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 129 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 130 #define MAX_MCAST_NUM 8192 131 132 /* 133 * Minimum values for user configurable parameters 134 */ 135 #define MIN_TX_RING_SIZE 64 136 #define MIN_RX_RING_SIZE 64 137 #define MIN_RX_GROUP_NUM 1 138 139 #define MIN_MTU ETHERMIN 140 #define MIN_RX_LIMIT_PER_INTR 16 141 142 #define MIN_RX_COPY_THRESHOLD 0 143 #define MIN_TX_COPY_THRESHOLD 0 144 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 145 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 146 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 147 #define MIN_MCAST_NUM 8 148 149 /* 150 * Default values for user configurable parameters 151 */ 152 #define DEFAULT_TX_RING_SIZE 512 153 #define DEFAULT_RX_RING_SIZE 512 154 #define DEFAULT_RX_GROUP_NUM 1 155 156 #define DEFAULT_MTU ETHERMTU 157 #define DEFAULT_RX_LIMIT_PER_INTR 256 158 159 #define DEFAULT_RX_COPY_THRESHOLD 128 160 #define DEFAULT_TX_COPY_THRESHOLD 512 161 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 162 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 163 #define DEFAULT_TX_RESCHED_THRESHOLD 128 164 #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32 165 #define DEFAULT_MCAST_NUM 4096 166 167 #define IGB_LSO_MAXLEN 65535 168 169 #define TX_DRAIN_TIME 200 170 #define RX_DRAIN_TIME 200 171 172 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 173 174 /* 175 * Defined for IP header alignment. 176 */ 177 #define IPHDR_ALIGN_ROOM 2 178 179 /* 180 * Bit flags for attach_progress 181 */ 182 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 183 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 184 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 185 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 186 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 187 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 188 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 189 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 190 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 191 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 192 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 193 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 194 195 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 196 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 197 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 198 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 199 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 200 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 201 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 202 #define PROP_DEFAULT_MTU "default_mtu" 203 #define PROP_FLOW_CONTROL "flow_control" 204 #define PROP_TX_RING_SIZE "tx_ring_size" 205 #define PROP_RX_RING_SIZE "rx_ring_size" 206 #define PROP_MR_ENABLE "mr_enable" 207 #define PROP_RX_GROUP_NUM "rx_group_number" 208 209 #define PROP_INTR_FORCE "intr_force" 210 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 211 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 212 #define PROP_LSO_ENABLE "lso_enable" 213 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 214 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 215 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 216 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 217 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 218 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 219 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 220 #define PROP_INTR_THROTTLING "intr_throttling" 221 #define PROP_MCAST_MAX_NUM "mcast_max_num" 222 223 #define IGB_LB_NONE 0 224 #define IGB_LB_EXTERNAL 1 225 #define IGB_LB_INTERNAL_PHY 3 226 #define IGB_LB_INTERNAL_SERDES 4 227 228 enum ioc_reply { 229 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 230 IOC_DONE, /* OK, reply sent */ 231 IOC_ACK, /* OK, just send ACK */ 232 IOC_REPLY /* OK, just send reply */ 233 }; 234 235 /* 236 * For s/w context extraction from a tx frame 237 */ 238 #define TX_CXT_SUCCESS 0 239 #define TX_CXT_E_LSO_CSUM (-1) 240 #define TX_CXT_E_ETHER_TYPE (-2) 241 242 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 243 0, 0, (flag))) 244 245 /* 246 * Defined for ring index operations 247 * ASSERT(index < limit) 248 * ASSERT(step < limit) 249 * ASSERT(index1 < limit) 250 * ASSERT(index2 < limit) 251 */ 252 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 253 (index) + (step) : (index) + (step) - (limit)) 254 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 255 (index) - (step) : (index) + (limit) - (step)) 256 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 257 (index2) - (index1) : (index2) + (limit) - (index1)) 258 259 #define LINK_LIST_INIT(_LH) \ 260 (_LH)->head = (_LH)->tail = NULL 261 262 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 263 264 #define LIST_POP_HEAD(_LH) \ 265 (single_link_t *)(_LH)->head; \ 266 { \ 267 if ((_LH)->head != NULL) { \ 268 (_LH)->head = (_LH)->head->link; \ 269 if ((_LH)->head == NULL) \ 270 (_LH)->tail = NULL; \ 271 } \ 272 } 273 274 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 275 276 #define LIST_PUSH_TAIL(_LH, _E) \ 277 if ((_LH)->tail != NULL) { \ 278 (_LH)->tail->link = (single_link_t *)(_E); \ 279 (_LH)->tail = (single_link_t *)(_E); \ 280 } else { \ 281 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 282 } \ 283 (_E)->link = NULL; 284 285 #define LIST_GET_NEXT(_LH, _E) \ 286 (((_LH)->tail == (single_link_t *)(_E)) ? \ 287 NULL : ((single_link_t *)(_E))->link) 288 289 290 typedef struct single_link { 291 struct single_link *link; 292 } single_link_t; 293 294 typedef struct link_list { 295 single_link_t *head; 296 single_link_t *tail; 297 } link_list_t; 298 299 /* 300 * Property lookups 301 */ 302 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 303 DDI_PROP_DONTPASS, (n)) 304 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 305 DDI_PROP_DONTPASS, (n), -1) 306 307 308 /* capability/feature flags */ 309 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 310 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 311 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 312 313 /* function pointer for nic-specific functions */ 314 typedef void (*igb_nic_func_t)(struct igb *); 315 316 /* adapter-specific info for each supported device type */ 317 typedef struct adapter_info { 318 /* limits */ 319 uint32_t max_rx_que_num; /* maximum number of rx queues */ 320 uint32_t min_rx_que_num; /* minimum number of rx queues */ 321 uint32_t def_rx_que_num; /* default number of rx queues */ 322 uint32_t max_tx_que_num; /* maximum number of tx queues */ 323 uint32_t min_tx_que_num; /* minimum number of tx queues */ 324 uint32_t def_tx_que_num; /* default number of tx queues */ 325 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 326 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 327 uint32_t def_intr_throttle; /* default interrupt throttle */ 328 /* function pointers */ 329 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 330 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 331 /* capabilities */ 332 uint32_t flags; /* capability flags */ 333 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 334 } adapter_info_t; 335 336 typedef union igb_ether_addr { 337 struct { 338 uint32_t high; 339 uint32_t low; 340 } reg; 341 struct { 342 uint8_t set; 343 uint8_t group_index; 344 uint8_t addr[ETHERADDRL]; 345 } mac; 346 } igb_ether_addr_t; 347 348 typedef enum { 349 USE_NONE, 350 USE_COPY, 351 USE_DMA 352 } tx_type_t; 353 354 typedef struct tx_context { 355 uint32_t hcksum_flags; 356 uint32_t ip_hdr_len; 357 uint32_t mac_hdr_len; 358 uint32_t l3_proto; 359 uint32_t l4_proto; 360 uint32_t mss; 361 uint32_t l4_hdr_len; 362 boolean_t lso_flag; 363 } tx_context_t; 364 365 /* Hold address/length of each DMA segment */ 366 typedef struct sw_desc { 367 uint64_t address; 368 size_t length; 369 } sw_desc_t; 370 371 /* Handles and addresses of DMA buffer */ 372 typedef struct dma_buffer { 373 caddr_t address; /* Virtual address */ 374 uint64_t dma_address; /* DMA (Hardware) address */ 375 ddi_acc_handle_t acc_handle; /* Data access handle */ 376 ddi_dma_handle_t dma_handle; /* DMA handle */ 377 size_t size; /* Buffer size */ 378 size_t len; /* Data length in the buffer */ 379 } dma_buffer_t; 380 381 /* 382 * Tx Control Block 383 */ 384 typedef struct tx_control_block { 385 single_link_t link; 386 uint32_t last_index; 387 uint32_t frag_num; 388 uint32_t desc_num; 389 mblk_t *mp; 390 tx_type_t tx_type; 391 ddi_dma_handle_t tx_dma_handle; 392 dma_buffer_t tx_buf; 393 sw_desc_t desc[MAX_COOKIE]; 394 } tx_control_block_t; 395 396 /* 397 * RX Control Block 398 */ 399 typedef struct rx_control_block { 400 mblk_t *mp; 401 uint32_t ref_cnt; 402 dma_buffer_t rx_buf; 403 frtn_t free_rtn; 404 struct igb_rx_data *rx_data; 405 } rx_control_block_t; 406 407 /* 408 * Software Data Structure for Tx Ring 409 */ 410 typedef struct igb_tx_ring { 411 uint32_t index; /* Ring index */ 412 uint32_t intr_vector; /* Interrupt vector index */ 413 414 /* 415 * Mutexes 416 */ 417 kmutex_t tx_lock; 418 kmutex_t recycle_lock; 419 kmutex_t tcb_head_lock; 420 kmutex_t tcb_tail_lock; 421 422 /* 423 * Tx descriptor ring definitions 424 */ 425 dma_buffer_t tbd_area; 426 union e1000_adv_tx_desc *tbd_ring; 427 uint32_t tbd_head; /* Index of next tbd to recycle */ 428 uint32_t tbd_tail; /* Index of next tbd to transmit */ 429 uint32_t tbd_free; /* Number of free tbd */ 430 431 /* 432 * Tx control block list definitions 433 */ 434 tx_control_block_t *tcb_area; 435 tx_control_block_t **work_list; 436 tx_control_block_t **free_list; 437 uint32_t tcb_head; /* Head index of free list */ 438 uint32_t tcb_tail; /* Tail index of free list */ 439 uint32_t tcb_free; /* Number of free tcb in free list */ 440 441 uint32_t *tbd_head_wb; /* Head write-back */ 442 uint32_t (*tx_recycle)(struct igb_tx_ring *); 443 444 /* 445 * s/w context structure for TCP/UDP checksum offload and LSO. 446 */ 447 tx_context_t tx_context; 448 449 /* 450 * Tx ring settings and status 451 */ 452 uint32_t ring_size; /* Tx descriptor ring size */ 453 uint32_t free_list_size; /* Tx free list size */ 454 455 boolean_t reschedule; 456 uint32_t recycle_fail; 457 uint32_t stall_watchdog; 458 459 /* 460 * Per-ring statistics 461 */ 462 uint64_t tx_pkts; /* Packets Transmitted Count */ 463 uint64_t tx_bytes; /* Bytes Transmitted Count */ 464 465 #ifdef IGB_DEBUG 466 /* 467 * Debug statistics 468 */ 469 uint32_t stat_overload; 470 uint32_t stat_fail_no_tbd; 471 uint32_t stat_fail_no_tcb; 472 uint32_t stat_fail_dma_bind; 473 uint32_t stat_reschedule; 474 uint32_t stat_pkt_cnt; 475 #endif 476 477 /* 478 * Pointer to the igb struct 479 */ 480 struct igb *igb; 481 mac_ring_handle_t ring_handle; /* call back ring handle */ 482 } igb_tx_ring_t; 483 484 /* 485 * Software Receive Ring 486 */ 487 typedef struct igb_rx_data { 488 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 489 490 /* 491 * Rx descriptor ring definitions 492 */ 493 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 494 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 495 uint32_t rbd_next; /* Index of next rx desc */ 496 497 /* 498 * Rx control block list definitions 499 */ 500 rx_control_block_t *rcb_area; 501 rx_control_block_t **work_list; /* Work list of rcbs */ 502 rx_control_block_t **free_list; /* Free list of rcbs */ 503 uint32_t rcb_head; /* Index of next free rcb */ 504 uint32_t rcb_tail; /* Index to put recycled rcb */ 505 uint32_t rcb_free; /* Number of free rcbs */ 506 507 /* 508 * Rx sw ring settings and status 509 */ 510 uint32_t ring_size; /* Rx descriptor ring size */ 511 uint32_t free_list_size; /* Rx free list size */ 512 513 uint32_t rcb_pending; 514 uint32_t flag; 515 516 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 517 } igb_rx_data_t; 518 519 /* 520 * Software Data Structure for Rx Ring 521 */ 522 typedef struct igb_rx_ring { 523 uint32_t index; /* Ring index */ 524 uint32_t intr_vector; /* Interrupt vector index */ 525 526 igb_rx_data_t *rx_data; /* Rx software ring */ 527 528 kmutex_t rx_lock; /* Rx access lock */ 529 530 /* 531 * Per-ring statistics 532 */ 533 uint64_t rx_pkts; /* Packets Received Count */ 534 uint64_t rx_bytes; /* Bytes Received Count */ 535 536 #ifdef IGB_DEBUG 537 /* 538 * Debug statistics 539 */ 540 uint32_t stat_frame_error; 541 uint32_t stat_cksum_error; 542 uint32_t stat_exceed_pkt; 543 uint32_t stat_pkt_cnt; 544 #endif 545 546 struct igb *igb; /* Pointer to igb struct */ 547 mac_ring_handle_t ring_handle; /* call back ring handle */ 548 uint32_t group_index; /* group index */ 549 uint64_t ring_gen_num; 550 } igb_rx_ring_t; 551 552 /* 553 * Software Receive Ring Group 554 */ 555 typedef struct igb_rx_group { 556 uint32_t index; /* Group index */ 557 mac_group_handle_t group_handle; /* call back group handle */ 558 struct igb *igb; /* Pointer to igb struct */ 559 } igb_rx_group_t; 560 561 typedef struct igb { 562 int instance; 563 mac_handle_t mac_hdl; 564 dev_info_t *dip; 565 struct e1000_hw hw; 566 struct igb_osdep osdep; 567 568 adapter_info_t *capab; /* adapter capabilities */ 569 570 uint32_t igb_state; 571 link_state_t link_state; 572 uint32_t link_speed; 573 uint32_t link_duplex; 574 boolean_t link_complete; 575 timeout_id_t link_tid; 576 577 uint32_t reset_count; 578 uint32_t attach_progress; 579 uint32_t loopback_mode; 580 uint32_t default_mtu; 581 uint32_t max_frame_size; 582 uint32_t dout_sync; 583 584 uint32_t rcb_pending; 585 586 uint32_t mr_enable; /* Enable multiple rings */ 587 uint32_t vmdq_mode; /* Mode of VMDq */ 588 589 /* 590 * Receive Rings and Groups 591 */ 592 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 593 uint32_t num_rx_rings; /* Number of rx rings in use */ 594 uint32_t rx_ring_size; /* Rx descriptor ring size */ 595 uint32_t rx_buf_size; /* Rx buffer size */ 596 igb_rx_group_t *rx_groups; /* Array of rx groups */ 597 uint32_t num_rx_groups; /* Number of rx groups in use */ 598 599 /* 600 * Transmit Rings 601 */ 602 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 603 uint32_t num_tx_rings; /* Number of tx rings in use */ 604 uint32_t tx_ring_size; /* Tx descriptor ring size */ 605 uint32_t tx_buf_size; /* Tx buffer size */ 606 607 boolean_t tx_ring_init; 608 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 609 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 610 boolean_t lso_enable; /* Large Segment Offload */ 611 uint32_t tx_copy_thresh; /* Tx copy threshold */ 612 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 613 uint32_t tx_overload_thresh; /* Tx overload threshold */ 614 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 615 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 616 uint32_t rx_copy_thresh; /* Rx copy threshold */ 617 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 618 619 uint32_t intr_throttling[MAX_NUM_EITR]; 620 uint32_t intr_force; 621 622 int intr_type; 623 int intr_cnt; 624 int intr_cap; 625 size_t intr_size; 626 uint_t intr_pri; 627 ddi_intr_handle_t *htable; 628 uint32_t eims_mask; 629 uint32_t ims_mask; 630 631 kmutex_t gen_lock; /* General lock for device access */ 632 kmutex_t watchdog_lock; 633 kmutex_t link_lock; 634 kmutex_t rx_pending_lock; 635 636 boolean_t watchdog_enable; 637 boolean_t watchdog_start; 638 timeout_id_t watchdog_tid; 639 640 boolean_t unicst_init; 641 uint32_t unicst_avail; 642 uint32_t unicst_total; 643 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 644 uint32_t mcast_count; 645 uint32_t mcast_alloc_count; 646 uint32_t mcast_max_num; 647 struct ether_addr *mcast_table; 648 649 /* 650 * LED related functions 651 */ 652 boolean_t igb_led_setup; 653 654 /* 655 * Kstat definitions 656 */ 657 kstat_t *igb_ks; 658 659 /* 660 * Backing store for MAC stats. These are reported via GLDv3, instead 661 * of via our private kstat structure. 662 */ 663 uint64_t stat_tor; /* rbytes */ 664 uint64_t stat_tpr; /* rpackets */ 665 uint64_t stat_tot; /* obytes */ 666 uint64_t stat_tpt; /* opackets */ 667 uint64_t stat_colc; /* collisions */ 668 uint64_t stat_mcc; /* multi colls */ 669 uint64_t stat_scc; /* single colls */ 670 uint64_t stat_ecol; /* excessive colls */ 671 uint64_t stat_latecol; /* late colls */ 672 uint64_t stat_bptc; /* xmit bcast */ 673 uint64_t stat_mptc; /* xmit bcast */ 674 uint64_t stat_bprc; /* recv bcast */ 675 uint64_t stat_mprc; /* recv mcast */ 676 uint64_t stat_rnbc; /* recv nobuf */ 677 uint64_t stat_roc; /* recv toolong */ 678 uint64_t stat_sec; /* sqe errors */ 679 uint64_t stat_dc; /* defer */ 680 uint64_t stat_algnerrc; /* align errors */ 681 uint64_t stat_crcerrs; /* crc errors */ 682 uint64_t stat_cexterr; /* carrier extension errors */ 683 uint64_t stat_ruc; /* recv tooshort */ 684 uint64_t stat_rjc; /* recv jabber */ 685 uint64_t stat_rxerrc; /* recv errors */ 686 687 uint32_t param_en_1000fdx_cap:1, 688 param_en_1000hdx_cap:1, 689 param_en_100t4_cap:1, 690 param_en_100fdx_cap:1, 691 param_en_100hdx_cap:1, 692 param_en_10fdx_cap:1, 693 param_en_10hdx_cap:1, 694 param_1000fdx_cap:1, 695 param_1000hdx_cap:1, 696 param_100t4_cap:1, 697 param_100fdx_cap:1, 698 param_100hdx_cap:1, 699 param_10fdx_cap:1, 700 param_10hdx_cap:1, 701 param_autoneg_cap:1, 702 param_pause_cap:1, 703 param_asym_pause_cap:1, 704 param_rem_fault:1, 705 param_adv_1000fdx_cap:1, 706 param_adv_1000hdx_cap:1, 707 param_adv_100t4_cap:1, 708 param_adv_100fdx_cap:1, 709 param_adv_100hdx_cap:1, 710 param_adv_10fdx_cap:1, 711 param_adv_10hdx_cap:1, 712 param_adv_autoneg_cap:1, 713 param_adv_pause_cap:1, 714 param_adv_asym_pause_cap:1, 715 param_adv_rem_fault:1, 716 param_lp_1000fdx_cap:1, 717 param_lp_1000hdx_cap:1, 718 param_lp_100t4_cap:1; 719 720 uint32_t param_lp_100fdx_cap:1, 721 param_lp_100hdx_cap:1, 722 param_lp_10fdx_cap:1, 723 param_lp_10hdx_cap:1, 724 param_lp_autoneg_cap:1, 725 param_lp_pause_cap:1, 726 param_lp_asym_pause_cap:1, 727 param_lp_rem_fault:1, 728 param_pad_to_32:24; 729 730 /* 731 * FMA capabilities 732 */ 733 int fm_capabilities; 734 735 ulong_t page_size; 736 } igb_t; 737 738 typedef struct igb_stat { 739 740 kstat_named_t reset_count; /* Reset Count */ 741 kstat_named_t dout_sync; /* DMA out of sync */ 742 #ifdef IGB_DEBUG 743 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 744 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 745 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 746 747 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 748 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 749 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 750 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 751 kstat_named_t tx_reschedule; /* Tx Reschedule */ 752 753 kstat_named_t gprc; /* Good Packets Received Count */ 754 kstat_named_t gptc; /* Good Packets Xmitted Count */ 755 kstat_named_t gor; /* Good Octets Received Count */ 756 kstat_named_t got; /* Good Octets Xmitd Count */ 757 kstat_named_t prc64; /* Packets Received - 64b */ 758 kstat_named_t prc127; /* Packets Received - 65-127b */ 759 kstat_named_t prc255; /* Packets Received - 127-255b */ 760 kstat_named_t prc511; /* Packets Received - 256-511b */ 761 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 762 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 763 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 764 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 765 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 766 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 767 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 768 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 769 #endif 770 kstat_named_t symerrs; /* Symbol Error Count */ 771 kstat_named_t mpc; /* Missed Packet Count */ 772 kstat_named_t rlec; /* Receive Length Error Count */ 773 kstat_named_t xonrxc; /* XON Received Count */ 774 kstat_named_t xontxc; /* XON Xmitted Count */ 775 kstat_named_t xoffrxc; /* XOFF Received Count */ 776 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 777 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 778 kstat_named_t rfc; /* Receive Frag Count */ 779 kstat_named_t tncrs; /* Transmit with no CRS */ 780 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 781 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 782 } igb_stat_t; 783 784 /* 785 * Function prototypes in e1000_osdep.c 786 */ 787 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 788 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 789 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 790 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 791 void e1000_rar_clear(struct e1000_hw *, uint32_t); 792 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 793 uint32_t, uint8_t); 794 795 /* 796 * Function prototypes in igb_buf.c 797 */ 798 int igb_alloc_dma(igb_t *); 799 void igb_free_dma(igb_t *); 800 void igb_free_dma_buffer(dma_buffer_t *); 801 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 802 void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 803 804 /* 805 * Function prototypes in igb_main.c 806 */ 807 int igb_start(igb_t *, boolean_t); 808 void igb_stop(igb_t *, boolean_t); 809 int igb_setup_link(igb_t *, boolean_t); 810 int igb_unicst_find(igb_t *, const uint8_t *); 811 int igb_unicst_set(igb_t *, const uint8_t *, int); 812 int igb_multicst_add(igb_t *, const uint8_t *); 813 int igb_multicst_remove(igb_t *, const uint8_t *); 814 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 815 void igb_enable_watchdog_timer(igb_t *); 816 void igb_disable_watchdog_timer(igb_t *); 817 int igb_atomic_reserve(uint32_t *, uint32_t); 818 int igb_check_acc_handle(ddi_acc_handle_t); 819 int igb_check_dma_handle(ddi_dma_handle_t); 820 void igb_fm_ereport(igb_t *, char *); 821 void igb_set_fma_flags(int); 822 823 /* 824 * Function prototypes in igb_gld.c 825 */ 826 int igb_m_start(void *); 827 void igb_m_stop(void *); 828 int igb_m_promisc(void *, boolean_t); 829 int igb_m_multicst(void *, boolean_t, const uint8_t *); 830 int igb_m_unicst(void *, const uint8_t *); 831 int igb_m_stat(void *, uint_t, uint64_t *); 832 void igb_m_resources(void *); 833 void igb_m_ioctl(void *, queue_t *, mblk_t *); 834 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 835 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 836 mac_ring_info_t *, mac_ring_handle_t); 837 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 838 int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 839 void igb_m_propinfo(void *, const char *, mac_prop_id_t, 840 mac_prop_info_handle_t); 841 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 842 int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 843 void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 844 boolean_t igb_param_locked(mac_prop_id_t); 845 void igb_fill_group(void *arg, mac_ring_type_t, const int, 846 mac_group_info_t *, mac_group_handle_t); 847 int igb_rx_ring_intr_enable(mac_intr_handle_t); 848 int igb_rx_ring_intr_disable(mac_intr_handle_t); 849 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 850 851 /* 852 * Function prototypes in igb_rx.c 853 */ 854 mblk_t *igb_rx(igb_rx_ring_t *, int); 855 void igb_rx_recycle(caddr_t arg); 856 857 /* 858 * Function prototypes in igb_tx.c 859 */ 860 void igb_free_tcb(tx_control_block_t *); 861 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 862 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 863 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 864 865 /* 866 * Function prototypes in igb_stat.c 867 */ 868 int igb_init_stats(igb_t *); 869 870 mblk_t *igb_rx_ring_poll(void *, int); 871 mblk_t *igb_tx_ring_send(void *, mblk_t *); 872 int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 873 int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 874 875 #ifdef __cplusplus 876 } 877 #endif 878 879 #endif /* _IGB_SW_H */ 880