1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hpi_vir.h> 27 #include <hxge_defs.h> 28 #include <hxge_impl.h> 29 30 /* 31 * Set up a logical group number that a logical device belongs to. 32 */ 33 hpi_status_t 34 hpi_fzc_ldg_num_set(hpi_handle_t handle, uint8_t ld, uint8_t ldg) 35 { 36 ld_grp_ctrl_t gnum; 37 38 if (!LD_VALID(ld)) { 39 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 40 " hpi_fzc_ldg_num_set ld <0x%x>", ld)); 41 return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld)); 42 } 43 44 if (!LDG_VALID(ldg)) { 45 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 46 " hpi_fzc_ldg_num_set ldg <0x%x>", ldg)); 47 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ld)); 48 } 49 50 gnum.value = 0; 51 gnum.bits.num = ldg; 52 53 HXGE_REG_WR32(handle, LD_GRP_CTRL + LD_NUM_OFFSET(ld), gnum.value); 54 55 return (HPI_SUCCESS); 56 } 57 58 /* 59 * Get device state vectors. 60 */ 61 hpi_status_t 62 hpi_ldsv_ldfs_get(hpi_handle_t handle, uint8_t ldg, uint32_t *vector0_p, 63 uint32_t *vector1_p) 64 { 65 int status; 66 67 if ((status = hpi_ldsv_get(handle, ldg, VECTOR0, vector0_p))) { 68 return (status); 69 } 70 if ((status = hpi_ldsv_get(handle, ldg, VECTOR1, vector1_p))) { 71 return (status); 72 } 73 74 return (HPI_SUCCESS); 75 } 76 77 /* 78 * Get device state vectors. 79 */ 80 hpi_status_t 81 hpi_ldsv_get(hpi_handle_t handle, uint8_t ldg, ldsv_type_t vector, 82 uint32_t *ldf_p) 83 { 84 uint32_t offset; 85 86 if (!LDG_VALID(ldg)) { 87 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 88 " hpi_ldsv_get Invalid Input ldg <0x%x>", ldg)); 89 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg)); 90 } 91 92 switch (vector) { 93 case VECTOR0: 94 offset = LDSV0 + LDSV_OFFSET(ldg); 95 break; 96 97 case VECTOR1: 98 offset = LDSV1 + LDSV_OFFSET(ldg); 99 break; 100 101 default: 102 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 103 " hpi_ldsv_get Invalid Input: ldsv type <0x%x>", vector)); 104 return (HPI_FAILURE | HPI_VIR_LDSV_INVALID(vector)); 105 } 106 107 HXGE_REG_RD32(handle, offset, ldf_p); 108 109 return (HPI_SUCCESS); 110 } 111 112 /* 113 * Set the mask bits for both ldf0 and ldf1. 114 */ 115 hpi_status_t 116 hpi_intr_mask_set(hpi_handle_t handle, uint8_t ld, uint8_t ldf_mask) 117 { 118 uint32_t offset; 119 120 if (!LD_VALID(ld)) { 121 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 122 " hpi_intr_mask_set ld", ld)); 123 return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld)); 124 } 125 126 ldf_mask &= LD_IM_MASK; 127 offset = LDSV_OFFSET_MASK(ld); 128 129 HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL, 130 "hpi_intr_mask_set: ld %d offset 0x%0x mask 0x%x", 131 ld, offset, ldf_mask)); 132 133 HXGE_REG_WR32(handle, offset, (uint32_t)ldf_mask); 134 135 return (HPI_SUCCESS); 136 } 137 138 /* 139 * Set interrupt timer and arm bit. 140 */ 141 hpi_status_t 142 hpi_intr_ldg_mgmt_set(hpi_handle_t handle, uint8_t ldg, boolean_t arm, 143 uint8_t timer) 144 { 145 ld_intr_mgmt_t mgm; 146 147 if (!LDG_VALID(ldg)) { 148 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 149 " hpi_intr_ldg_mgmt_set Invalid Input: ldg <0x%x>", ldg)); 150 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg)); 151 } 152 153 if (!LD_INTTIMER_VALID(timer)) { 154 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 155 " hpi_intr_ldg_mgmt_set Invalid Input" 156 " timer <0x%x>", timer)); 157 return (HPI_FAILURE | HPI_VIR_INTM_TM_INVALID(ldg)); 158 } 159 160 if (arm) { 161 mgm.bits.arm = 1; 162 } else { 163 HXGE_REG_RD32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), 164 &mgm.value); 165 } 166 167 mgm.bits.timer = timer; 168 HXGE_REG_WR32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), mgm.value); 169 170 HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL, 171 " hpi_intr_ldg_mgmt_set: ldg %d reg offset 0x%x", 172 ldg, LD_INTR_MGMT + LDSV_OFFSET(ldg))); 173 174 return (HPI_SUCCESS); 175 } 176 177 /* 178 * Set the timer resolution. 179 */ 180 hpi_status_t 181 hpi_fzc_ldg_timer_res_set(hpi_handle_t handle, uint32_t res) 182 { 183 ld_intr_tim_res_t tm; 184 185 if (res > LDGTITMRES_RES_MASK) { 186 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 187 " hpi_fzc_ldg_timer_res_set Invalid Input: res <0x%x>", 188 res)); 189 return (HPI_FAILURE | HPI_VIR_TM_RES_INVALID); 190 } 191 192 tm.value = 0; 193 tm.bits.res = res; 194 195 HXGE_REG_WR32(handle, LD_INTR_TIM_RES, tm.value); 196 197 return (HPI_SUCCESS); 198 } 199 200 /* 201 * Set the system interrupt data. 202 */ 203 hpi_status_t 204 hpi_fzc_sid_set(hpi_handle_t handle, fzc_sid_t sid) 205 { 206 sid_t sd; 207 208 if (!LDG_VALID(sid.ldg)) { 209 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 210 " hpi_fzc_sid_set Invalid Input: ldg <0x%x>", sid.ldg)); 211 return (HPI_FAILURE | HPI_VIR_LDG_INVALID(sid.ldg)); 212 } 213 214 if (!SID_VECTOR_VALID(sid.vector)) { 215 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 216 " hpi_fzc_sid_set Invalid Input: vector <0x%x>", 217 sid.vector)); 218 219 return (HPI_FAILURE | HPI_VIR_SID_VEC_INVALID(sid.vector)); 220 } 221 222 sd.value = 0; 223 sd.bits.data = sid.vector; 224 HXGE_REG_WR32(handle, SID + LDG_SID_OFFSET(sid.ldg), sd.value); 225 226 return (HPI_SUCCESS); 227 } 228 229 /* 230 * Mask/Unmask the device error mask bits. 231 */ 232 hpi_status_t 233 hpi_fzc_sys_err_mask_set(hpi_handle_t handle, boolean_t mask) 234 { 235 dev_err_mask_t dev_mask; 236 237 dev_mask.value = 0; 238 if (mask) { 239 dev_mask.bits.tdc_mask0 = 1; 240 dev_mask.bits.rdc_mask0 = 1; 241 dev_mask.bits.vnm_pio_mask1 = 1; 242 dev_mask.bits.tdc_mask1 = 1; 243 dev_mask.bits.rdc_mask1 = 1; 244 dev_mask.bits.peu_mask1 = 1; 245 } 246 247 HXGE_REG_WR32(handle, DEV_ERR_MASK, dev_mask.value); 248 return (HPI_SUCCESS); 249 } 250 251 /* 252 * Get the system error stats. 253 */ 254 hpi_status_t 255 hpi_fzc_sys_err_stat_get(hpi_handle_t handle, dev_err_stat_t *statp) 256 { 257 HXGE_REG_RD32(handle, DEV_ERR_STAT, &statp->value); 258 return (HPI_SUCCESS); 259 } 260