1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_ADAPTER_H 24 #define __CXGBE_ADAPTER_H 25 26 #include <sys/ddi.h> 27 #include <sys/mac_provider.h> 28 #include <sys/ethernet.h> 29 #include <sys/queue.h> 30 31 #include "offload.h" 32 #include "firmware/t4fw_interface.h" 33 34 struct adapter; 35 typedef struct adapter adapter_t; 36 37 enum { 38 FW_IQ_QSIZE = 256, 39 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 40 41 RX_IQ_QSIZE = 1024, 42 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 43 44 EQ_ESIZE = 64, /* All egres queues use this entry size */ 45 46 RX_FL_ESIZE = 64, /* 8 64bit addresses */ 47 48 FL_BUF_SIZES = 4, 49 50 CTRL_EQ_QSIZE = 128, 51 52 TX_EQ_QSIZE = 1024, 53 TX_SGL_SEGS = 36, 54 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 55 }; 56 57 enum { 58 /* adapter flags */ 59 FULL_INIT_DONE = (1 << 0), 60 FW_OK = (1 << 1), 61 INTR_FWD = (1 << 2), 62 INTR_ALLOCATED = (1 << 3), 63 MASTER_PF = (1 << 4), 64 65 CXGBE_BUSY = (1 << 9), 66 67 /* port flags */ 68 DOOMED = (1 << 0), 69 PORT_INIT_DONE = (1 << 1), 70 }; 71 72 enum { 73 /* Features */ 74 CXGBE_HW_LSO = (1 << 0), 75 CXGBE_HW_CSUM = (1 << 1), 76 }; 77 78 #define IS_DOOMED(pi) (pi->flags & DOOMED) 79 #define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0) 80 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) 81 #define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0) 82 #define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0) 83 84 struct port_info { 85 PORT_INFO_HDR; 86 87 kmutex_t lock; 88 struct adapter *adapter; 89 90 #ifndef TCP_OFFLOAD_DISABLE 91 void *tdev; 92 #endif 93 94 unsigned int flags; 95 96 uint16_t viid; 97 int16_t xact_addr_filt; /* index of exact MAC address filter */ 98 uint16_t rss_size; /* size of VI's RSS table slice */ 99 uint16_t ntxq; /* # of tx queues */ 100 uint16_t first_txq; /* index of first tx queue */ 101 uint16_t nrxq; /* # of rx queues */ 102 uint16_t first_rxq; /* index of first rx queue */ 103 #ifndef TCP_OFFLOAD_DISABLE 104 uint16_t nofldtxq; /* # of offload tx queues */ 105 uint16_t first_ofld_txq; /* index of first offload tx queue */ 106 uint16_t nofldrxq; /* # of offload rx queues */ 107 uint16_t first_ofld_rxq; /* index of first offload rx queue */ 108 #endif 109 uint8_t lport; /* associated offload logical port */ 110 int8_t mdio_addr; 111 uint8_t port_type; 112 uint8_t mod_type; 113 uint8_t port_id; 114 uint8_t tx_chan; 115 uint8_t instance; /* Associated adapter instance */ 116 uint8_t child_inst; /* Associated child instance */ 117 uint8_t tmr_idx; 118 int8_t pktc_idx; 119 struct link_config link_cfg; 120 struct port_stats stats; 121 uint32_t features; 122 kstat_t *ksp_config; 123 kstat_t *ksp_info; 124 }; 125 126 struct fl_sdesc { 127 struct rxbuf *rxb; 128 }; 129 130 struct tx_desc { 131 __be64 flit[8]; 132 }; 133 134 /* DMA maps used for tx */ 135 struct tx_maps { 136 ddi_dma_handle_t *map; 137 uint32_t map_total; /* # of DMA maps */ 138 uint32_t map_pidx; /* next map to be used */ 139 uint32_t map_cidx; /* reclaimed up to this index */ 140 uint32_t map_avail; /* # of available maps */ 141 }; 142 143 struct tx_sdesc { 144 mblk_t *m; 145 uint32_t txb_used; /* # of bytes of tx copy buffer used */ 146 uint16_t hdls_used; /* # of dma handles used */ 147 uint16_t desc_used; /* # of hardware descriptors used */ 148 }; 149 150 enum { 151 /* iq flags */ 152 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 153 IQ_INTR = (1 << 1), /* iq takes direct interrupt */ 154 IQ_HAS_FL = (1 << 2), /* iq has fl */ 155 156 /* iq state */ 157 IQS_DISABLED = 0, 158 IQS_BUSY = 1, 159 IQS_IDLE = 2, 160 }; 161 162 /* 163 * Ingress Queue: T4 is producer, driver is consumer. 164 */ 165 struct sge_iq { 166 unsigned int flags; 167 ddi_dma_handle_t dhdl; 168 ddi_acc_handle_t ahdl; 169 170 volatile uint_t state; 171 __be64 *desc; /* KVA of descriptor ring */ 172 uint64_t ba; /* bus address of descriptor ring */ 173 const __be64 *cdesc; /* current descriptor */ 174 struct adapter *adapter; /* associated adapter */ 175 uint8_t gen; /* generation bit */ 176 uint8_t intr_params; /* interrupt holdoff parameters */ 177 int8_t intr_pktc_idx; /* packet count threshold index */ 178 uint8_t intr_next; /* holdoff for next interrupt */ 179 uint8_t esize; /* size (bytes) of each entry in the queue */ 180 uint16_t qsize; /* size (# of entries) of the queue */ 181 uint16_t cidx; /* consumer index */ 182 uint16_t pending; /* # of descs processed since last doorbell */ 183 uint16_t cntxt_id; /* SGE context id for the iq */ 184 uint16_t abs_id; /* absolute SGE id for the iq */ 185 186 STAILQ_ENTRY(sge_iq) link; 187 }; 188 189 enum { 190 EQ_CTRL = 1, 191 EQ_ETH = 2, 192 #ifndef TCP_OFFLOAD_DISABLE 193 EQ_OFLD = 3, 194 #endif 195 196 /* eq flags */ 197 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 198 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 199 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 200 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 201 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 202 EQ_MTX = (1 << 7), /* mutex has been initialized */ 203 EQ_STARTED = (1 << 8), /* started */ 204 }; 205 206 /* Listed in order of preference. Update t4_sysctls too if you change these */ 207 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8}; 208 209 /* 210 * Egress Queue: driver is producer, T4 is consumer. 211 * 212 * Note: A free list is an egress queue (driver produces the buffers and T4 213 * consumes them) but it's special enough to have its own struct (see sge_fl). 214 */ 215 struct sge_eq { 216 ddi_dma_handle_t desc_dhdl; 217 ddi_acc_handle_t desc_ahdl; 218 unsigned int flags; 219 kmutex_t lock; 220 221 struct tx_desc *desc; /* KVA of descriptor ring */ 222 uint64_t ba; /* bus address of descriptor ring */ 223 struct sge_qstat *spg; /* status page, for convenience */ 224 int doorbells; 225 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 226 u_int udb_qid; /* relative qid within the doorbell page */ 227 uint16_t cap; /* max # of desc, for convenience */ 228 uint16_t avail; /* available descriptors, for convenience */ 229 uint16_t qsize; /* size (# of entries) of the queue */ 230 uint16_t cidx; /* consumer idx (desc idx) */ 231 uint16_t pidx; /* producer idx (desc idx) */ 232 uint16_t pending; /* # of descriptors used since last doorbell */ 233 uint16_t iqid; /* iq that gets egr_update for the eq */ 234 uint8_t tx_chan; /* tx channel used by the eq */ 235 uint32_t cntxt_id; /* SGE context id for the eq */ 236 }; 237 238 enum { 239 /* fl flags */ 240 FL_MTX = (1 << 0), /* mutex has been initialized */ 241 FL_STARVING = (1 << 1), /* on the list of starving fl's */ 242 FL_DOOMED = (1 << 2), /* about to be destroyed */ 243 }; 244 245 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 246 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 247 248 struct sge_fl { 249 unsigned int flags; 250 kmutex_t lock; 251 ddi_dma_handle_t dhdl; 252 ddi_acc_handle_t ahdl; 253 254 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 255 uint64_t ba; /* bus address of descriptor ring */ 256 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 257 uint32_t cap; /* max # of buffers, for convenience */ 258 uint16_t qsize; /* size (# of entries) of the queue */ 259 uint16_t cntxt_id; /* SGE context id for the freelist */ 260 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 261 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 262 uint32_t needed; /* # of buffers needed to fill up fl. */ 263 uint32_t lowat; /* # of buffers <= this means fl needs help */ 264 uint32_t pending; /* # of bufs allocated since last doorbell */ 265 uint32_t offset; /* current packet within the larger buffer */ 266 uint16_t copy_threshold; /* anything this size or less is copied up */ 267 268 uint64_t copied_up; /* # of frames copied into mblk and handed up */ 269 uint64_t passed_up; /* # of frames wrapped in mblk and handed up */ 270 271 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 272 }; 273 274 /* txq: SGE egress queue + miscellaneous items */ 275 struct sge_txq { 276 struct sge_eq eq; /* MUST be first */ 277 278 struct port_info *port; /* the port this txq belongs to */ 279 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 280 281 /* DMA handles used for tx */ 282 ddi_dma_handle_t *tx_dhdl; 283 uint32_t tx_dhdl_total; /* Total # of handles */ 284 uint32_t tx_dhdl_pidx; /* next handle to be used */ 285 uint32_t tx_dhdl_cidx; /* reclaimed up to this index */ 286 uint32_t tx_dhdl_avail; /* # of available handles */ 287 288 /* Copy buffers for tx */ 289 ddi_dma_handle_t txb_dhdl; 290 ddi_acc_handle_t txb_ahdl; 291 caddr_t txb_va; /* KVA of copy buffers area */ 292 uint64_t txb_ba; /* bus address of copy buffers area */ 293 uint32_t txb_size; /* total size */ 294 uint32_t txb_next; /* offset of next useable area in the buffer */ 295 uint32_t txb_avail; /* # of bytes available */ 296 uint16_t copy_threshold; /* anything this size or less is copied up */ 297 298 kstat_t *ksp; 299 300 /* stats for common events first */ 301 302 uint64_t txcsum; /* # of times hardware assisted with checksum */ 303 uint64_t tso_wrs; /* # of IPv4 TSO work requests */ 304 uint64_t imm_wrs; /* # of work requests with immediate data */ 305 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 306 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 307 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 308 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 309 uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */ 310 uint64_t hdl_used; /* # of DMA handles used */ 311 312 /* stats for not-that-common events */ 313 314 uint32_t txb_full; /* txb ran out of space */ 315 uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */ 316 uint32_t dma_map_failed; /* couldn't obtain DMA mapping */ 317 uint32_t qfull; /* out of hardware descriptors */ 318 uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */ 319 uint32_t pullup_early; /* # of pullups before starting frame's SGL */ 320 uint32_t pullup_late; /* # of pullups while building frame's SGL */ 321 uint32_t pullup_failed; /* # of failed pullups */ 322 }; 323 324 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 325 struct sge_rxq { 326 struct sge_iq iq; /* MUST be first */ 327 struct sge_fl fl; 328 329 struct port_info *port; /* the port this rxq belongs to */ 330 kstat_t *ksp; 331 332 /* stats for common events first */ 333 334 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 335 336 /* stats for not-that-common events */ 337 338 uint32_t nomem; /* mblk allocation during rx failed */ 339 }; 340 341 #ifndef TCP_OFFLOAD_DISABLE 342 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 343 struct sge_ofld_rxq { 344 struct sge_iq iq; /* MUST be first */ 345 struct sge_fl fl; 346 }; 347 348 /* 349 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 350 * and offload tx queues are of this type. 351 */ 352 struct sge_wrq { 353 struct sge_eq eq; /* MUST be first */ 354 355 struct adapter *adapter; 356 357 /* List of WRs held up due to lack of tx descriptors */ 358 struct mblk_pair wr_list; 359 360 /* stats for common events first */ 361 362 uint64_t tx_wrs; /* # of tx work requests */ 363 364 /* stats for not-that-common events */ 365 366 uint32_t no_desc; /* out of hardware descriptors */ 367 }; 368 #endif 369 370 struct sge { 371 int fl_starve_threshold; 372 int s_qpp; 373 374 int nrxq; /* total rx queues (all ports and the rest) */ 375 int ntxq; /* total tx queues (all ports and the rest) */ 376 #ifndef TCP_OFFLOAD_DISABLE 377 int nofldrxq; /* total # of TOE rx queues */ 378 int nofldtxq; /* total # of TOE tx queues */ 379 #endif 380 int niq; /* total ingress queues */ 381 int neq; /* total egress queues */ 382 383 struct sge_iq fwq; /* Firmware event queue */ 384 #ifndef TCP_OFFLOAD_DISABLE 385 struct sge_wrq mgmtq; /* Management queue (Control queue) */ 386 #endif 387 struct sge_txq *txq; /* NIC tx queues */ 388 struct sge_rxq *rxq; /* NIC rx queues */ 389 #ifndef TCP_OFFLOAD_DISABLE 390 struct sge_wrq *ctrlq; /* Control queues */ 391 struct sge_wrq *ofld_txq; /* TOE tx queues */ 392 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 393 #endif 394 395 uint16_t iq_start; 396 int eq_start; 397 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 398 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 399 400 /* Device access and DMA attributes for all the descriptor rings */ 401 ddi_device_acc_attr_t acc_attr_desc; 402 ddi_dma_attr_t dma_attr_desc; 403 404 /* Device access and DMA attributes for tx buffers */ 405 ddi_device_acc_attr_t acc_attr_tx; 406 ddi_dma_attr_t dma_attr_tx; 407 408 /* Device access and DMA attributes for rx buffers are in rxb_params */ 409 kmem_cache_t *rxbuf_cache; 410 struct rxbuf_cache_params rxb_params; 411 }; 412 413 struct driver_properties { 414 /* There is a driver.conf variable for each of these */ 415 int max_ntxq_10g; 416 int max_nrxq_10g; 417 int max_ntxq_1g; 418 int max_nrxq_1g; 419 #ifndef TCP_OFFLOAD_DISABLE 420 int max_nofldtxq_10g; 421 int max_nofldrxq_10g; 422 int max_nofldtxq_1g; 423 int max_nofldrxq_1g; 424 #endif 425 int intr_types; 426 int tmr_idx_10g; 427 int pktc_idx_10g; 428 int tmr_idx_1g; 429 int pktc_idx_1g; 430 int qsize_txq; 431 int qsize_rxq; 432 433 int timer_val[SGE_NTIMERS]; 434 int counter_val[SGE_NCOUNTERS]; 435 436 int wc; 437 }; 438 439 struct rss_header; 440 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 441 mblk_t *); 442 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 443 444 struct adapter { 445 SLIST_ENTRY(adapter) link; 446 dev_info_t *dip; 447 dev_t dev; 448 449 unsigned int pf; 450 unsigned int mbox; 451 452 uint_t open; /* character device is open */ 453 454 /* PCI config space access handle */ 455 ddi_acc_handle_t pci_regh; 456 457 /* MMIO register access handle */ 458 ddi_acc_handle_t regh; 459 caddr_t regp; 460 /* BAR1 register access handle */ 461 ddi_acc_handle_t reg1h; 462 caddr_t reg1p; 463 464 /* Interrupt information */ 465 int intr_type; 466 int intr_count; 467 int intr_cap; 468 uint_t intr_pri; 469 ddi_intr_handle_t *intr_handle; 470 471 struct driver_properties props; 472 kstat_t *ksp; 473 kstat_t *ksp_stat; 474 475 struct sge sge; 476 477 struct port_info *port[MAX_NPORTS]; 478 uint8_t chan_map[NCHAN]; 479 uint32_t filter_mode; 480 481 struct l2t_data *l2t; /* L2 table */ 482 struct tid_info tids; 483 484 int doorbells; 485 int registered_device_map; 486 int open_device_map; 487 int flags; 488 489 unsigned int cfcsum; 490 struct adapter_params params; 491 struct t4_virt_res vres; 492 493 #ifndef TCP_OFFLOAD_DISABLE 494 struct uld_softc tom; 495 struct tom_tunables tt; 496 #endif 497 498 #ifndef TCP_OFFLOAD_DISABLE 499 int offload_map; 500 #endif 501 uint16_t linkcaps; 502 uint16_t niccaps; 503 uint16_t toecaps; 504 uint16_t rdmacaps; 505 uint16_t iscsicaps; 506 uint16_t fcoecaps; 507 508 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 509 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 510 511 kmutex_t lock; 512 kcondvar_t cv; 513 514 /* Starving free lists */ 515 kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */ 516 TAILQ_HEAD(, sge_fl) sfl; 517 timeout_id_t sfl_timer; 518 }; 519 520 enum { 521 NIC_H = 0, 522 TOM_H, 523 IW_H, 524 ISCSI_H 525 }; 526 527 #define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock) 528 #define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock) 529 #define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock)) 530 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock)) 531 532 #define PORT_LOCK(pi) mutex_enter(&(pi)->lock) 533 #define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock) 534 #define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock)) 535 #define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock)) 536 537 #define IQ_LOCK(iq) mutex_enter(&(iq)->lock) 538 #define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock) 539 #define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock)) 540 #define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock)) 541 542 #define FL_LOCK(fl) mutex_enter(&(fl)->lock) 543 #define FL_UNLOCK(fl) mutex_exit(&(fl)->lock) 544 #define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock)) 545 #define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock)) 546 547 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq) 548 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq) 549 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq) 550 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq) 551 552 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 553 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 554 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 555 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 556 557 #define EQ_LOCK(eq) mutex_enter(&(eq)->lock) 558 #define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock) 559 #define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock)) 560 #define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock)) 561 562 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 563 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 564 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 565 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 566 567 #define for_each_txq(pi, iter, txq) \ 568 txq = &pi->adapter->sge.txq[pi->first_txq]; \ 569 for (iter = 0; iter < pi->ntxq; ++iter, ++txq) 570 #define for_each_rxq(pi, iter, rxq) \ 571 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ 572 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) 573 #define for_each_ofld_txq(pi, iter, ofld_txq) \ 574 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \ 575 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq) 576 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \ 577 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \ 578 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq) 579 580 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) 581 582 /* One for errors, one for firmware events */ 583 #define T4_EXTRA_INTR 2 584 585 /* adapter.c */ 586 uint32_t t4_read_reg(struct adapter *sc, uint32_t reg); 587 void t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val); 588 void t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val); 589 void t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val); 590 void t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val); 591 void t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val); 592 void t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val); 593 void t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val); 594 uint64_t t4_read_reg64(struct adapter *sc, uint32_t reg); 595 void t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val); 596 struct port_info *adap2pinfo(struct adapter *sc, int idx); 597 void t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]); 598 bool is_10G_port(const struct port_info *pi); 599 bool is_40G_port(const struct port_info *pi); 600 struct sge_rxq *iq_to_rxq(struct sge_iq *iq); 601 int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m); 602 603 /* t4_nexus.c */ 604 int t4_os_find_pci_capability(struct adapter *sc, int cap); 605 void t4_os_portmod_changed(const struct adapter *sc, int idx); 606 int adapter_full_init(struct adapter *sc); 607 int adapter_full_uninit(struct adapter *sc); 608 int port_full_init(struct port_info *pi); 609 int port_full_uninit(struct port_info *pi); 610 void enable_port_queues(struct port_info *pi); 611 void disable_port_queues(struct port_info *pi); 612 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); 613 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 614 void t4_iterate(void (*func)(int, void *), void *arg); 615 616 /* t4_sge.c */ 617 void t4_sge_init(struct adapter *sc); 618 int t4_setup_adapter_queues(struct adapter *sc); 619 int t4_teardown_adapter_queues(struct adapter *sc); 620 int t4_setup_port_queues(struct port_info *pi); 621 int t4_teardown_port_queues(struct port_info *pi); 622 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); 623 uint_t t4_intr(caddr_t arg1, caddr_t arg2); 624 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); 625 int t4_mgmt_tx(struct adapter *sc, mblk_t *m); 626 #ifndef TCP_OFFLOAD_DISABLE 627 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0); 628 #endif 629 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); 630 uint32_t position_memwin(struct adapter *, int, uint32_t); 631 632 mblk_t *t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame); 633 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, 634 int flags); 635 636 /* t4_mac.c */ 637 void t4_mc_init(struct port_info *pi); 638 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat); 639 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m); 640 641 /* t4_ioctl.c */ 642 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode); 643 644 struct l2t_data *t4_init_l2t(struct adapter *sc); 645 #endif /* __CXGBE_ADAPTER_H */ 646