1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_ATI 0x1002 36 #define AUDIOHD_VID_CIRRUS 0x1013 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_REALTEK 0x10ec 39 #define AUDIOHD_VID_IDT 0x111d 40 #define AUDIOHD_VID_ANALOG 0x11d4 41 #define AUDIOHD_VID_CONEXANT 0x14f1 42 #define AUDIOHD_VID_SIGMATEL 0x8384 43 #define AUDIOHD_VID_INTEL 0x8086 44 45 /* 46 * specific audiohd controller device id 47 */ 48 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 49 50 /* 51 * specific codec id used by specific vendors 52 */ 53 #define AUDIOHD_CODEC_IDT7608 0x111d7608 54 #define AUDIOHD_CODEC_IDT76B2 0x111d76b2 55 #define AUDIOHD_CODEC_AD1981 0x11d41981 56 #define AUDIOHD_CODEC_ALC272 0x10ec0272 57 #define AUDIOHD_CODEC_ALC885 0x10ec0885 58 #define AUDIOHD_CODECID_ALC888 0x10ec0888 59 #define AUDIOHD_CODECID_SONY1 0x10ec0260 60 #define AUDIOHD_CODECID_SONY2 0x10ec0262 61 #define AUDIOHD_CODEC_CX20549 0x14f15045 62 63 #define AUDIOHD_INTS 50 64 #define AUDIOHD_MAX_INTS 1500 65 #define AUDIOHD_MIN_INTS 32 66 67 #define AUDIOHD_DEV_CONFIG "onboard1" 68 #define AUDIOHD_DEV_VERSION "a" 69 70 #define AUDIOHD_FMT_PCM 0x001 71 /* 72 * Only for Intel hardware: 73 * PCI Express traffic class select register in PCI configure space 74 */ 75 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 76 77 /* 78 * Only for ATI SB450: 79 * MISC control register 2 80 */ 81 #define AUDIOHD_ATI_PCI_MISC2 0x42 82 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 83 #define AUDIOHDC_NID(x) x 84 #define AUDIOHDC_NULL_NODE -1 85 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 86 /* 87 * currently, only the format of 48K sample rate, 16-bit 88 * 2-channel is supported. 89 */ 90 #define AUDIOHD_FMT_PCMOUT 0x0011 91 #define AUDIOHD_FMT_PCMIN 0x0011 92 93 #define AUDIOHD_EXT_AMP_MASK 0x00010000 94 #define AUDIOHD_EXT_AMP_ENABLE 0x02 95 /* NVIDIA snoop */ 96 #define AUDIOHD_NVIDIA_SNOOP 0x0f 97 98 /* Power On/Off */ 99 #define AUDIOHD_PW_OFF 1 100 #define AUDIOHD_PW_ON 0 101 #define AUDIOHD_PW_D0 0 102 #define AUDIOHD_PW_D2 2 103 104 #define AUDIOHD_INTEL_TCS_MASK 0xf8 105 #define AUDIOHD_ATI_MISC2_MASK 0xf8 106 107 /* Pin speaker On/Off */ 108 #define AUDIOHD_SP_ON 1 109 #define AUDIOHD_SP_OFF 0 110 111 #define AUDIOHD_PORT_MAX 15 112 #define AUDIOHD_CODEC_MAX 16 113 #define AUDIOHD_MEMIO_LEN 0x4000 114 115 #define AUDIOHD_RETRY_TIMES 60 116 #define AUDIOHD_TEST_TIMES 500 117 #define AUDIOHD_OUTSTR_NUM_OFF 12 118 #define AUDIOHD_INSTR_NUM_OFF 8 119 120 #define AUDIOHD_CORB_SIZE_OFF 0x4e 121 122 #define AUDIOHD_URCAP_MASK 0x80 123 #define AUDIOHD_DTCCAP_MASK 0x4 124 #define AUDIOHD_UR_ENABLE_OFF 8 125 #define AUDIOHD_UR_TAG_MASK 0x1f 126 127 #define AUDIOHD_CIS_MASK 0x40000000 128 129 #define AUDIOHD_RIRB_UR_MASK 0x10 130 #define AUDIOHD_RIRB_CODEC_MASK 0xf 131 #define AUDIOHD_RIRB_WID_OFF 27 132 #define AUDIOHD_RIRB_INTRCNT 0x0 133 #define AUDIOHD_RIRB_WPMASK 0xff 134 135 #define AUDIOHD_FORM_MASK 0x0080 136 #define AUDIOHD_LEN_MASK 0x007f 137 #define AUDIOHD_PIN_CAP_MASK 0x00000010 138 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 139 #define AUDIOHD_PIN_CON_MASK 3 140 #define AUDIOHD_PIN_CON_STEP 30 141 #define AUDIOHD_PIN_IO_MASK 0X0018 142 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 143 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 144 #define AUDIOHD_PIN_ASO_OFF 0x4 145 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 146 #define AUDIOHD_PIN_DEV_OFF 20 147 #define AUDIOHD_PIN_NUMS 6 148 #define AUDIOHD_PIN_NO_CONN 0x40000000 149 #define AUDIOHD_PIN_IN_ENABLE 0x20 150 #define AUDIOHD_PIN_OUT_ENABLE 0x40 151 #define AUDIOHD_PIN_PRES_OFF 0x20 152 #define AUDIOHD_PIN_CONTP_OFF 0x1e 153 #define AUDIOHD_PIN_CON_JACK 0 154 #define AUDIOHD_PIN_CON_FIXED 0x2 155 #define AUDIOHD_PIN_CONTP_MASK 0x3 156 #define AUDIOHD_PIN_VREF_L1 0x20 157 #define AUDIOHD_PIN_VREF_L2 0x10 158 #define AUDIOHD_PIN_VREF_L3 0x04 159 #define AUDIOHD_PIN_VREF_L4 0x02 160 #define AUDIOHD_PIN_VREF_OFF 8 161 #define AUDIOHD_PIN_VREF_MASK 0xff 162 #define AUDIOHD_PIN_CLR_MASK 0xf 163 #define AUDIOHD_PIN_CLR_OFF 12 164 165 166 #define AUDIOHD_VERB_ADDR_OFF 28 167 #define AUDIOHD_VERB_NID_OFF 20 168 #define AUDIOHD_VERB_CMD_OFF 8 169 #define AUDIOHD_VERB_CMD16_OFF 16 170 171 #define AUDIOHD_RING_MAX_SIZE 0x00ff 172 #define AUDIOHD_REC_TAG_OFF 4 173 #define AUDIOHD_PLAY_TAG_OFF 4 174 #define AUDIOHD_PLAY_CTL_OFF 2 175 #define AUDIOHD_REC_CTL_OFF 2 176 177 #define AUDIOHD_SPDIF_ON 1 178 #define AUDIOHD_SPDIF_MASK 0x00ff 179 180 #define AUDIOHD_GAIN_OFF 8 181 182 #define AUDIOHD_CODEC_STR_OFF 16 183 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 184 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 185 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 186 187 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 188 #define AUDIOHD_FRAGFR_ALIGN 64 189 #define AUDIOHD_BDLE_BUF_ALIGN 128 190 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 191 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 192 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 193 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 194 195 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 196 197 /* 198 * Audio registers of high definition 199 */ 200 #define AUDIOHD_REG_GCAP 0x00 201 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 202 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 203 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 204 #define AUDIOHDR_GCAP_NSDO 0x0006 205 #define AUDIOHDR_GCAP_64OK 0x0001 206 207 #define AUDIOHD_REG_VMIN 0x02 208 #define AUDIOHD_REG_VMAJ 0x03 209 #define AUDIOHD_REG_OUTPAY 0x04 210 #define AUDIOHD_REG_INPAY 0x06 211 #define AUDIOHD_REG_GCTL 0x08 212 #define AUDIOHD_REG_WAKEEN 0x0C 213 #define AUDIOHD_REG_STATESTS 0x0E 214 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 215 216 #define AUDIOHD_REG_GSTS 0x10 217 #define AUDIOHD_REG_INTCTL 0x20 218 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 219 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 220 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 221 222 223 #define AUDIOHD_REG_INTSTS 0x24 224 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 225 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 226 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 227 228 #define AUDIOHD_REG_WALCLK 0x30 229 #define AUDIOHD_REG_SYNC 0x38 230 231 #define AUDIOHD_REG_CORBLBASE 0x40 232 #define AUDIOHD_REG_CORBUBASE 0x44 233 #define AUDIOHD_REG_CORBWP 0x48 234 #define AUDIOHD_REG_CORBRP 0x4A 235 #define AUDIOHD_REG_CORBCTL 0x4C 236 #define AUDIOHD_REG_CORBST 0x4D 237 #define AUDIOHD_REG_CORBSIZE 0x4E 238 239 #define AUDIOHD_REG_RIRBLBASE 0x50 240 #define AUDIOHD_REG_RIRBUBASE 0x54 241 #define AUDIOHD_REG_RIRBWP 0x58 242 #define AUDIOHD_REG_RINTCNT 0x5A 243 #define AUDIOHD_REG_RIRBCTL 0x5C 244 #define AUDIOHD_REG_RIRBSTS 0x5D 245 #define AUDIOHD_REG_RIRBSIZE 0x5E 246 247 #define AUDIOHD_REG_IC 0x60 248 #define AUDIOHD_REG_IR 0x64 249 #define AUDIOHD_REG_IRS 0x68 250 #define AUDIOHD_REG_DPLBASE 0x70 251 #define AUDIOHD_REG_DPUBASE 0x74 252 253 #define AUDIOHD_REG_SD_BASE 0x80 254 #define AUDIOHD_REG_SD_LEN 0x20 255 256 /* 257 * Offset of Stream Descriptor Registers 258 */ 259 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 260 #define AUDIOHD_SDREG_OFFSET_STS 0x03 261 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 262 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 263 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 264 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 265 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 266 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 267 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 268 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 269 270 /* bits for stream descriptor control reg */ 271 #define AUDIOHDR_SD_CTL_DEIE 0x000010 272 #define AUDIOHDR_SD_CTL_FEIE 0x000008 273 #define AUDIOHDR_SD_CTL_IOCE 0x000004 274 #define AUDIOHDR_SD_CTL_SRUN 0x000002 275 #define AUDIOHDR_SD_CTL_SRST 0x000001 276 #define AUDIOHDR_SD_CTL_INTS \ 277 (AUDIOHDR_SD_CTL_DEIE | \ 278 AUDIOHDR_SD_CTL_FEIE | \ 279 AUDIOHDR_SD_CTL_IOCE) 280 281 282 /* bits for stream descriptor status register */ 283 #define AUDIOHDR_SD_STS_BCIS 0x0004 284 #define AUDIOHDR_SD_STS_FIFOE 0x0008 285 #define AUDIOHDR_SD_STS_DESE 0x0010 286 #define AUDIOHDR_SD_STS_FIFORY 0x0020 287 #define AUDIOHDR_SD_STS_INTRS \ 288 (AUDIOHDR_SD_STS_BCIS | \ 289 AUDIOHDR_SD_STS_FIFOE | \ 290 AUDIOHDR_SD_STS_DESE) 291 292 293 /* bits for GCTL register */ 294 #define AUDIOHDR_GCTL_CRST 0x00000001 295 #define AUDIOHDR_GCTL_URESPE 0x00000100 296 297 /* bits for CORBRP register */ 298 #define AUDIOHDR_CORBRP_RESET 0x8000 299 #define AUDIOHDR_CORBRP_WPTR 0x00ff 300 301 /* bits for CORBCTL register */ 302 #define AUDIOHDR_CORBCTL_CMEIE 0x01 303 #define AUDIOHDR_CORBCTL_DMARUN 0x02 304 305 /* bits for CORB SIZE register */ 306 #define AUDIOHDR_CORBSZ_8 0 307 #define AUDIOHDR_CORBSZ_16 1 308 #define AUDIOHDR_CORBSZ_256 2 309 310 /* bits for RIRBCTL register */ 311 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 312 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 313 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 314 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 315 316 /* bits for RIRBWP register */ 317 #define AUDIOHDR_RIRBWP_RESET 0x8000 318 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 319 320 /* bits for RIRB SIZE register */ 321 #define AUDIOHDR_RIRBSZ_8 0 322 #define AUDIOHDR_RIRBSZ_16 1 323 #define AUDIOHDR_RIRBSZ_256 2 324 325 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 326 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 327 328 /* HD spec: ID of Root node is 0 */ 329 #define AUDIOHDC_NODE_ROOT 0x00 330 331 /* HD spec: ID of audio function group is "1" */ 332 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 333 334 /* 335 * HD audio verbs can be either 12-bit or 4-bit in length. 336 */ 337 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 338 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 339 340 #define AUDIOHDC_SAMPR48000 48000 341 #define AUDIOHDC_MAX_BEEP_GEN 12000 342 #define AUDIOHDC_MIX_BEEP_GEN 47 343 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 344 345 /* 346 * 12-bit verbs 347 */ 348 #define AUDIOHDC_VERB_GET_PARAM 0xf00 349 350 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 351 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 352 353 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 354 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 355 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 356 357 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 358 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 359 360 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 361 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 362 363 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 364 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 365 366 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 367 368 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 369 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 370 371 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 372 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 373 374 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 375 #define AUDIOHDC_VERB_SET_EAPD 0x70c 376 377 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 378 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 379 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 380 381 #define AUDIOHDC_VERB_SET_URCTRL 0x708 382 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 383 384 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 385 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 386 387 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 388 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 389 390 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 391 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 392 393 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 394 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 395 396 #define AUDIOHDC_GPIO_ENABLE 0xff 397 #define AUDIOHDC_GPIO_DIRECT 0xf1 398 399 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 400 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 401 /* 402 * 4-bit verbs 403 */ 404 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 405 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 406 407 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 408 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 409 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 410 411 /* 412 * parameters of nodes 413 */ 414 #define AUDIOHDC_PAR_VENDOR_ID 0x00 415 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 416 #define AUDIOHDC_PAR_REV_ID 0x02 417 #define AUDIOHDC_PAR_NODE_COUNT 0x04 418 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 419 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 420 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 421 #define AUDIOHDC_PAR_PCM 0x0a 422 #define AUDIOHDC_PAR_STREAM 0x0b 423 #define AUDIOHDC_PAR_PIN_CAP 0x0c 424 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 425 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 426 #define AUDIOHDC_PAR_POWER_STATE 0x0f 427 #define AUDIOHDC_PAR_PROC_CAP 0x10 428 #define AUDIOHDC_PAR_GPIO_CAP 0x11 429 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 430 431 /* 432 * bits for get/set amplifier gain/mute 433 */ 434 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 435 #define AUDIOHDC_AMP_SET_INPUT 0x4000 436 #define AUDIOHDC_AMP_SET_LEFT 0x2000 437 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 438 #define AUDIOHDC_AMP_SET_MUTE 0x0080 439 #define AUDIOHDC_AMP_SET_LNR 0x3000 440 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 441 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 442 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 443 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 444 #define AUDIOHDC_GAIN_MAX 0x7f 445 #define AUDIOHDC_GAIN_BITS 7 446 #define AUDIOHDC_GAIN_DEFAULT 0x0f 447 448 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 449 #define AUDIOHDC_AMP_GET_INPUT 0x0000 450 451 /* value used to set max volume for left output */ 452 #define AUDIOHDC_AMP_LOUT_MAX \ 453 (AUDIOHDC_AMP_SET_OUTPUT | \ 454 AUDIOHDC_AMP_SET_LEFT | \ 455 AUDIOHDC_GAIN_MAX) 456 457 /* value used to set max volume for right output */ 458 #define AUDIOHDC_AMP_ROUT_MAX \ 459 (AUDIOHDC_AMP_SET_OUTPUT | \ 460 AUDIOHDC_AMP_SET_RIGHT | \ 461 AUDIOHDC_GAIN_MAX) 462 463 464 /* 465 * Bits for pin widget control verb 466 */ 467 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 468 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 469 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 470 471 /* 472 * Bits for Amplifier capabilities 473 */ 474 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 475 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 476 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 477 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 478 479 480 /* 481 * Bits for Audio Widget Capabilities 482 */ 483 #define AUDIOHD_WIDCAP_STEREO 0x00000001 484 #define AUDIOHD_WIDCAP_INAMP 0x00000002 485 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 486 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 487 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 488 #define AUDIOHD_WIDCAP_STRIP 0x00000020 489 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 490 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 491 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 492 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 493 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 494 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 495 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 496 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 497 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 498 499 500 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 501 502 /* 503 * buffer descriptor list entry of stream descriptor 504 */ 505 typedef struct { 506 uint64_t sbde_addr; 507 uint32_t sbde_len; 508 uint32_t 509 sbde_ioc: 1, 510 reserved: 31; 511 }sd_bdle_t; 512 513 514 #define AUDIOHD_PLAY_STARTED 0x00000001 515 #define AUDIOHD_PLAY_EMPTY 0x00000002 516 #define AUDIOHD_PLAY_PAUSED 0x00000004 517 #define AUDIOHD_RECORD_STARTED 0x00000008 518 519 enum audiohda_widget_type { 520 WTYPE_AUDIO_OUT = 0, 521 WTYPE_AUDIO_IN, 522 WTYPE_AUDIO_MIX, 523 WTYPE_AUDIO_SEL, 524 WTYPE_PIN, 525 WTYPE_POWER, 526 WTYPE_VOL_KNOB, 527 WTYPE_BEEP, 528 WTYPE_VENDOR = 0xf 529 }; 530 531 enum audiohda_device_type { 532 DTYPE_LINEOUT = 0, 533 DTYPE_SPEAKER, 534 DTYPE_HP_OUT, 535 DTYPE_CD, 536 DTYPE_SPDIF_OUT, 537 DTYPE_DIGIT_OUT, 538 DTYPE_MODEM_SIDE, 539 DTYPE_MODEM_HNAD_SIDE, 540 DTYPE_LINE_IN, 541 DTYPE_AUX, 542 DTYPE_MIC_IN, 543 DTYPE_TEL, 544 DTYPE_SPDIF_IN, 545 DTYPE_DIGIT_IN, 546 DTYPE_OTHER = 0x0f, 547 }; 548 549 enum audiohd_pin_color { 550 AUDIOHD_PIN_UNKNOWN = 0, 551 AUDIOHD_PIN_BLACK, 552 AUDIOHD_PIN_GREY, 553 AUDIOHD_PIN_BLUE, 554 AUDIOHD_PIN_GREEN, 555 AUDIOHD_PIN_RED, 556 AUDIOHD_PIN_ORANGE, 557 AUDIOHD_PIN_YELLOW, 558 AUDIOHD_PIN_PURPLE, 559 AUDIOHD_PIN_PINK, 560 AUDIOHD_PIN_WHITE = 0xe, 561 AUDIOHD_PIN_OTHER = 0xf, 562 }; 563 564 #define CTRL_NUM 16 565 566 /* values for audiohd_widget.path_flags */ 567 #define AUDIOHD_PATH_DAC (1 << 0) 568 #define AUDIOHD_PATH_ADC (1 << 1) 569 #define AUDIOHD_PATH_MON (1 << 2) 570 #define AUDIOHD_PATH_NOMON (1 << 3) 571 #define AUDIOHD_PATH_BEEP (1 << 4) 572 573 typedef struct audiohd_path audiohd_path_t; 574 typedef struct audiohd_widget audiohd_widget_t; 575 typedef struct audiohd_state audiohd_state_t; 576 typedef struct audiohd_pin audiohd_pin_t; 577 typedef struct hda_codec hda_codec_t; 578 typedef uint32_t wid_t; /* id of widget */ 579 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 580 typedef enum audiohda_device_type audiohda_device_type_t; 581 typedef enum audiohd_pin_color audiohd_pin_color_t; 582 583 #define AUDIOHD_MAX_WIDGET 128 584 #define AUDIOHD_MAX_CONN 16 585 #define AUDIOHD_MAX_PINS 16 586 #define AUDIOHD_MAX_DEPTH 8 587 588 struct audiohd_entry_prop { 589 uint32_t conn_len; 590 uint32_t mask_range; 591 uint32_t mask_wid; 592 wid_t input_wid; 593 int conns_per_entry; 594 int bits_per_conn; 595 }; 596 struct audiohd_widget { 597 wid_t wid_wid; 598 hda_codec_t *codec; 599 enum audiohda_widget_type type; 600 601 uint32_t widget_cap; 602 uint32_t pcm_format; 603 uint32_t inamp_cap; 604 uint32_t outamp_cap; 605 606 uint32_t path_flags; 607 608 int out_weight; 609 int in_weight; 610 int finish; 611 612 /* 613 * wid of possible & selected input connections 614 */ 615 wid_t avail_conn[AUDIOHD_MAX_CONN]; 616 wid_t selconn; 617 /* 618 * for monitor path 619 */ 620 wid_t selmon[AUDIOHD_MAX_CONN]; 621 uint16_t used; 622 623 /* 624 * available (input) connections. 0 means this widget 625 * has fixed connection 626 */ 627 int nconns; 628 629 /* 630 * pointer to struct depending on widget type: 631 * 1. DAC audiohd_ostream_t 632 * 2. ADC audiohd_istream_t 633 * 3. PIN audiohd_pin_t 634 */ 635 void *priv; 636 }; 637 638 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 639 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 640 #define AUDIOHD_FLAG_HP (1 << 2) 641 #define AUDIOHD_FLAG_MONO (1 << 3) 642 643 #define AUDIOHD_MAX_MIXER 5 644 #define AUDIOHD_MAX_PIN 4 645 646 #define PORT_DAC 0 647 #define PORT_ADC 1 648 #define PORT_MAX 2 649 typedef enum { 650 PLAY = 0, 651 RECORD = 1, 652 BEEP = 2, 653 } path_type_t; 654 655 struct audiohd_path { 656 wid_t adda_wid; 657 wid_t beep_wid; 658 659 wid_t pin_wid[AUDIOHD_MAX_PINS]; 660 int sum_selconn[AUDIOHD_MAX_PINS]; 661 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 662 int pin_nums; 663 int maxmixer[AUDIOHD_MAX_PINS]; 664 665 path_type_t path_type; 666 667 wid_t mute_wid; 668 int mute_dir; 669 wid_t gain_wid; 670 int gain_dir; 671 uint32_t gain_bits; 672 673 uint32_t pin_outputs; 674 uint8_t tag; 675 676 hda_codec_t *codec; 677 678 wid_t sum_wid; 679 680 audiohd_state_t *statep; 681 }; 682 683 typedef struct audiohd_port 684 { 685 uint8_t nchan; 686 int index; 687 uint16_t regoff; 688 boolean_t started; 689 boolean_t triggered; 690 691 unsigned fragfr; 692 unsigned nframes; 693 uint64_t count; 694 int curpos; 695 int intrs; 696 697 uint_t format; 698 unsigned sync_dir; 699 700 ddi_dma_handle_t samp_dmah; 701 ddi_acc_handle_t samp_acch; 702 size_t samp_size; 703 caddr_t samp_kaddr; 704 uint64_t samp_paddr; 705 706 ddi_dma_handle_t bdl_dmah; 707 ddi_acc_handle_t bdl_acch; 708 size_t bdl_size; 709 caddr_t bdl_kaddr; 710 uint64_t bdl_paddr; 711 712 audio_engine_t *engine; 713 audiohd_state_t *statep; 714 }audiohd_port_t; 715 716 typedef struct audiohd_ctrl 717 { 718 audiohd_state_t *statep; 719 audio_ctrl_t *ctrl; 720 uint32_t num; 721 uint64_t val; 722 } audiohd_ctrl_t; 723 724 struct audiohd_pin { 725 audiohd_pin_t *next; 726 wid_t wid; 727 wid_t mute_wid; /* node used to mute this pin */ 728 int mute_dir; /* 1: input, 2: output */ 729 wid_t gain_wid; /* node for gain control */ 730 int gain_dir; /* _OUTPUT/_INPUT */ 731 uint32_t gain_bits; 732 733 uint8_t vrefvalue; /* value of VRef */ 734 735 uint32_t cap; 736 uint32_t config; 737 uint32_t ctrl; 738 uint32_t assoc; 739 uint32_t seq; 740 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 741 wid_t beep_wid; 742 int no_phys_conn; 743 enum audiohda_device_type device; 744 745 /* 746 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 747 * widget wid. 748 */ 749 int mg_dir[AUDIOHD_MAX_CONN]; 750 int mg_gain[AUDIOHD_MAX_CONN]; 751 int mg_wid[AUDIOHD_MAX_CONN]; 752 int num; 753 int finish; 754 755 }; 756 757 typedef struct { 758 ddi_dma_handle_t ad_dmahdl; 759 ddi_acc_handle_t ad_acchdl; 760 caddr_t ad_vaddr; /* virtual addr */ 761 uint64_t ad_paddr; /* physical addr */ 762 size_t ad_req_sz; /* required size of memory */ 763 size_t ad_real_sz; /* real size of memory */ 764 } audiohd_dma_t; 765 766 struct hda_codec { 767 uint8_t index; /* codec address */ 768 uint32_t vid; /* vendor id and device id */ 769 uint32_t revid; /* revision id */ 770 wid_t wid_afg; /* id of AFG */ 771 wid_t first_wid; /* wid of 1st subnode of AFG */ 772 wid_t last_wid; /* wid of the last subnode of AFG */ 773 int nnodes; /* # of subnodes of AFG */ 774 uint8_t nistream; 775 776 uint32_t outamp_cap; 777 uint32_t inamp_cap; 778 uint32_t stream_format; 779 uint32_t pcm_format; 780 781 audiohd_state_t *soft_statep; 782 783 /* use wid as index to the array of widget pointers */ 784 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 785 786 787 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 788 uint8_t portnum; 789 audiohd_pin_t *first_pin; 790 }; 791 792 #define AUDIOHD_MAX_ASSOC 15 793 struct audiohd_state { 794 dev_info_t *hda_dip; 795 kstat_t *hda_ksp; 796 kmutex_t hda_mutex; 797 uint32_t hda_flags; 798 799 boolean_t soft_volume; 800 801 caddr_t hda_reg_base; 802 ddi_acc_handle_t hda_pci_handle; 803 ddi_acc_handle_t hda_reg_handle; 804 805 ddi_intr_handle_t *htable; /* For array of interrupts */ 806 boolean_t intr_added; 807 int intr_type; /* What type of interrupt */ 808 int intr_rqst; /* # of request intrs count */ 809 int intr_cnt; /* # of intrs count returned */ 810 uint_t intr_pri; /* Interrupt priority */ 811 int intr_cap; /* Interrupt capabilities */ 812 boolean_t msi_enable; 813 814 audiohd_dma_t hda_dma_corb; 815 audiohd_dma_t hda_dma_rirb; 816 817 818 uint8_t hda_rirb_rp; /* read pointer for rirb */ 819 uint16_t hda_codec_mask; 820 821 822 audio_dev_t *adev; 823 uint32_t devid; 824 825 826 int hda_pint_freq; /* play intr frequence */ 827 int hda_rint_freq; /* record intr frequence */ 828 829 int hda_input_streams; /* # of input stream */ 830 int hda_output_streams; /* # of output stream */ 831 int hda_streams_nums; /* # of stream */ 832 833 uint_t hda_play_regbase; 834 uint_t hda_record_regbase; 835 836 uint_t hda_play_stag; /* tag of playback stream */ 837 uint_t hda_record_stag; /* tag of record stream */ 838 uint_t hda_play_lgain; /* left gain for playback */ 839 uint_t hda_play_rgain; /* right gain for playback */ 840 841 /* 842 * Now, for the time being, we add some fields 843 * for parsing codec topology 844 */ 845 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 846 /* 847 * Suspend/Resume used fields 848 */ 849 boolean_t suspended; 850 boolean_t monitor_unsupported; 851 852 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 853 uint8_t pathnum; 854 audiohd_port_t *port[PORT_MAX]; 855 uint8_t pchan; 856 uint8_t rchan; 857 858 uint64_t inmask; 859 860 uint_t hda_out_ports; 861 uint_t in_port; 862 863 /* 864 * Controls 865 */ 866 audiohd_ctrl_t *controls[CTRL_NUM]; 867 868 /* for multichannel */ 869 uint8_t chann[AUDIOHD_MAX_ASSOC]; 870 uint8_t assoc; 871 872 }; 873 874 875 /* 876 * Operation for high definition audio control system bus 877 * interface registers 878 */ 879 #define AUDIOHD_REG_GET8(reg) \ 880 ddi_get8(statep->hda_reg_handle, \ 881 (void *)((char *)statep->hda_reg_base + (reg))) 882 883 #define AUDIOHD_REG_GET16(reg) \ 884 ddi_get16(statep->hda_reg_handle, \ 885 (void *)((char *)statep->hda_reg_base + (reg))) 886 887 #define AUDIOHD_REG_GET32(reg) \ 888 ddi_get32(statep->hda_reg_handle, \ 889 (void *)((char *)statep->hda_reg_base + (reg))) 890 891 #define AUDIOHD_REG_GET64(reg) \ 892 ddi_get64(statep->hda_reg_handle, \ 893 (void *)((char *)statep->hda_reg_base + (reg))) 894 895 #define AUDIOHD_REG_SET8(reg, val) \ 896 ddi_put8(statep->hda_reg_handle, \ 897 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 898 899 #define AUDIOHD_REG_SET16(reg, val) \ 900 ddi_put16(statep->hda_reg_handle, \ 901 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 902 903 #define AUDIOHD_REG_SET32(reg, val) \ 904 ddi_put32(statep->hda_reg_handle, \ 905 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 906 907 #define AUDIOHD_REG_SET64(reg, val) \ 908 ddi_put64(statep->hda_reg_handle, \ 909 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 910 911 912 /* 913 * enable a pin widget to output 914 */ 915 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 916 { \ 917 uint32_t lTmp; \ 918 \ 919 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 920 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 921 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 922 return (DDI_FAILURE); \ 923 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 924 AUDIOHDC_VERB_SET_PIN_CTRL, \ 925 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 926 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 927 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 928 return (DDI_FAILURE); \ 929 } 930 931 /* 932 * disable output pin 933 */ 934 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 935 { \ 936 uint32_t lTmp; \ 937 \ 938 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 939 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 940 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 941 return (DDI_FAILURE); \ 942 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 943 AUDIOHDC_VERB_SET_PIN_CTRL, \ 944 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 945 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 946 return (DDI_FAILURE); \ 947 } 948 949 /* 950 * enable a pin widget to input 951 */ 952 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 953 { \ 954 (void) audioha_codec_verb_get(statep, caddr, wid, \ 955 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 956 } 957 958 959 /* 960 * disable input pin 961 */ 962 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 963 { \ 964 uint32_t lTmp; \ 965 \ 966 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 967 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 968 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 969 return (DDI_FAILURE); \ 970 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 971 AUDIOHDC_VERB_SET_PIN_CTRL, \ 972 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 973 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 974 return (DDI_FAILURE); \ 975 } 976 977 /* 978 * unmute an output pin 979 */ 980 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 981 { \ 982 if (audioha_codec_4bit_verb_get(statep, \ 983 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 984 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 985 AUDIOHD_CODEC_FAILURE) \ 986 return (DDI_FAILURE); \ 987 } 988 989 /* 990 * check volume adjust value of 2 channels control 991 */ 992 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 993 { \ 994 if ((value) & ~0xffff) \ 995 return (EINVAL); \ 996 if ((((value) & 0xff00) >> 8) > 100 || \ 997 ((value) & 0xff) > 100) \ 998 return (EINVAL); \ 999 } 1000 1001 /* 1002 * check volume adjust value of mono channel control 1003 */ 1004 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 1005 { \ 1006 if ((value) & ~0xff) \ 1007 return (EINVAL); \ 1008 if (((value) & 0xff) > 100) \ 1009 return (EINVAL); \ 1010 } 1011 1012 #ifdef __cplusplus 1013 } 1014 #endif 1015 1016 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 1017