xref: /illumos-gate/usr/src/cmd/fm/modules/common/fabric-xlate/fx_fabric.c (revision 5f8171005a0c33f3c67f7da52d41c2362c3fd891)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 #include <stddef.h>
27 #include <strings.h>
28 #include <sys/fm/util.h>
29 
30 #include "fabric-xlate.h"
31 
32 #define	FAB_LOOKUP(sz, name, field) \
33 	(void) nvlist_lookup_uint ## sz(nvl, name, field)
34 
35 static boolean_t fab_xlate_fake_rp = B_TRUE;
36 static fab_err_tbl_t *fab_master_err_tbl;
37 
38 /*
39  * Translation tables for converting "fabric" error bits into "pci" ereports.
40  * <Ereport Class Name>, <Error Bit Mask>, <Preparation Function>
41  */
42 
43 /* MACRO for table entries with no TGT ereports */
44 #define	NT(class, bit, prep) class, bit, prep, NULL
45 /* Translate Fabric ereports to ereport.io.pci.* */
46 fab_erpt_tbl_t fab_pci_erpt_tbl[] = {
47 	PCI_DET_PERR,		PCI_STAT_PERROR,	NULL,
48 	PCI_MDPE,		PCI_STAT_S_PERROR,	NULL,
49 	PCI_SIG_SERR,		PCI_STAT_S_SYSERR,	NULL,
50 	PCI_MA,			PCI_STAT_R_MAST_AB,	NULL,
51 	PCI_REC_TA,		PCI_STAT_R_TARG_AB,	NULL,
52 	PCI_SIG_TA,		PCI_STAT_S_TARG_AB,	NULL,
53 	NULL, NULL, NULL
54 };
55 
56 /* Translate Fabric ereports to ereport.io.pci.sec-* */
57 static fab_erpt_tbl_t fab_pci_bdg_erpt_tbl[] = {
58 	PCI_DET_PERR,		PCI_STAT_PERROR,	NULL,
59 	PCI_MDPE,		PCI_STAT_S_PERROR,	NULL,
60 	PCI_REC_SERR,		PCI_STAT_S_SYSERR,	NULL,
61 #ifdef sparc
62 	PCI_MA,			PCI_STAT_R_MAST_AB,	NULL,
63 #endif
64 	PCI_REC_TA,		PCI_STAT_R_TARG_AB,	NULL,
65 	PCI_SIG_TA,		PCI_STAT_S_TARG_AB,	NULL,
66 	NULL, NULL, NULL, NULL,
67 };
68 
69 
70 /* Translate Fabric ereports to ereport.io.pci.dto */
71 static fab_erpt_tbl_t fab_pci_bdg_ctl_erpt_tbl[] = {
72 	PCI_DTO,	PCI_BCNF_BCNTRL_DTO_STAT,	NULL,
73 	NULL, NULL, NULL
74 };
75 
76 /* Translate Fabric ereports to ereport.io.pciex.* */
77 static fab_erpt_tbl_t fab_pcie_ce_erpt_tbl[] = {
78 	PCIEX_RE,	PCIE_AER_CE_RECEIVER_ERR,	NULL,
79 	PCIEX_RNR,	PCIE_AER_CE_REPLAY_ROLLOVER,	NULL,
80 	PCIEX_RTO,	PCIE_AER_CE_REPLAY_TO,		NULL,
81 	PCIEX_BDP,	PCIE_AER_CE_BAD_DLLP,		NULL,
82 	PCIEX_BTP,	PCIE_AER_CE_BAD_TLP,		NULL,
83 	PCIEX_ANFE,	PCIE_AER_CE_AD_NFE,		NULL,
84 	NULL, NULL, NULL
85 };
86 
87 /*
88  * Translate Fabric ereports to ereport.io.pciex.*
89  * The Target Ereports for this section is only used on leaf devices, with the
90  * exception of TO
91  */
92 static fab_erpt_tbl_t fab_pcie_ue_erpt_tbl[] = {
93 	PCIEX_TE,	PCIE_AER_UCE_TRAINING,		NULL,
94 	PCIEX_DLP,	PCIE_AER_UCE_DLP,		NULL,
95 	PCIEX_SD,	PCIE_AER_UCE_SD,		NULL,
96 	PCIEX_ROF,	PCIE_AER_UCE_RO,		NULL,
97 	PCIEX_FCP,	PCIE_AER_UCE_FCP,		NULL,
98 	PCIEX_MFP,	PCIE_AER_UCE_MTLP,		NULL,
99 	PCIEX_CTO,	PCIE_AER_UCE_TO,		PCI_TARG_MA,
100 	PCIEX_UC,	PCIE_AER_UCE_UC,		NULL,
101 	PCIEX_ECRC,	PCIE_AER_UCE_ECRC,		NULL,
102 	PCIEX_CA,	PCIE_AER_UCE_CA,		PCI_TARG_REC_TA,
103 #ifdef sparc
104 	PCIEX_UR,	PCIE_AER_UCE_UR,		PCI_TARG_MA,
105 #endif
106 	PCIEX_POIS,	PCIE_AER_UCE_PTLP,		PCI_TARG_MDPE,
107 	NULL, NULL, NULL
108 };
109 
110 /* Translate Fabric ereports to ereport.io.pciex.* */
111 static fab_erpt_tbl_t fab_pcie_sue_erpt_tbl[] = {
112 	PCIEX_S_TA_SC,	PCIE_AER_SUCE_TA_ON_SC,		PCI_TARG_REC_TA,
113 	PCIEX_S_MA_SC,	PCIE_AER_SUCE_MA_ON_SC,		PCI_TARG_MA,
114 	PCIEX_S_RTA,	PCIE_AER_SUCE_RCVD_TA,		PCI_TARG_REC_TA,
115 #ifdef sparc
116 	PCIEX_S_RMA,	PCIE_AER_SUCE_RCVD_MA,		PCI_TARG_MA,
117 #endif
118 	PCIEX_S_USC,	PCIE_AER_SUCE_USC_ERR,		NULL,
119 	PCIEX_S_USCMD,	PCIE_AER_SUCE_USC_MSG_DATA_ERR,	PCI_TARG_REC_TA,
120 	PCIEX_S_UDE,	PCIE_AER_SUCE_UC_DATA_ERR,	PCI_TARG_MDPE,
121 	PCIEX_S_UAT,	PCIE_AER_SUCE_UC_ATTR_ERR,	PCI_TARG_MDPE,
122 	PCIEX_S_UADR,	PCIE_AER_SUCE_UC_ADDR_ERR,	PCI_TARG_MDPE,
123 	PCIEX_S_TEX,	PCIE_AER_SUCE_TIMER_EXPIRED,	NULL,
124 	PCIEX_S_PERR,	PCIE_AER_SUCE_PERR_ASSERT,	PCI_TARG_MDPE,
125 	PCIEX_S_SERR,	PCIE_AER_SUCE_SERR_ASSERT,	NULL,
126 	PCIEX_INTERR,	PCIE_AER_SUCE_INTERNAL_ERR,	NULL,
127 	NULL, NULL, NULL
128 };
129 
130 /* Translate Fabric ereports to ereport.io.pcix.* */
131 static fab_erpt_tbl_t fab_pcix_erpt_tbl[] = {
132 	PCIX_SPL_DIS,		PCI_PCIX_SPL_DSCD,	NULL,
133 	PCIX_UNEX_SPL,		PCI_PCIX_UNEX_SPL,	NULL,
134 	PCIX_RX_SPL_MSG,	PCI_PCIX_RX_SPL_MSG,	NULL,
135 	NULL, NULL, NULL
136 };
137 static fab_erpt_tbl_t *fab_pcix_bdg_erpt_tbl = fab_pcix_erpt_tbl;
138 
139 /* Translate Fabric ereports to ereport.io.pcix.sec-* */
140 static fab_erpt_tbl_t fab_pcix_bdg_sec_erpt_tbl[] = {
141 	PCIX_SPL_DIS,		PCI_PCIX_BSS_SPL_DSCD,	NULL,
142 	PCIX_UNEX_SPL,		PCI_PCIX_BSS_UNEX_SPL,	NULL,
143 	PCIX_BSS_SPL_OR,	PCI_PCIX_BSS_SPL_OR,	NULL,
144 	PCIX_BSS_SPL_DLY,	PCI_PCIX_BSS_SPL_DLY,	NULL,
145 	NULL, NULL, NULL
146 };
147 
148 /* Translate Fabric ereports to ereport.io.pciex.* */
149 static fab_erpt_tbl_t fab_pcie_nadv_erpt_tbl[] = {
150 #ifdef sparc
151 	PCIEX_UR,		PCIE_DEVSTS_UR_DETECTED,	NULL,
152 #endif
153 	PCIEX_FAT,		PCIE_DEVSTS_FE_DETECTED,	NULL,
154 	PCIEX_NONFAT,		PCIE_DEVSTS_NFE_DETECTED,	NULL,
155 	PCIEX_CORR,		PCIE_DEVSTS_CE_DETECTED,	NULL,
156 	NULL, NULL, NULL
157 };
158 
159 /* Translate Fabric ereports to ereport.io.pciex.* */
160 static fab_erpt_tbl_t fab_pcie_rc_erpt_tbl[] = {
161 	PCIEX_RC_FE_MSG,	PCIE_AER_RE_STS_FE_MSGS_RCVD,	NULL,
162 	PCIEX_RC_NFE_MSG,	PCIE_AER_RE_STS_NFE_MSGS_RCVD,	NULL,
163 	PCIEX_RC_CE_MSG,	PCIE_AER_RE_STS_CE_RCVD,	NULL,
164 	PCIEX_RC_MCE_MSG,	PCIE_AER_RE_STS_MUL_CE_RCVD,	NULL,
165 	PCIEX_RC_MUE_MSG,	PCIE_AER_RE_STS_MUL_FE_NFE_RCVD, NULL,
166 	NULL, NULL, NULL
167 };
168 
169 /*
170  * Translate Fabric ereports to pseudo ereport.io.pciex.* RC Fabric Messages.
171  * If the RP is not a PCIe compliant RP or does not support AER, rely on the
172  * leaf fabric ereport to help create a xxx_MSG ereport coming from the RC.
173  */
174 static fab_erpt_tbl_t fab_pcie_fake_rc_erpt_tbl[] = {
175 	PCIEX_RC_FE_MSG,	PCIE_DEVSTS_FE_DETECTED,	NULL,
176 	PCIEX_RC_NFE_MSG,	PCIE_DEVSTS_NFE_DETECTED,	NULL,
177 	PCIEX_RC_CE_MSG,	PCIE_DEVSTS_CE_DETECTED,	NULL,
178 	NULL, NULL, NULL,
179 };
180 
181 /* ARGSUSED */
182 void
183 fab_pci_fabric_to_data(fmd_hdl_t *hdl, nvlist_t *nvl, fab_data_t *data)
184 {
185 	data->nvl = nvl;
186 
187 	/* Generic PCI device information */
188 	FAB_LOOKUP(16,	"bdf",			&data->bdf);
189 	FAB_LOOKUP(16,	"device_id",		&data->device_id);
190 	FAB_LOOKUP(16,	"vendor_id",		&data->vendor_id);
191 	FAB_LOOKUP(8,	"rev_id",		&data->rev_id);
192 	FAB_LOOKUP(16,	"dev_type",		&data->dev_type);
193 	FAB_LOOKUP(16,	"pcie_off",		&data->pcie_off);
194 	FAB_LOOKUP(16,	"pcix_off",		&data->pcix_off);
195 	FAB_LOOKUP(16,	"aer_off",		&data->aer_off);
196 	FAB_LOOKUP(16,	"ecc_ver",		&data->ecc_ver);
197 
198 	/* Misc ereport information */
199 	FAB_LOOKUP(32,	"remainder",		&data->remainder);
200 	FAB_LOOKUP(32,	"severity",		&data->severity);
201 
202 	/* PCI registers */
203 	FAB_LOOKUP(16,	"pci_status",		&data->pci_err_status);
204 	FAB_LOOKUP(16,	"pci_command",		&data->pci_cfg_comm);
205 
206 	/* PCI bridge registers */
207 	FAB_LOOKUP(16,	"pci_bdg_sec_status",	&data->pci_bdg_sec_stat);
208 	FAB_LOOKUP(16,	"pci_bdg_ctrl",		&data->pci_bdg_ctrl);
209 
210 	/* PCIx registers */
211 	FAB_LOOKUP(32,	"pcix_status",		&data->pcix_status);
212 	FAB_LOOKUP(16,	"pcix_command",		&data->pcix_command);
213 
214 	/* PCIx ECC Registers */
215 	FAB_LOOKUP(16,	"pcix_ecc_control_0",	&data->pcix_ecc_control_0);
216 	FAB_LOOKUP(16,	"pcix_ecc_status_0",	&data->pcix_ecc_status_0);
217 	FAB_LOOKUP(32,	"pcix_ecc_fst_addr_0",	&data->pcix_ecc_fst_addr_0);
218 	FAB_LOOKUP(32,	"pcix_ecc_sec_addr_0",	&data->pcix_ecc_sec_addr_0);
219 	FAB_LOOKUP(32,	"pcix_ecc_attr_0",	&data->pcix_ecc_attr_0);
220 
221 	/* PCIx ECC Bridge Registers */
222 	FAB_LOOKUP(16,	"pcix_ecc_control_1",	&data->pcix_ecc_control_1);
223 	FAB_LOOKUP(16,	"pcix_ecc_status_1",	&data->pcix_ecc_status_1);
224 	FAB_LOOKUP(32,	"pcix_ecc_fst_addr_1",	&data->pcix_ecc_fst_addr_1);
225 	FAB_LOOKUP(32,	"pcix_ecc_sec_addr_1",	&data->pcix_ecc_sec_addr_1);
226 	FAB_LOOKUP(32,	"pcix_ecc_attr_1",	&data->pcix_ecc_attr_1);
227 
228 	/* PCIx Bridge */
229 	FAB_LOOKUP(32,	"pcix_bdg_status",	&data->pcix_bdg_stat);
230 	FAB_LOOKUP(16,	"pcix_bdg_sec_status",	&data->pcix_bdg_sec_stat);
231 
232 	/* PCIe registers */
233 	FAB_LOOKUP(16,	"pcie_status",		&data->pcie_err_status);
234 	FAB_LOOKUP(16,	"pcie_command",		&data->pcie_err_ctl);
235 	FAB_LOOKUP(32,	"pcie_dev_cap",		&data->pcie_dev_cap);
236 
237 	/* PCIe AER registers */
238 	FAB_LOOKUP(32,	"pcie_adv_ctl",		&data->pcie_adv_ctl);
239 	FAB_LOOKUP(32,	"pcie_ue_status",	&data->pcie_ue_status);
240 	FAB_LOOKUP(32,	"pcie_ue_mask",		&data->pcie_ue_mask);
241 	FAB_LOOKUP(32,	"pcie_ue_sev",		&data->pcie_ue_sev);
242 	FAB_LOOKUP(32,	"pcie_ue_hdr0",		&data->pcie_ue_hdr[0]);
243 	FAB_LOOKUP(32,	"pcie_ue_hdr1",		&data->pcie_ue_hdr[1]);
244 	FAB_LOOKUP(32,	"pcie_ue_hdr2",		&data->pcie_ue_hdr[2]);
245 	FAB_LOOKUP(32,	"pcie_ue_hdr3",		&data->pcie_ue_hdr[3]);
246 	FAB_LOOKUP(32,	"pcie_ce_status",	&data->pcie_ce_status);
247 	FAB_LOOKUP(32,	"pcie_ce_mask",		&data->pcie_ce_mask);
248 	FAB_LOOKUP(32,	"pcie_ue_tgt_trans",	&data->pcie_ue_tgt_trans);
249 	FAB_LOOKUP(64,	"pcie_ue_tgt_addr",	&data->pcie_ue_tgt_addr);
250 	FAB_LOOKUP(16,	"pcie_ue_tgt_bdf",	&data->pcie_ue_tgt_bdf);
251 
252 	/* PCIe BDG AER registers */
253 	FAB_LOOKUP(32,	"pcie_sue_adv_ctl",	&data->pcie_sue_ctl);
254 	FAB_LOOKUP(32,	"pcie_sue_status",	&data->pcie_sue_status);
255 	FAB_LOOKUP(32,	"pcie_sue_mask",	&data->pcie_sue_mask);
256 	FAB_LOOKUP(32,	"pcie_sue_sev",		&data->pcie_sue_sev);
257 	FAB_LOOKUP(32,	"pcie_sue_hdr0",	&data->pcie_sue_hdr[0]);
258 	FAB_LOOKUP(32,	"pcie_sue_hdr1",	&data->pcie_sue_hdr[1]);
259 	FAB_LOOKUP(32,	"pcie_sue_hdr2",	&data->pcie_sue_hdr[2]);
260 	FAB_LOOKUP(32,	"pcie_sue_hdr3",	&data->pcie_sue_hdr[3]);
261 	FAB_LOOKUP(32,	"pcie_sue_tgt_trans",	&data->pcie_sue_tgt_trans);
262 	FAB_LOOKUP(64,	"pcie_sue_tgt_addr",	&data->pcie_sue_tgt_addr);
263 	FAB_LOOKUP(16,	"pcie_sue_tgt_bdf",	&data->pcie_sue_tgt_bdf);
264 
265 	/* PCIe RP registers */
266 	FAB_LOOKUP(32,	"pcie_rp_status",	&data->pcie_rp_status);
267 	FAB_LOOKUP(16,	"pcie_rp_control",	&data->pcie_rp_ctl);
268 
269 	/* PCIe RP AER registers */
270 	FAB_LOOKUP(32,	"pcie_adv_rp_status",	&data->pcie_rp_err_status);
271 	FAB_LOOKUP(32,	"pcie_adv_rp_command",	&data->pcie_rp_err_cmd);
272 	FAB_LOOKUP(16,	"pcie_adv_rp_ce_src_id", &data->pcie_rp_ce_src_id);
273 	FAB_LOOKUP(16,	"pcie_adv_rp_ue_src_id", &data->pcie_rp_ue_src_id);
274 
275 	/*
276 	 * If the system has a PCIe complaint RP with AER, turn off translating
277 	 * fake RP ereports.
278 	 */
279 	if (fab_xlate_fake_rp &&
280 	    (data->dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) &&
281 	    data->aer_off)
282 		fab_xlate_fake_rp = B_FALSE;
283 }
284 
285 static int
286 fab_prep_pci_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
287     fab_erpt_tbl_t *tbl)
288 {
289 	const char *class = tbl->err_class;
290 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
291 
292 	/* Generate an ereport for this error bit. */
293 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
294 	    PCI_ERROR_SUBCLASS, class);
295 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
296 
297 	(void) nvlist_add_uint16(erpt, PCI_CONFIG_STATUS, data->pci_err_status);
298 	(void) nvlist_add_uint16(erpt, PCI_CONFIG_COMMAND, data->pci_cfg_comm);
299 
300 	return (err);
301 }
302 
303 static int
304 fab_prep_pci_bdg_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
305     fab_erpt_tbl_t *tbl)
306 {
307 	const char *class = tbl->err_class;
308 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
309 
310 	/* Generate an ereport for this error bit. */
311 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s-%s",
312 	    PCI_ERROR_SUBCLASS, PCI_SEC_ERROR_SUBCLASS, class);
313 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
314 
315 	(void) nvlist_add_uint16(erpt, PCI_SEC_CONFIG_STATUS,
316 	    data->pci_bdg_sec_stat);
317 	(void) nvlist_add_uint16(erpt, PCI_BCNTRL, data->pci_bdg_ctrl);
318 
319 	return (err);
320 }
321 
322 static int
323 fab_prep_pci_bdg_ctl_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
324     fab_erpt_tbl_t *tbl)
325 {
326 	const char *class = tbl->err_class;
327 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
328 
329 	/* Generate an ereport for this error bit. */
330 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
331 	    PCI_ERROR_SUBCLASS, class);
332 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
333 
334 	(void) nvlist_add_uint16(erpt, PCI_SEC_CONFIG_STATUS,
335 	    data->pci_bdg_sec_stat);
336 	(void) nvlist_add_uint16(erpt, PCI_BCNTRL, data->pci_bdg_ctrl);
337 
338 	return (err);
339 }
340 
341 
342 static int
343 fab_prep_pcie_ce_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
344     fab_erpt_tbl_t *tbl)
345 {
346 	const char *class = tbl->err_class;
347 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
348 
349 	/* Generate an ereport for this error bit. */
350 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
351 	    PCIEX_ERROR_SUBCLASS, class);
352 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
353 
354 	(void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
355 	(void) nvlist_add_uint32(erpt, PCIEX_CE_STATUS_REG,
356 	    data->pcie_ce_status);
357 
358 	return (err);
359 }
360 
361 static int
362 fab_prep_pcie_ue_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
363     fab_erpt_tbl_t *tbl)
364 {
365 	const char *class = tbl->err_class;
366 	uint32_t first_err = 1 << (data->pcie_adv_ctl &
367 	    PCIE_AER_CTL_FST_ERR_PTR_MASK);
368 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
369 
370 	/* Generate an ereport for this error bit. */
371 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
372 	    PCIEX_ERROR_SUBCLASS, class);
373 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
374 
375 	(void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
376 	(void) nvlist_add_uint32(erpt, PCIEX_UE_STATUS_REG,
377 	    data->pcie_ue_status);
378 	(void) nvlist_add_uint32(erpt, PCIEX_UE_SEV_REG, data->pcie_ue_sev);
379 	(void) nvlist_add_uint32(erpt, PCIEX_ADV_CTL, data->pcie_adv_ctl);
380 
381 	fmd_hdl_debug(hdl, "Bit 0x%x First Err 0x%x", tbl->reg_bit, first_err);
382 
383 	if ((tbl->reg_bit == first_err) && data->pcie_ue_tgt_bdf) {
384 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
385 		    data->pcie_ue_tgt_bdf);
386 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
387 	} else {
388 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, 0);
389 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_FALSE);
390 	}
391 
392 	if ((tbl->reg_bit == first_err) && !data->pcie_ue_no_tgt_erpt &&
393 	    data->pcie_ue_tgt_trans) {
394 		if (tbl->tgt_class)
395 			fab_send_tgt_erpt(hdl, data, tbl->tgt_class, B_TRUE);
396 	}
397 
398 	return (err);
399 }
400 
401 static int
402 fab_prep_pcie_sue_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
403     fab_erpt_tbl_t *tbl)
404 {
405 	const char *class = tbl->err_class;
406 	uint32_t first_err = 1 << (data->pcie_sue_ctl &
407 	    PCIE_AER_SCTL_FST_ERR_PTR_MASK);
408 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
409 
410 	/* Generate an ereport for this error bit. */
411 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
412 	    PCIEX_ERROR_SUBCLASS, class);
413 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
414 
415 	(void) nvlist_add_uint32(erpt, PCIEX_SEC_UE_STATUS,
416 	    data->pcie_sue_status);
417 
418 	fmd_hdl_debug(hdl, "Bit 0x%x First Err 0x%x", tbl->reg_bit, first_err);
419 
420 	if ((tbl->reg_bit == first_err) && data->pcie_sue_tgt_bdf) {
421 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
422 		    data->pcie_sue_tgt_bdf);
423 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
424 	} else {
425 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, 0);
426 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_FALSE);
427 	}
428 
429 	if ((tbl->reg_bit == first_err) && !data->pcie_ue_no_tgt_erpt &&
430 	    data->pcie_sue_tgt_trans) {
431 		if (tbl->tgt_class)
432 			fab_send_tgt_erpt(hdl, data, tbl->tgt_class, B_FALSE);
433 	}
434 
435 	return (err);
436 }
437 
438 static int
439 fab_prep_pcix_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
440     fab_erpt_tbl_t *tbl)
441 {
442 	const char *class = tbl->err_class;
443 	int err = 0;
444 
445 	/* Only send if this is not a bridge */
446 	if (!data->pcix_status || data->pcix_bdg_sec_stat)
447 		return (1);
448 
449 	err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
450 
451 	/* Generate an ereport for this error bit. */
452 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
453 	    PCIX_ERROR_SUBCLASS, class);
454 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
455 
456 	(void) nvlist_add_uint8(erpt, PCIX_COMMAND, data->pcix_command);
457 	(void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
458 
459 	return (err);
460 }
461 
462 static void
463 fab_send_pcix_ecc_erpt(fmd_hdl_t *hdl, fab_data_t *data)
464 {
465 	nvlist_t *erpt;
466 	int ecc_phase = (data->pcix_ecc_status_0 & PCI_PCIX_ECC_PHASE) >> 0x4;
467 	int ecc_corr = data->pcix_ecc_status_0 & PCI_PCIX_ECC_CORR;
468 	int sec_ue = data->pcix_ecc_status_0 & PCI_PCIX_ECC_S_UE;
469 	int sec_ce = data->pcix_ecc_status_0 & PCI_PCIX_ECC_S_CE;
470 	uint32_t ctlstat = (data->pcix_ecc_control_0 << 16) |
471 	    data->pcix_ecc_status_0;
472 
473 	switch (ecc_phase) {
474 	case PCI_PCIX_ECC_PHASE_NOERR:
475 		break;
476 	case PCI_PCIX_ECC_PHASE_FADDR:
477 	case PCI_PCIX_ECC_PHASE_SADDR:
478 		(void) snprintf(fab_buf, FM_MAX_CLASS,
479 		    "%s.%s", PCIX_ERROR_SUBCLASS,
480 		    ecc_corr ? PCIX_ECC_CE_ADDR : PCIX_ECC_UE_ADDR);
481 		break;
482 	case PCI_PCIX_ECC_PHASE_ATTR:
483 		(void) snprintf(fab_buf, FM_MAX_CLASS,
484 		    "%s.%s", PCIX_ERROR_SUBCLASS,
485 		    ecc_corr ? PCIX_ECC_CE_ATTR : PCIX_ECC_UE_ATTR);
486 		break;
487 	case PCI_PCIX_ECC_PHASE_DATA32:
488 	case PCI_PCIX_ECC_PHASE_DATA64:
489 		(void) snprintf(fab_buf, FM_MAX_CLASS,
490 		    "%s.%s", PCIX_ERROR_SUBCLASS,
491 		    ecc_corr ? PCIX_ECC_CE_DATA : PCIX_ECC_UE_DATA);
492 		break;
493 	}
494 
495 	if (ecc_phase) {
496 		if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
497 			goto done;
498 		(void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
499 		(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
500 		(void) nvlist_add_uint16(erpt, PCIX_COMMAND,
501 		    data->pcix_command);
502 		(void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
503 		(void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
504 		(void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
505 		    data->pcix_ecc_attr_0);
506 		fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
507 		fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
508 		if (fmd_xprt_error(hdl, fab_fmd_xprt))
509 			fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
510 	}
511 
512 	if (sec_ce || sec_ue) {
513 		(void) snprintf(fab_buf, FM_MAX_CLASS,
514 		    "%s.%s", PCIX_ERROR_SUBCLASS,
515 		    sec_ce ? PCIX_ECC_S_CE : PCIX_ECC_S_UE);
516 		if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
517 			goto done;
518 		(void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
519 		(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
520 		(void) nvlist_add_uint16(erpt, PCIX_COMMAND,
521 		    data->pcix_command);
522 		(void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
523 		(void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
524 		(void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
525 		    data->pcix_ecc_attr_0);
526 		fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
527 		fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
528 		if (fmd_xprt_error(hdl, fab_fmd_xprt))
529 			fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
530 	}
531 
532 	return;
533 done:
534 	fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
535 }
536 
537 static int
538 fab_prep_pcix_bdg_sec_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
539     fab_erpt_tbl_t *tbl)
540 {
541 	const char *class = tbl->err_class;
542 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
543 
544 	/* Generate an ereport for this error bit. */
545 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s%s",
546 	    PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS, class);
547 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
548 
549 	(void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
550 	    data->pcix_bdg_sec_stat);
551 	(void) nvlist_add_uint32(erpt, PCIX_BDG_STAT, data->pcix_bdg_stat);
552 
553 	return (err);
554 }
555 
556 static int
557 fab_prep_pcix_bdg_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
558     fab_erpt_tbl_t *tbl)
559 {
560 	const char *class = tbl->err_class;
561 	int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
562 
563 	/* Generate an ereport for this error bit. */
564 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
565 	    PCIX_ERROR_SUBCLASS, class);
566 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
567 
568 	(void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
569 	    data->pcix_bdg_sec_stat);
570 	(void) nvlist_add_uint32(erpt, PCIX_BDG_STAT, data->pcix_bdg_stat);
571 
572 	return (err);
573 }
574 
575 static void
576 fab_send_pcix_bdg_ecc_erpt(fmd_hdl_t *hdl, fab_data_t *data)
577 {
578 	nvlist_t *erpt;
579 	int ecc_phase = (data->pcix_ecc_status_1 & PCI_PCIX_ECC_PHASE) >> 0x4;
580 	int ecc_corr = data->pcix_ecc_status_1 & PCI_PCIX_ECC_CORR;
581 	int sec_ue = data->pcix_ecc_status_1 & PCI_PCIX_ECC_S_UE;
582 	int sec_ce = data->pcix_ecc_status_1 & PCI_PCIX_ECC_S_CE;
583 	uint32_t ctlstat = (data->pcix_ecc_control_1 << 16) |
584 	    data->pcix_ecc_status_1;
585 
586 	switch (ecc_phase) {
587 	case PCI_PCIX_ECC_PHASE_NOERR:
588 		break;
589 	case PCI_PCIX_ECC_PHASE_FADDR:
590 	case PCI_PCIX_ECC_PHASE_SADDR:
591 		(void) snprintf(fab_buf, FM_MAX_CLASS,
592 		    "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
593 		    ecc_corr ? PCIX_ECC_CE_ADDR : PCIX_ECC_UE_ADDR);
594 		break;
595 	case PCI_PCIX_ECC_PHASE_ATTR:
596 		(void) snprintf(fab_buf, FM_MAX_CLASS,
597 		    "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
598 		    ecc_corr ? PCIX_ECC_CE_ATTR : PCIX_ECC_UE_ATTR);
599 		break;
600 	case PCI_PCIX_ECC_PHASE_DATA32:
601 	case PCI_PCIX_ECC_PHASE_DATA64:
602 		(void) snprintf(fab_buf, FM_MAX_CLASS,
603 		    "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
604 		    ecc_corr ? PCIX_ECC_CE_DATA : PCIX_ECC_UE_DATA);
605 		break;
606 	}
607 	if (ecc_phase) {
608 		if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
609 			goto done;
610 		(void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
611 		(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
612 		(void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
613 		    data->pcix_bdg_sec_stat);
614 		(void) nvlist_add_uint32(erpt, PCIX_BDG_STAT,
615 		    data->pcix_bdg_stat);
616 		(void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
617 		(void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
618 		    data->pcix_ecc_attr_1);
619 		fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
620 		fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
621 		if (fmd_xprt_error(hdl, fab_fmd_xprt))
622 			fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
623 	}
624 
625 	if (sec_ce || sec_ue) {
626 		(void) snprintf(fab_buf, FM_MAX_CLASS,
627 		    "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
628 		    sec_ce ? PCIX_ECC_S_CE : PCIX_ECC_S_UE);
629 		if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
630 			goto done;
631 		(void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
632 		(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
633 		(void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
634 		    data->pcix_bdg_sec_stat);
635 		(void) nvlist_add_uint32(erpt, PCIX_BDG_STAT,
636 		    data->pcix_bdg_stat);
637 		(void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
638 		(void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
639 		    data->pcix_ecc_attr_1);
640 		fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
641 		fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
642 		if (fmd_xprt_error(hdl, fab_fmd_xprt))
643 			fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
644 	}
645 	return;
646 done:
647 	fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
648 }
649 
650 static int
651 fab_prep_pcie_nadv_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
652     fab_erpt_tbl_t *tbl)
653 {
654 	const char *class = tbl->err_class;
655 	int err = 0;
656 
657 	/* Don't send this for PCI device, Root Ports, or PCIe with AER */
658 	if ((data->dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV) ||
659 	    (data->dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
660 	    data->aer_off)
661 		return (1);
662 
663 	err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
664 
665 	/* Generate an ereport for this error bit. */
666 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
667 	    PCIEX_ERROR_SUBCLASS, class);
668 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
669 
670 	(void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
671 
672 	return (err);
673 }
674 
675 static int
676 fab_prep_pcie_rc_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
677     fab_erpt_tbl_t *tbl)
678 {
679 	const char *class = tbl->err_class;
680 	uint32_t status = data->pcie_rp_err_status;
681 	int err = 0;
682 	int isFE = 0, isNFE = 0;
683 
684 	fmd_hdl_debug(hdl, "XLATE RP Error Class %s", class);
685 
686 	if (!data->aer_off)
687 		return (-1);
688 
689 	/* Only send a FE Msg if the 1st UE error is FE */
690 	if (STRCMP(class, PCIEX_RC_FE_MSG))
691 		if (!(status & PCIE_AER_RE_STS_FIRST_UC_FATAL))
692 			return (-1);
693 		else
694 			isFE = 1;
695 
696 	/* Only send a NFE Msg is the 1st UE error is NFE */
697 	if (STRCMP(class, PCIEX_RC_NFE_MSG))
698 		if (status & PCIE_AER_RE_STS_FIRST_UC_FATAL)
699 			return (-1);
700 		else
701 			isNFE = 1;
702 
703 	fmd_hdl_debug(hdl, "XLATE RP Error");
704 
705 	err |= fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
706 
707 	/* Generate an ereport for this error bit. */
708 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
709 	    PCIEX_ERROR_SUBCLASS, class);
710 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
711 
712 	(void) nvlist_add_uint32(erpt, PCIEX_ROOT_ERRSTS_REG, status);
713 	if ((isFE || isNFE) && data->pcie_rp_ue_src_id) {
714 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
715 		    data->pcie_rp_ue_src_id);
716 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
717 	}
718 	if (STRCMP(class, PCIEX_RC_CE_MSG) && data->pcie_rp_ce_src_id) {
719 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
720 		    data->pcie_rp_ce_src_id);
721 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
722 	}
723 
724 	return (err);
725 }
726 
727 static int
728 fab_prep_pcie_fake_rc_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
729     fab_erpt_tbl_t *tbl)
730 {
731 	const char *class = tbl->err_class;
732 	uint32_t rc_err_sts = 0;
733 	int err = 0;
734 
735 	/*
736 	 * Don't send this for PCI device or Root Ports.  Only send it on
737 	 * systems with non-compliant RPs.
738 	 */
739 	if ((data->dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV) ||
740 	    (data->dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
741 	    (!fab_xlate_fake_rp))
742 		return (-1);
743 
744 	err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_TRUE);
745 
746 	/* Generate an ereport for this error bit. */
747 	(void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
748 	    PCIEX_ERROR_SUBCLASS, class);
749 	(void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
750 
751 	/* Send PCIe RC Ereports */
752 	if (data->pcie_err_status & PCIE_DEVSTS_CE_DETECTED) {
753 		rc_err_sts |= PCIE_AER_RE_STS_CE_RCVD;
754 	}
755 
756 	/* NFE/FE src id takes precedence over CE src id */
757 	if (data->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) {
758 		rc_err_sts |= PCIE_AER_RE_STS_NFE_MSGS_RCVD;
759 		rc_err_sts |= PCIE_AER_RE_STS_FE_NFE_RCVD;
760 	}
761 	if (data->pcie_err_status & PCIE_DEVSTS_FE_DETECTED) {
762 		rc_err_sts |= PCIE_AER_RE_STS_FE_MSGS_RCVD;
763 		rc_err_sts |= PCIE_AER_RE_STS_FE_NFE_RCVD;
764 	}
765 	if ((data->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) &&
766 	    (data->pcie_err_status & PCIE_DEVSTS_FE_DETECTED)) {
767 		rc_err_sts |= PCIE_AER_RE_STS_FIRST_UC_FATAL;
768 		rc_err_sts |= PCIE_AER_RE_STS_MUL_FE_NFE_RCVD;
769 	}
770 
771 	(void) nvlist_add_uint32(erpt, PCIEX_ROOT_ERRSTS_REG, rc_err_sts);
772 
773 	if (!(rc_err_sts & PCIE_AER_RE_STS_MUL_FE_NFE_RCVD)) {
774 		(void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, data->bdf);
775 		(void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
776 	}
777 
778 	return (err);
779 }
780 
781 void
782 fab_xlate_pcie_erpts(fmd_hdl_t *hdl, fab_data_t *data)
783 {
784 	fab_err_tbl_t *tbl;
785 
786 	fmd_hdl_debug(hdl, "Sending Ereports Now");
787 
788 	/* Go through the error logs and send the relavant reports */
789 	for (tbl = fab_master_err_tbl; tbl->erpt_tbl; tbl++) {
790 		fab_send_erpt(hdl, data, tbl);
791 	}
792 
793 	/* Send PCI-X ECC Ereports */
794 	fab_send_pcix_ecc_erpt(hdl, data);
795 	fab_send_pcix_bdg_ecc_erpt(hdl, data);
796 }
797 
798 void
799 fab_xlate_fabric_erpts(fmd_hdl_t *hdl, nvlist_t *nvl, const char *class)
800 {
801 	fab_data_t data = {0};
802 
803 	fmd_hdl_debug(hdl, "fabric ereport received: %s\n", class);
804 
805 	fab_pci_fabric_to_data(hdl, nvl, &data);
806 	fab_xlate_pcie_erpts(hdl, &data);
807 }
808 
809 #define	SET_TBL(n, err, reg, sz) \
810 	fab_master_err_tbl[n].erpt_tbl = fab_ ## err ## _erpt_tbl; \
811 	fab_master_err_tbl[n].reg_offset = offsetof(fab_data_t, reg); \
812 	fab_master_err_tbl[n].reg_size = sz; \
813 	fab_master_err_tbl[n].fab_prep = fab_prep_ ## err ## _erpt;
814 
815 void
816 fab_setup_master_table()
817 {
818 	/* Setup the master error table */
819 	fab_master_err_tbl = (fab_err_tbl_t *)calloc(13,
820 	    sizeof (fab_err_tbl_t));
821 
822 	SET_TBL(0, pci,			pci_err_status,	    16);
823 	SET_TBL(1, pci_bdg,		pci_bdg_sec_stat,   16);
824 	SET_TBL(2, pci_bdg_ctl,		pci_bdg_ctrl,	    16);
825 	SET_TBL(3, pcie_ce,		pcie_ce_status,	    32);
826 	SET_TBL(4, pcie_ue,		pcie_ue_status,	    32);
827 	SET_TBL(5, pcie_sue,		pcie_sue_status,    32);
828 	SET_TBL(6, pcix,		pcix_status,	    32);
829 	SET_TBL(7, pcix_bdg_sec,	pcix_bdg_sec_stat,  16);
830 	SET_TBL(8, pcix_bdg,		pcix_bdg_stat,	    32);
831 	SET_TBL(9, pcie_nadv,		pcie_err_status,    16);
832 	SET_TBL(10, pcie_rc,		pcie_rp_err_status, 32);
833 	SET_TBL(11, pcie_fake_rc,	pcie_err_status,    16);
834 }
835