1.\" Copyright (c) 1999 Chris Costello 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd September 28, 1999 28.Dt MEMCONTROL 8 29.Os 30.Sh NAME 31.Nm memcontrol 32.Nd "control system cache behaviour with respect to memory" 33.Sh SYNOPSIS 34.Nm 35.Ar list 36.Op Fl a 37.Pp 38.Nm 39.Ar set 40.Fl b Ar base 41.Fl l Ar length 42.Fl o Ar owner 43.Ar attribute 44.Pp 45.Nm 46.Ar clear 47.Fl o Ar owner 48.Pp 49.Nm 50.Ar clear 51.Fl b Ar base 52.Fl l Ar length 53.Sh DESCRIPTION 54A number of supported system architectures allow the behaviour of the CPU 55cache to be programmed to behave differently depending on the region being 56written. 57.Pp 58.Nm Memcontrol 59provides an interface to this facility, allowing CPU cache behavior to 60be altered for ranges of system physical memory. 61.Pp 62These ranges are typically power-of-2 aligned and sized, however the specific 63rules governing their layout vary between architectures. The 64.Nm 65program does not attempt to enforce these rules, however the system will 66reject any attempt to set an illegal combination. 67.Bl -tag -width clear 68.It Ar list 69List range slots. 70.Bl -tag -width xxxxxx 71.It Op Fl a 72List all range slots, even those that are inactive 73.El 74.It Ar set 75Set memory range attributes. 76.Bl -tag -width xxxxxx 77.It Fl b Ar base 78Memory range base address 79.It Fl l Ar length 80Length of memory range in bytes, power of 2 81.It Fl o Ar owner 82Text identifier for this setting (7 char max) 83.It Ar attribute 84Attributes applied to this range; one of 85.Ar uncacheable , 86.Ar write-combine , 87.Ar write-through , 88.Ar write-back , 89.Ar write-protect 90.El 91.It Ar clear 92Clear memory range attributes. 93Ranges may be cleared by owner or by 94base/length combination. 95.Pp 96To clear based on ownership: 97.Bl -tag -width xxxxxx 98.It Fl o Ar owner 99All ranges with this owner will be cleared 100.El 101.Pp 102To clear based on the base/length combination: 103.Bl -tag -width xxxxxx 104.It Fl b Ar base 105Memory range base address 106.It Fl l Ar length 107Length of memory range in bytes, power of 2 108.El 109.Pp 110Base and length must exactly match an existing range. 111.El 112.Sh SEE ALSO 113.Xr mem 4 114