1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/linker_set.h> 32 #include <sys/mman.h> 33 34 #include <ctype.h> 35 #include <err.h> 36 #include <errno.h> 37 #include <pthread.h> 38 #include <stdio.h> 39 #include <stdlib.h> 40 #include <string.h> 41 #include <strings.h> 42 #include <assert.h> 43 #include <stdbool.h> 44 #include <sysexits.h> 45 46 #include <machine/vmm.h> 47 #include <machine/vmm_snapshot.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "config.h" 53 #include "debug.h" 54 #include "inout.h" 55 #ifdef __amd64__ 56 #include "amd64/ioapic.h" 57 #endif 58 #include "mem.h" 59 #include "pci_emul.h" 60 #ifdef __amd64__ 61 #include "amd64/pci_irq.h" 62 #include "amd64/pci_lpc.h" 63 #endif 64 #include "pci_passthru.h" 65 #include "qemu_fwcfg.h" 66 67 #define CONF1_ADDR_PORT 0x0cf8 68 #define CONF1_DATA_PORT 0x0cfc 69 70 #define CONF1_ENABLE 0x80000000ul 71 72 #define MAXBUSES (PCI_BUSMAX + 1) 73 #define MAXSLOTS (PCI_SLOTMAX + 1) 74 #define MAXFUNCS (PCI_FUNCMAX + 1) 75 76 #define GB (1024 * 1024 * 1024UL) 77 78 struct funcinfo { 79 nvlist_t *fi_config; 80 struct pci_devemu *fi_pde; 81 struct pci_devinst *fi_devi; 82 }; 83 84 struct intxinfo { 85 int ii_count; 86 int ii_pirq_pin; 87 int ii_ioapic_irq; 88 }; 89 90 struct slotinfo { 91 struct intxinfo si_intpins[4]; 92 struct funcinfo si_funcs[MAXFUNCS]; 93 }; 94 95 struct businfo { 96 uint16_t iobase, iolimit; /* I/O window */ 97 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 98 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 99 struct slotinfo slotinfo[MAXSLOTS]; 100 }; 101 102 static struct businfo *pci_businfo[MAXBUSES]; 103 104 SET_DECLARE(pci_devemu_set, struct pci_devemu); 105 106 static uint64_t pci_emul_iobase; 107 static uint8_t *pci_emul_rombase; 108 static uint64_t pci_emul_romoffset; 109 static uint8_t *pci_emul_romlim; 110 static uint64_t pci_emul_membase32; 111 static uint64_t pci_emul_membase64; 112 static uint64_t pci_emul_memlim64; 113 114 struct pci_bar_allocation { 115 TAILQ_ENTRY(pci_bar_allocation) chain; 116 struct pci_devinst *pdi; 117 int idx; 118 enum pcibar_type type; 119 uint64_t size; 120 }; 121 122 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 123 TAILQ_HEAD_INITIALIZER(pci_bars); 124 125 struct boot_device { 126 TAILQ_ENTRY(boot_device) boot_device_chain; 127 struct pci_devinst *pdi; 128 int bootindex; 129 }; 130 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 131 boot_devices); 132 133 #define PCI_EMUL_IOBASE 0x2000 134 #define PCI_EMUL_IOLIMIT 0x10000 135 136 #define PCI_EMUL_ROMSIZE 0x10000000 137 138 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 139 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 140 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 141 142 /* 143 * OVMF always uses 0xC0000000 as base address for 32 bit PCI MMIO. Don't 144 * change this address without changing it in OVMF. 145 */ 146 #define PCI_EMUL_MEMBASE32 0xC0000000 147 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 148 #define PCI_EMUL_MEMSIZE64 (32*GB) 149 150 #ifdef __amd64__ 151 static void pci_lintr_route(struct pci_devinst *pi); 152 static void pci_lintr_update(struct pci_devinst *pi); 153 #endif 154 155 static struct pci_devemu *pci_emul_finddev(const char *name); 156 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 157 int bytes, uint32_t *val); 158 159 static __inline void 160 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 161 { 162 163 if (bytes == 1) 164 pci_set_cfgdata8(pi, coff, val); 165 else if (bytes == 2) 166 pci_set_cfgdata16(pi, coff, val); 167 else 168 pci_set_cfgdata32(pi, coff, val); 169 } 170 171 static __inline uint32_t 172 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 173 { 174 175 if (bytes == 1) 176 return (pci_get_cfgdata8(pi, coff)); 177 else if (bytes == 2) 178 return (pci_get_cfgdata16(pi, coff)); 179 else 180 return (pci_get_cfgdata32(pi, coff)); 181 } 182 183 static int 184 is_pcir_bar(int coff) 185 { 186 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 187 } 188 189 static int 190 is_pcir_bios(int coff) 191 { 192 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 193 } 194 195 /* 196 * I/O access 197 */ 198 199 /* 200 * Slot options are in the form: 201 * 202 * <bus>:<slot>:<func>,<emul>[,<config>] 203 * <slot>[:<func>],<emul>[,<config>] 204 * 205 * slot is 0..31 206 * func is 0..7 207 * emul is a string describing the type of PCI device e.g. virtio-net 208 * config is an optional string, depending on the device, that can be 209 * used for configuration. 210 * Examples are: 211 * 1,virtio-net,tap0 212 * 3:0,dummy 213 */ 214 static void 215 pci_parse_slot_usage(char *aopt) 216 { 217 218 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 219 } 220 221 /* 222 * Helper function to parse a list of comma-separated options where 223 * each option is formatted as "name[=value]". If no value is 224 * provided, the option is treated as a boolean and is given a value 225 * of true. 226 */ 227 int 228 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 229 { 230 char *config, *name, *tofree, *value; 231 232 if (opt == NULL) 233 return (0); 234 235 config = tofree = strdup(opt); 236 while ((name = strsep(&config, ",")) != NULL) { 237 value = strchr(name, '='); 238 if (value != NULL) { 239 *value = '\0'; 240 value++; 241 set_config_value_node(nvl, name, value); 242 } else 243 set_config_bool_node(nvl, name, true); 244 } 245 free(tofree); 246 return (0); 247 } 248 249 /* 250 * PCI device configuration is stored in MIBs that encode the device's 251 * location: 252 * 253 * pci.<bus>.<slot>.<func> 254 * 255 * Where "bus", "slot", and "func" are all decimal values without 256 * leading zeroes. Each valid device must have a "device" node which 257 * identifies the driver model of the device. 258 * 259 * Device backends can provide a parser for the "config" string. If 260 * a custom parser is not provided, pci_parse_legacy_config() is used 261 * to parse the string. 262 */ 263 int 264 pci_parse_slot(char *opt) 265 { 266 char node_name[sizeof("pci.XXX.XX.X")]; 267 struct pci_devemu *pde; 268 char *emul, *config, *str, *cp; 269 int error, bnum, snum, fnum; 270 nvlist_t *nvl; 271 272 error = -1; 273 str = strdup(opt); 274 275 emul = config = NULL; 276 if ((cp = strchr(str, ',')) != NULL) { 277 *cp = '\0'; 278 emul = cp + 1; 279 if ((cp = strchr(emul, ',')) != NULL) { 280 *cp = '\0'; 281 config = cp + 1; 282 } 283 } else { 284 pci_parse_slot_usage(opt); 285 goto done; 286 } 287 288 /* <bus>:<slot>:<func> */ 289 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 290 bnum = 0; 291 /* <slot>:<func> */ 292 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 293 fnum = 0; 294 /* <slot> */ 295 if (sscanf(str, "%d", &snum) != 1) { 296 snum = -1; 297 } 298 } 299 } 300 301 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 302 fnum < 0 || fnum >= MAXFUNCS) { 303 pci_parse_slot_usage(opt); 304 goto done; 305 } 306 307 pde = pci_emul_finddev(emul); 308 if (pde == NULL) { 309 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 310 fnum, emul); 311 goto done; 312 } 313 314 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 315 fnum); 316 nvl = find_config_node(node_name); 317 if (nvl != NULL) { 318 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 319 fnum); 320 goto done; 321 } 322 nvl = create_config_node(node_name); 323 if (pde->pe_alias != NULL) 324 set_config_value_node(nvl, "device", pde->pe_alias); 325 else 326 set_config_value_node(nvl, "device", pde->pe_emu); 327 328 if (pde->pe_legacy_config != NULL) 329 error = pde->pe_legacy_config(nvl, config); 330 else 331 error = pci_parse_legacy_config(nvl, config); 332 done: 333 free(str); 334 return (error); 335 } 336 337 void 338 pci_print_supported_devices(void) 339 { 340 struct pci_devemu **pdpp, *pdp; 341 342 SET_FOREACH(pdpp, pci_devemu_set) { 343 pdp = *pdpp; 344 printf("%s\n", pdp->pe_emu); 345 } 346 } 347 348 uint32_t 349 pci_config_read_reg(const struct pcisel *const host_sel, nvlist_t *nvl, 350 const uint32_t reg, const uint8_t size, const uint32_t def) 351 { 352 const char *config; 353 const nvlist_t *pci_regs; 354 355 assert(size == 1 || size == 2 || size == 4); 356 357 pci_regs = find_relative_config_node(nvl, "pcireg"); 358 if (pci_regs == NULL) { 359 return def; 360 } 361 362 switch (reg) { 363 case PCIR_DEVICE: 364 config = get_config_value_node(pci_regs, "device"); 365 break; 366 case PCIR_VENDOR: 367 config = get_config_value_node(pci_regs, "vendor"); 368 break; 369 case PCIR_REVID: 370 config = get_config_value_node(pci_regs, "revid"); 371 break; 372 case PCIR_SUBVEND_0: 373 config = get_config_value_node(pci_regs, "subvendor"); 374 break; 375 case PCIR_SUBDEV_0: 376 config = get_config_value_node(pci_regs, "subdevice"); 377 break; 378 default: 379 return (-1); 380 } 381 382 if (config == NULL) { 383 return def; 384 } else if (host_sel != NULL && strcmp(config, "host") == 0) { 385 return pci_host_read_config(host_sel, reg, size); 386 } else { 387 return strtol(config, NULL, 16); 388 } 389 } 390 391 static int 392 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 393 { 394 395 if (offset < pi->pi_msix.pba_offset) 396 return (0); 397 398 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 399 return (0); 400 } 401 402 return (1); 403 } 404 405 int 406 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 407 uint64_t value) 408 { 409 int msix_entry_offset; 410 int tab_index; 411 char *dest; 412 413 /* support only 4 or 8 byte writes */ 414 if (size != 4 && size != 8) 415 return (-1); 416 417 /* 418 * Return if table index is beyond what device supports 419 */ 420 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 421 if (tab_index >= pi->pi_msix.table_count) 422 return (-1); 423 424 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 425 426 /* support only aligned writes */ 427 if ((msix_entry_offset % size) != 0) 428 return (-1); 429 430 dest = (char *)(pi->pi_msix.table + tab_index); 431 dest += msix_entry_offset; 432 433 if (size == 4) 434 *((uint32_t *)dest) = value; 435 else 436 *((uint64_t *)dest) = value; 437 438 return (0); 439 } 440 441 uint64_t 442 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 443 { 444 char *dest; 445 int msix_entry_offset; 446 int tab_index; 447 uint64_t retval = ~0; 448 449 /* 450 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 451 * table but we also allow 1 byte access to accommodate reads from 452 * ddb. 453 */ 454 if (size != 1 && size != 4 && size != 8) 455 return (retval); 456 457 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 458 459 /* support only aligned reads */ 460 if ((msix_entry_offset % size) != 0) { 461 return (retval); 462 } 463 464 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 465 466 if (tab_index < pi->pi_msix.table_count) { 467 /* valid MSI-X Table access */ 468 dest = (char *)(pi->pi_msix.table + tab_index); 469 dest += msix_entry_offset; 470 471 if (size == 1) 472 retval = *((uint8_t *)dest); 473 else if (size == 4) 474 retval = *((uint32_t *)dest); 475 else 476 retval = *((uint64_t *)dest); 477 } else if (pci_valid_pba_offset(pi, offset)) { 478 /* return 0 for PBA access */ 479 retval = 0; 480 } 481 482 return (retval); 483 } 484 485 int 486 pci_msix_table_bar(struct pci_devinst *pi) 487 { 488 489 if (pi->pi_msix.table != NULL) 490 return (pi->pi_msix.table_bar); 491 else 492 return (-1); 493 } 494 495 int 496 pci_msix_pba_bar(struct pci_devinst *pi) 497 { 498 499 if (pi->pi_msix.table != NULL) 500 return (pi->pi_msix.pba_bar); 501 else 502 return (-1); 503 } 504 505 static int 506 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 507 int bytes, uint32_t *eax, void *arg) 508 { 509 struct pci_devinst *pdi = arg; 510 struct pci_devemu *pe = pdi->pi_d; 511 uint64_t offset; 512 int i; 513 514 assert(port >= 0); 515 516 for (i = 0; i <= PCI_BARMAX; i++) { 517 if (pdi->pi_bar[i].type == PCIBAR_IO && 518 (uint64_t)port >= pdi->pi_bar[i].addr && 519 (uint64_t)port + bytes <= 520 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 521 offset = port - pdi->pi_bar[i].addr; 522 if (in) 523 *eax = (*pe->pe_barread)(pdi, i, 524 offset, bytes); 525 else 526 (*pe->pe_barwrite)(pdi, i, offset, 527 bytes, *eax); 528 return (0); 529 } 530 } 531 return (-1); 532 } 533 534 static int 535 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 536 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 537 { 538 struct pci_devinst *pdi = arg1; 539 struct pci_devemu *pe = pdi->pi_d; 540 uint64_t offset; 541 int bidx = (int) arg2; 542 543 assert(bidx <= PCI_BARMAX); 544 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 545 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 546 assert(addr >= pdi->pi_bar[bidx].addr && 547 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 548 549 offset = addr - pdi->pi_bar[bidx].addr; 550 551 if (dir == MEM_F_WRITE) { 552 if (size == 8) { 553 (*pe->pe_barwrite)(pdi, bidx, offset, 554 4, *val & 0xffffffff); 555 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 556 4, *val >> 32); 557 } else { 558 (*pe->pe_barwrite)(pdi, bidx, offset, 559 size, *val); 560 } 561 } else { 562 if (size == 8) { 563 *val = (*pe->pe_barread)(pdi, bidx, 564 offset, 4); 565 *val |= (*pe->pe_barread)(pdi, bidx, 566 offset + 4, 4) << 32; 567 } else { 568 *val = (*pe->pe_barread)(pdi, bidx, 569 offset, size); 570 } 571 } 572 573 return (0); 574 } 575 576 577 static int 578 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 579 uint64_t *addr) 580 { 581 uint64_t base; 582 583 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 584 585 base = roundup2(*baseptr, size); 586 587 if (base + size <= limit) { 588 *addr = base; 589 *baseptr = base + size; 590 return (0); 591 } else 592 return (-1); 593 } 594 595 /* 596 * Register (or unregister) the MMIO or I/O region associated with the BAR 597 * register 'idx' of an emulated pci device. 598 */ 599 static void 600 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 601 { 602 struct pci_devemu *pe; 603 int error; 604 struct inout_port iop; 605 struct mem_range mr; 606 607 pe = pi->pi_d; 608 switch (pi->pi_bar[idx].type) { 609 case PCIBAR_IO: 610 bzero(&iop, sizeof(struct inout_port)); 611 iop.name = pi->pi_name; 612 iop.port = pi->pi_bar[idx].addr; 613 iop.size = pi->pi_bar[idx].size; 614 if (registration) { 615 iop.flags = IOPORT_F_INOUT; 616 iop.handler = pci_emul_io_handler; 617 iop.arg = pi; 618 error = register_inout(&iop); 619 } else 620 error = unregister_inout(&iop); 621 break; 622 case PCIBAR_MEM32: 623 case PCIBAR_MEM64: 624 bzero(&mr, sizeof(struct mem_range)); 625 mr.name = pi->pi_name; 626 mr.base = pi->pi_bar[idx].addr; 627 mr.size = pi->pi_bar[idx].size; 628 if (registration) { 629 mr.flags = MEM_F_RW; 630 mr.handler = pci_emul_mem_handler; 631 mr.arg1 = pi; 632 mr.arg2 = idx; 633 error = register_mem(&mr); 634 } else 635 error = unregister_mem(&mr); 636 break; 637 case PCIBAR_ROM: 638 error = 0; 639 break; 640 default: 641 error = EINVAL; 642 break; 643 } 644 assert(error == 0); 645 646 if (pe->pe_baraddr != NULL) 647 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); 648 } 649 650 static void 651 unregister_bar(struct pci_devinst *pi, int idx) 652 { 653 654 modify_bar_registration(pi, idx, 0); 655 } 656 657 static void 658 register_bar(struct pci_devinst *pi, int idx) 659 { 660 661 modify_bar_registration(pi, idx, 1); 662 } 663 664 /* Is the ROM enabled for the emulated pci device? */ 665 static int 666 romen(struct pci_devinst *pi) 667 { 668 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 669 PCIM_BIOS_ENABLE; 670 } 671 672 /* Are we decoding i/o port accesses for the emulated pci device? */ 673 static int 674 porten(struct pci_devinst *pi) 675 { 676 uint16_t cmd; 677 678 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 679 680 return (cmd & PCIM_CMD_PORTEN); 681 } 682 683 /* Are we decoding memory accesses for the emulated pci device? */ 684 static int 685 memen(struct pci_devinst *pi) 686 { 687 uint16_t cmd; 688 689 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 690 691 return (cmd & PCIM_CMD_MEMEN); 692 } 693 694 /* 695 * Update the MMIO or I/O address that is decoded by the BAR register. 696 * 697 * If the pci device has enabled the address space decoding then intercept 698 * the address range decoded by the BAR register. 699 */ 700 static void 701 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 702 { 703 int decode; 704 705 if (pi->pi_bar[idx].type == PCIBAR_IO) 706 decode = porten(pi); 707 else 708 decode = memen(pi); 709 710 if (decode) 711 unregister_bar(pi, idx); 712 713 switch (type) { 714 case PCIBAR_IO: 715 case PCIBAR_MEM32: 716 pi->pi_bar[idx].addr = addr; 717 break; 718 case PCIBAR_MEM64: 719 pi->pi_bar[idx].addr &= ~0xffffffffUL; 720 pi->pi_bar[idx].addr |= addr; 721 break; 722 case PCIBAR_MEMHI64: 723 pi->pi_bar[idx].addr &= 0xffffffff; 724 pi->pi_bar[idx].addr |= addr; 725 break; 726 default: 727 assert(0); 728 } 729 730 if (decode) 731 register_bar(pi, idx); 732 } 733 734 int 735 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 736 uint64_t size) 737 { 738 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); 739 assert((type != PCIBAR_ROM) || (idx == PCI_ROM_IDX)); 740 741 if ((size & (size - 1)) != 0) 742 size = 1UL << flsl(size); /* round up to a power of 2 */ 743 744 /* Enforce minimum BAR sizes required by the PCI standard */ 745 if (type == PCIBAR_IO) { 746 if (size < 4) 747 size = 4; 748 } else if (type == PCIBAR_ROM) { 749 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 750 size = ~PCIM_BIOS_ADDR_MASK + 1; 751 } else { 752 if (size < 16) 753 size = 16; 754 } 755 756 /* 757 * To reduce fragmentation of the MMIO space, we allocate the BARs by 758 * size. Therefore, don't allocate the BAR yet. We create a list of all 759 * BAR allocation which is sorted by BAR size. When all PCI devices are 760 * initialized, we will assign an address to the BARs. 761 */ 762 763 /* create a new list entry */ 764 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 765 memset(new_bar, 0, sizeof(*new_bar)); 766 new_bar->pdi = pdi; 767 new_bar->idx = idx; 768 new_bar->type = type; 769 new_bar->size = size; 770 771 /* 772 * Search for a BAR which size is lower than the size of our newly 773 * allocated BAR. 774 */ 775 struct pci_bar_allocation *bar = NULL; 776 TAILQ_FOREACH(bar, &pci_bars, chain) { 777 if (bar->size < size) { 778 break; 779 } 780 } 781 782 if (bar == NULL) { 783 /* 784 * Either the list is empty or new BAR is the smallest BAR of 785 * the list. Append it to the end of our list. 786 */ 787 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 788 } else { 789 /* 790 * The found BAR is smaller than our new BAR. For that reason, 791 * insert our new BAR before the found BAR. 792 */ 793 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 794 } 795 796 /* 797 * pci_passthru devices synchronize their physical and virtual command 798 * register on init. For that reason, the virtual cmd reg should be 799 * updated as early as possible. 800 */ 801 uint16_t enbit = 0; 802 switch (type) { 803 case PCIBAR_IO: 804 enbit = PCIM_CMD_PORTEN; 805 break; 806 case PCIBAR_MEM64: 807 case PCIBAR_MEM32: 808 enbit = PCIM_CMD_MEMEN; 809 break; 810 default: 811 enbit = 0; 812 break; 813 } 814 815 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 816 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 817 818 return (0); 819 } 820 821 static int 822 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 823 const enum pcibar_type type, const uint64_t size) 824 { 825 int error; 826 uint64_t *baseptr, limit, addr, mask, lobits, bar; 827 828 switch (type) { 829 case PCIBAR_NONE: 830 baseptr = NULL; 831 addr = mask = lobits = 0; 832 break; 833 case PCIBAR_IO: 834 baseptr = &pci_emul_iobase; 835 limit = PCI_EMUL_IOLIMIT; 836 mask = PCIM_BAR_IO_BASE; 837 lobits = PCIM_BAR_IO_SPACE; 838 break; 839 case PCIBAR_MEM64: 840 /* 841 * XXX 842 * Some drivers do not work well if the 64-bit BAR is allocated 843 * above 4GB. Allow for this by allocating small requests under 844 * 4GB unless then allocation size is larger than some arbitrary 845 * number (128MB currently). 846 */ 847 if (size > 128 * 1024 * 1024) { 848 baseptr = &pci_emul_membase64; 849 limit = pci_emul_memlim64; 850 mask = PCIM_BAR_MEM_BASE; 851 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 852 PCIM_BAR_MEM_PREFETCH; 853 } else { 854 baseptr = &pci_emul_membase32; 855 limit = PCI_EMUL_MEMLIMIT32; 856 mask = PCIM_BAR_MEM_BASE; 857 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 858 } 859 break; 860 case PCIBAR_MEM32: 861 baseptr = &pci_emul_membase32; 862 limit = PCI_EMUL_MEMLIMIT32; 863 mask = PCIM_BAR_MEM_BASE; 864 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 865 break; 866 case PCIBAR_ROM: 867 /* do not claim memory for ROM. OVMF will do it for us. */ 868 baseptr = NULL; 869 limit = 0; 870 mask = PCIM_BIOS_ADDR_MASK; 871 lobits = 0; 872 break; 873 default: 874 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 875 assert(0); 876 } 877 878 if (baseptr != NULL) { 879 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 880 if (error != 0) 881 return (error); 882 } else { 883 addr = 0; 884 } 885 886 pdi->pi_bar[idx].type = type; 887 pdi->pi_bar[idx].addr = addr; 888 pdi->pi_bar[idx].size = size; 889 /* 890 * passthru devices are using same lobits as physical device they set 891 * this property 892 */ 893 if (pdi->pi_bar[idx].lobits != 0) { 894 lobits = pdi->pi_bar[idx].lobits; 895 } else { 896 pdi->pi_bar[idx].lobits = lobits; 897 } 898 899 /* Initialize the BAR register in config space */ 900 bar = (addr & mask) | lobits; 901 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 902 903 if (type == PCIBAR_MEM64) { 904 assert(idx + 1 <= PCI_BARMAX); 905 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 906 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 907 } 908 909 if (type != PCIBAR_ROM) { 910 register_bar(pdi, idx); 911 } 912 913 return (0); 914 } 915 916 int 917 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 918 void **const addr) 919 { 920 /* allocate ROM space once on first call */ 921 if (pci_emul_rombase == 0) { 922 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 923 "pcirom", PCI_EMUL_ROMSIZE); 924 if (pci_emul_rombase == MAP_FAILED) { 925 warnx("%s: failed to create rom segment", __func__); 926 return (-1); 927 } 928 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 929 pci_emul_romoffset = 0; 930 } 931 932 /* ROM size should be a power of 2 and greater than 2 KB */ 933 const uint64_t rom_size = MAX(1UL << flsl(size), 934 ~PCIM_BIOS_ADDR_MASK + 1); 935 936 /* check if ROM fits into ROM space */ 937 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 938 warnx("%s: no space left in rom segment:", __func__); 939 warnx("%16lu bytes left", 940 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 941 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 942 pdi->pi_slot, pdi->pi_func); 943 return (-1); 944 } 945 946 /* allocate ROM BAR */ 947 const int error = pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, 948 rom_size); 949 if (error) 950 return error; 951 952 /* return address */ 953 *addr = pci_emul_rombase + pci_emul_romoffset; 954 955 /* save offset into ROM Space */ 956 pdi->pi_romoffset = pci_emul_romoffset; 957 958 /* increase offset for next ROM */ 959 pci_emul_romoffset += rom_size; 960 961 return (0); 962 } 963 964 int 965 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 966 { 967 struct boot_device *new_device, *device; 968 969 /* don't permit a negative bootindex */ 970 if (bootindex < 0) { 971 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 972 } 973 974 /* alloc new boot device */ 975 new_device = calloc(1, sizeof(struct boot_device)); 976 if (new_device == NULL) { 977 return (ENOMEM); 978 } 979 new_device->pdi = pi; 980 new_device->bootindex = bootindex; 981 982 /* search for boot device with higher boot index */ 983 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 984 if (device->bootindex == bootindex) { 985 errx(4, 986 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 987 bootindex, pi->pi_name, device->pdi->pi_name); 988 } else if (device->bootindex > bootindex) { 989 break; 990 } 991 } 992 993 /* add boot device to queue */ 994 if (device == NULL) { 995 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 996 } else { 997 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 998 } 999 1000 return (0); 1001 } 1002 1003 #define CAP_START_OFFSET 0x40 1004 static int 1005 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1006 { 1007 int i, capoff, reallen; 1008 uint16_t sts; 1009 1010 assert(caplen > 0); 1011 1012 reallen = roundup2(caplen, 4); /* dword aligned */ 1013 1014 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1015 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1016 capoff = CAP_START_OFFSET; 1017 else 1018 capoff = pi->pi_capend + 1; 1019 1020 /* Check if we have enough space */ 1021 if (capoff + reallen > PCI_REGMAX + 1) 1022 return (-1); 1023 1024 /* Set the previous capability pointer */ 1025 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1026 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1027 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1028 } else 1029 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1030 1031 /* Copy the capability */ 1032 for (i = 0; i < caplen; i++) 1033 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1034 1035 /* Set the next capability pointer */ 1036 pci_set_cfgdata8(pi, capoff + 1, 0); 1037 1038 pi->pi_prevcap = capoff; 1039 pi->pi_capend = capoff + reallen - 1; 1040 return (0); 1041 } 1042 1043 static struct pci_devemu * 1044 pci_emul_finddev(const char *name) 1045 { 1046 struct pci_devemu **pdpp, *pdp; 1047 1048 SET_FOREACH(pdpp, pci_devemu_set) { 1049 pdp = *pdpp; 1050 if (!strcmp(pdp->pe_emu, name)) { 1051 return (pdp); 1052 } 1053 } 1054 1055 return (NULL); 1056 } 1057 1058 static int 1059 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1060 int func, struct funcinfo *fi) 1061 { 1062 struct pci_devinst *pdi; 1063 int err; 1064 1065 pdi = calloc(1, sizeof(struct pci_devinst)); 1066 1067 pdi->pi_vmctx = ctx; 1068 pdi->pi_bus = bus; 1069 pdi->pi_slot = slot; 1070 pdi->pi_func = func; 1071 #ifdef __amd64__ 1072 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1073 pdi->pi_lintr.pin = 0; 1074 pdi->pi_lintr.state = IDLE; 1075 pdi->pi_lintr.pirq_pin = 0; 1076 pdi->pi_lintr.ioapic_irq = 0; 1077 #endif 1078 pdi->pi_d = pde; 1079 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1080 slot, func); 1081 1082 /* Disable legacy interrupts */ 1083 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1084 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1085 1086 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1087 1088 err = (*pde->pe_init)(pdi, fi->fi_config); 1089 if (err == 0) 1090 fi->fi_devi = pdi; 1091 else 1092 free(pdi); 1093 1094 return (err); 1095 } 1096 1097 void 1098 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1099 { 1100 int mmc; 1101 1102 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1103 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1104 mmc = ffs(msgnum) - 1; 1105 1106 bzero(msicap, sizeof(struct msicap)); 1107 msicap->capid = PCIY_MSI; 1108 msicap->nextptr = nextptr; 1109 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1110 } 1111 1112 int 1113 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1114 { 1115 struct msicap msicap; 1116 1117 pci_populate_msicap(&msicap, msgnum, 0); 1118 1119 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1120 } 1121 1122 static void 1123 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1124 uint32_t msix_tab_size) 1125 { 1126 1127 assert(msix_tab_size % 4096 == 0); 1128 1129 bzero(msixcap, sizeof(struct msixcap)); 1130 msixcap->capid = PCIY_MSIX; 1131 1132 /* 1133 * Message Control Register, all fields set to 1134 * zero except for the Table Size. 1135 * Note: Table size N is encoded as N-1 1136 */ 1137 msixcap->msgctrl = msgnum - 1; 1138 1139 /* 1140 * MSI-X BAR setup: 1141 * - MSI-X table start at offset 0 1142 * - PBA table starts at a 4K aligned offset after the MSI-X table 1143 */ 1144 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1145 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1146 } 1147 1148 static void 1149 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1150 { 1151 int i, table_size; 1152 1153 assert(table_entries > 0); 1154 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1155 1156 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1157 pi->pi_msix.table = calloc(1, table_size); 1158 1159 /* set mask bit of vector control register */ 1160 for (i = 0; i < table_entries; i++) 1161 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1162 } 1163 1164 int 1165 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1166 { 1167 uint32_t tab_size; 1168 struct msixcap msixcap; 1169 1170 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1171 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1172 1173 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1174 1175 /* Align table size to nearest 4K */ 1176 tab_size = roundup2(tab_size, 4096); 1177 1178 pi->pi_msix.table_bar = barnum; 1179 pi->pi_msix.pba_bar = barnum; 1180 pi->pi_msix.table_offset = 0; 1181 pi->pi_msix.table_count = msgnum; 1182 pi->pi_msix.pba_offset = tab_size; 1183 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1184 1185 pci_msix_table_init(pi, msgnum); 1186 1187 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1188 1189 /* allocate memory for MSI-X Table and PBA */ 1190 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1191 tab_size + pi->pi_msix.pba_size); 1192 1193 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1194 sizeof(msixcap))); 1195 } 1196 1197 static void 1198 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1199 int bytes, uint32_t val) 1200 { 1201 uint16_t msgctrl, rwmask; 1202 int off; 1203 1204 off = offset - capoff; 1205 /* Message Control Register */ 1206 if (off == 2 && bytes == 2) { 1207 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1208 msgctrl = pci_get_cfgdata16(pi, offset); 1209 msgctrl &= ~rwmask; 1210 msgctrl |= val & rwmask; 1211 val = msgctrl; 1212 1213 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1214 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1215 #ifdef __amd64__ 1216 pci_lintr_update(pi); 1217 #endif 1218 } 1219 1220 CFGWRITE(pi, offset, val, bytes); 1221 } 1222 1223 static void 1224 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1225 int bytes, uint32_t val) 1226 { 1227 uint16_t msgctrl, rwmask, msgdata, mme; 1228 uint32_t addrlo; 1229 1230 /* 1231 * If guest is writing to the message control register make sure 1232 * we do not overwrite read-only fields. 1233 */ 1234 if ((offset - capoff) == 2 && bytes == 2) { 1235 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1236 msgctrl = pci_get_cfgdata16(pi, offset); 1237 msgctrl &= ~rwmask; 1238 msgctrl |= val & rwmask; 1239 val = msgctrl; 1240 } 1241 CFGWRITE(pi, offset, val, bytes); 1242 1243 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1244 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1245 if (msgctrl & PCIM_MSICTRL_64BIT) 1246 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1247 else 1248 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1249 1250 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1251 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1252 if (pi->pi_msi.enabled) { 1253 pi->pi_msi.addr = addrlo; 1254 pi->pi_msi.msg_data = msgdata; 1255 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1256 } else { 1257 pi->pi_msi.maxmsgnum = 0; 1258 } 1259 #ifdef __amd64__ 1260 pci_lintr_update(pi); 1261 #endif 1262 } 1263 1264 static void 1265 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1266 int bytes, uint32_t val) 1267 { 1268 1269 /* XXX don't write to the readonly parts */ 1270 CFGWRITE(pi, offset, val, bytes); 1271 } 1272 1273 #define PCIECAP_VERSION 0x2 1274 int 1275 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1276 { 1277 int err; 1278 struct pciecap pciecap; 1279 1280 bzero(&pciecap, sizeof(pciecap)); 1281 1282 /* 1283 * Use the integrated endpoint type for endpoints on a root complex bus. 1284 * 1285 * NB: bhyve currently only supports a single PCI bus that is the root 1286 * complex bus, so all endpoints are integrated. 1287 */ 1288 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1289 type = PCIEM_TYPE_ROOT_INT_EP; 1290 1291 pciecap.capid = PCIY_EXPRESS; 1292 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1293 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1294 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1295 pciecap.link_status = 0x11; /* gen1, x1 */ 1296 } 1297 1298 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1299 return (err); 1300 } 1301 1302 /* 1303 * This function assumes that 'coff' is in the capabilities region of the 1304 * config space. A capoff parameter of zero will force a search for the 1305 * offset and type. 1306 */ 1307 void 1308 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1309 uint8_t capoff, int capid) 1310 { 1311 uint8_t nextoff; 1312 1313 /* Do not allow un-aligned writes */ 1314 if ((offset & (bytes - 1)) != 0) 1315 return; 1316 1317 if (capoff == 0) { 1318 /* Find the capability that we want to update */ 1319 capoff = CAP_START_OFFSET; 1320 while (1) { 1321 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1322 if (nextoff == 0) 1323 break; 1324 if (offset >= capoff && offset < nextoff) 1325 break; 1326 1327 capoff = nextoff; 1328 } 1329 assert(offset >= capoff); 1330 capid = pci_get_cfgdata8(pi, capoff); 1331 } 1332 1333 /* 1334 * Capability ID and Next Capability Pointer are readonly. 1335 * However, some o/s's do 4-byte writes that include these. 1336 * For this case, trim the write back to 2 bytes and adjust 1337 * the data. 1338 */ 1339 if (offset == capoff || offset == capoff + 1) { 1340 if (offset == capoff && bytes == 4) { 1341 bytes = 2; 1342 offset += 2; 1343 val >>= 16; 1344 } else 1345 return; 1346 } 1347 1348 switch (capid) { 1349 case PCIY_MSI: 1350 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1351 break; 1352 case PCIY_MSIX: 1353 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1354 break; 1355 case PCIY_EXPRESS: 1356 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1357 break; 1358 default: 1359 break; 1360 } 1361 } 1362 1363 static int 1364 pci_emul_iscap(struct pci_devinst *pi, int offset) 1365 { 1366 uint16_t sts; 1367 1368 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1369 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1370 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1371 return (1); 1372 } 1373 return (0); 1374 } 1375 1376 static int 1377 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1378 uint64_t addr __unused, int size __unused, uint64_t *val, 1379 void *arg1 __unused, long arg2 __unused) 1380 { 1381 /* 1382 * Ignore writes; return 0xff's for reads. The mem read code 1383 * will take care of truncating to the correct size. 1384 */ 1385 if (dir == MEM_F_READ) { 1386 *val = 0xffffffffffffffff; 1387 } 1388 1389 return (0); 1390 } 1391 1392 static int 1393 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1394 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1395 { 1396 int bus, slot, func, coff, in; 1397 1398 coff = addr & 0xfff; 1399 func = (addr >> 12) & 0x7; 1400 slot = (addr >> 15) & 0x1f; 1401 bus = (addr >> 20) & 0xff; 1402 in = (dir == MEM_F_READ); 1403 if (in) 1404 *val = ~0UL; 1405 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1406 return (0); 1407 } 1408 1409 uint64_t 1410 pci_ecfg_base(void) 1411 { 1412 1413 return (PCI_EMUL_ECFG_BASE); 1414 } 1415 1416 static int 1417 init_bootorder(void) 1418 { 1419 struct boot_device *device; 1420 FILE *fp; 1421 char *bootorder; 1422 size_t bootorder_len; 1423 1424 if (TAILQ_EMPTY(&boot_devices)) 1425 return (0); 1426 1427 fp = open_memstream(&bootorder, &bootorder_len); 1428 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1429 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1430 device->pdi->pi_slot, device->pdi->pi_func); 1431 } 1432 fclose(fp); 1433 1434 return (qemu_fwcfg_add_file("bootorder", bootorder_len, bootorder)); 1435 } 1436 1437 #define BUSIO_ROUNDUP 32 1438 #define BUSMEM32_ROUNDUP (1024 * 1024) 1439 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1440 1441 int 1442 init_pci(struct vmctx *ctx) 1443 { 1444 char node_name[sizeof("pci.XXX.XX.X")]; 1445 struct mem_range mr; 1446 struct pci_devemu *pde; 1447 struct businfo *bi; 1448 struct slotinfo *si; 1449 struct funcinfo *fi; 1450 nvlist_t *nvl; 1451 const char *emul; 1452 size_t lowmem; 1453 int bus, slot, func; 1454 int error; 1455 1456 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1457 errx(EX_OSERR, "Invalid lowmem limit"); 1458 1459 pci_emul_iobase = PCI_EMUL_IOBASE; 1460 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1461 1462 pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx); 1463 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1464 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1465 1466 TAILQ_INIT(&boot_devices); 1467 1468 for (bus = 0; bus < MAXBUSES; bus++) { 1469 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1470 nvl = find_config_node(node_name); 1471 if (nvl == NULL) 1472 continue; 1473 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1474 bi = pci_businfo[bus]; 1475 1476 /* 1477 * Keep track of the i/o and memory resources allocated to 1478 * this bus. 1479 */ 1480 bi->iobase = pci_emul_iobase; 1481 bi->membase32 = pci_emul_membase32; 1482 bi->membase64 = pci_emul_membase64; 1483 1484 /* first run: init devices */ 1485 for (slot = 0; slot < MAXSLOTS; slot++) { 1486 si = &bi->slotinfo[slot]; 1487 for (func = 0; func < MAXFUNCS; func++) { 1488 fi = &si->si_funcs[func]; 1489 snprintf(node_name, sizeof(node_name), 1490 "pci.%d.%d.%d", bus, slot, func); 1491 nvl = find_config_node(node_name); 1492 if (nvl == NULL) 1493 continue; 1494 1495 fi->fi_config = nvl; 1496 emul = get_config_value_node(nvl, "device"); 1497 if (emul == NULL) { 1498 EPRINTLN("pci slot %d:%d:%d: missing " 1499 "\"device\" value", bus, slot, func); 1500 return (EINVAL); 1501 } 1502 pde = pci_emul_finddev(emul); 1503 if (pde == NULL) { 1504 EPRINTLN("pci slot %d:%d:%d: unknown " 1505 "device \"%s\"", bus, slot, func, 1506 emul); 1507 return (EINVAL); 1508 } 1509 if (pde->pe_alias != NULL) { 1510 EPRINTLN("pci slot %d:%d:%d: legacy " 1511 "device \"%s\", use \"%s\" instead", 1512 bus, slot, func, emul, 1513 pde->pe_alias); 1514 return (EINVAL); 1515 } 1516 fi->fi_pde = pde; 1517 error = pci_emul_init(ctx, pde, bus, slot, 1518 func, fi); 1519 if (error) 1520 return (error); 1521 } 1522 } 1523 1524 /* second run: assign BARs and free list */ 1525 struct pci_bar_allocation *bar; 1526 struct pci_bar_allocation *bar_tmp; 1527 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1528 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1529 bar->size); 1530 free(bar); 1531 } 1532 TAILQ_INIT(&pci_bars); 1533 1534 /* 1535 * Add some slop to the I/O and memory resources decoded by 1536 * this bus to give a guest some flexibility if it wants to 1537 * reprogram the BARs. 1538 */ 1539 pci_emul_iobase += BUSIO_ROUNDUP; 1540 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1541 bi->iolimit = pci_emul_iobase; 1542 1543 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1544 pci_emul_membase32 = roundup2(pci_emul_membase32, 1545 BUSMEM32_ROUNDUP); 1546 bi->memlimit32 = pci_emul_membase32; 1547 1548 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1549 pci_emul_membase64 = roundup2(pci_emul_membase64, 1550 BUSMEM64_ROUNDUP); 1551 bi->memlimit64 = pci_emul_membase64; 1552 } 1553 1554 #ifdef __amd64__ 1555 /* 1556 * PCI backends are initialized before routing INTx interrupts 1557 * so that LPC devices are able to reserve ISA IRQs before 1558 * routing PIRQ pins. 1559 */ 1560 for (bus = 0; bus < MAXBUSES; bus++) { 1561 if ((bi = pci_businfo[bus]) == NULL) 1562 continue; 1563 1564 for (slot = 0; slot < MAXSLOTS; slot++) { 1565 si = &bi->slotinfo[slot]; 1566 for (func = 0; func < MAXFUNCS; func++) { 1567 fi = &si->si_funcs[func]; 1568 if (fi->fi_devi == NULL) 1569 continue; 1570 pci_lintr_route(fi->fi_devi); 1571 } 1572 } 1573 } 1574 lpc_pirq_routed(); 1575 #endif 1576 1577 if ((error = init_bootorder()) != 0) { 1578 warnx("%s: Unable to init bootorder", __func__); 1579 return (error); 1580 } 1581 1582 /* 1583 * The guest physical memory map looks like the following: 1584 * [0, lowmem) guest system memory 1585 * [lowmem, 0xC0000000) memory hole (may be absent) 1586 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1587 * [0xE0000000, 0xF0000000) PCI extended config window 1588 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1589 * [4GB, 4GB + highmem) 1590 */ 1591 1592 /* 1593 * Accesses to memory addresses that are not allocated to system 1594 * memory or PCI devices return 0xff's. 1595 */ 1596 lowmem = vm_get_lowmem_size(ctx); 1597 bzero(&mr, sizeof(struct mem_range)); 1598 mr.name = "PCI hole"; 1599 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1600 mr.base = lowmem; 1601 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1602 mr.handler = pci_emul_fallback_handler; 1603 error = register_mem_fallback(&mr); 1604 assert(error == 0); 1605 1606 /* PCI extended config space */ 1607 bzero(&mr, sizeof(struct mem_range)); 1608 mr.name = "PCI ECFG"; 1609 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1610 mr.base = PCI_EMUL_ECFG_BASE; 1611 mr.size = PCI_EMUL_ECFG_SIZE; 1612 mr.handler = pci_emul_ecfg_handler; 1613 error = register_mem(&mr); 1614 assert(error == 0); 1615 1616 return (0); 1617 } 1618 1619 #ifdef __amd64__ 1620 static void 1621 pci_apic_prt_entry(int bus __unused, int slot, int pin, int pirq_pin __unused, 1622 int ioapic_irq, void *arg __unused) 1623 { 1624 1625 dsdt_line(" Package ()"); 1626 dsdt_line(" {"); 1627 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1628 dsdt_line(" 0x%02X,", pin - 1); 1629 dsdt_line(" Zero,"); 1630 dsdt_line(" 0x%X", ioapic_irq); 1631 dsdt_line(" },"); 1632 } 1633 1634 static void 1635 pci_pirq_prt_entry(int bus __unused, int slot, int pin, int pirq_pin, 1636 int ioapic_irq __unused, void *arg __unused) 1637 { 1638 char *name; 1639 1640 name = lpc_pirq_name(pirq_pin); 1641 if (name == NULL) 1642 return; 1643 dsdt_line(" Package ()"); 1644 dsdt_line(" {"); 1645 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1646 dsdt_line(" 0x%02X,", pin - 1); 1647 dsdt_line(" %s,", name); 1648 dsdt_line(" 0x00"); 1649 dsdt_line(" },"); 1650 free(name); 1651 } 1652 #endif 1653 1654 /* 1655 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1656 * corresponding to each PCI bus. 1657 */ 1658 static void 1659 pci_bus_write_dsdt(int bus) 1660 { 1661 struct businfo *bi; 1662 struct slotinfo *si; 1663 struct pci_devinst *pi; 1664 int func, slot; 1665 1666 /* 1667 * If there are no devices on this 'bus' then just return. 1668 */ 1669 if ((bi = pci_businfo[bus]) == NULL) { 1670 /* 1671 * Bus 0 is special because it decodes the I/O ports used 1672 * for PCI config space access even if there are no devices 1673 * on it. 1674 */ 1675 if (bus != 0) 1676 return; 1677 } 1678 1679 dsdt_line(" Device (PC%02X)", bus); 1680 dsdt_line(" {"); 1681 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1682 1683 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1684 dsdt_line(" {"); 1685 dsdt_line(" Return (0x%08X)", bus); 1686 dsdt_line(" }"); 1687 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1688 dsdt_line(" {"); 1689 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1690 "MaxFixed, PosDecode,"); 1691 dsdt_line(" 0x0000, // Granularity"); 1692 dsdt_line(" 0x%04X, // Range Minimum", bus); 1693 dsdt_line(" 0x%04X, // Range Maximum", bus); 1694 dsdt_line(" 0x0000, // Translation Offset"); 1695 dsdt_line(" 0x0001, // Length"); 1696 dsdt_line(" ,, )"); 1697 1698 if (bus == 0) { 1699 dsdt_indent(3); 1700 dsdt_fixed_ioport(0xCF8, 8); 1701 dsdt_unindent(3); 1702 1703 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1704 "PosDecode, EntireRange,"); 1705 dsdt_line(" 0x0000, // Granularity"); 1706 dsdt_line(" 0x0000, // Range Minimum"); 1707 dsdt_line(" 0x0CF7, // Range Maximum"); 1708 dsdt_line(" 0x0000, // Translation Offset"); 1709 dsdt_line(" 0x0CF8, // Length"); 1710 dsdt_line(" ,, , TypeStatic)"); 1711 1712 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1713 "PosDecode, EntireRange,"); 1714 dsdt_line(" 0x0000, // Granularity"); 1715 dsdt_line(" 0x0D00, // Range Minimum"); 1716 dsdt_line(" 0x%04X, // Range Maximum", 1717 PCI_EMUL_IOBASE - 1); 1718 dsdt_line(" 0x0000, // Translation Offset"); 1719 dsdt_line(" 0x%04X, // Length", 1720 PCI_EMUL_IOBASE - 0x0D00); 1721 dsdt_line(" ,, , TypeStatic)"); 1722 1723 if (bi == NULL) { 1724 dsdt_line(" })"); 1725 goto done; 1726 } 1727 } 1728 assert(bi != NULL); 1729 1730 /* i/o window */ 1731 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1732 "PosDecode, EntireRange,"); 1733 dsdt_line(" 0x0000, // Granularity"); 1734 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1735 dsdt_line(" 0x%04X, // Range Maximum", 1736 bi->iolimit - 1); 1737 dsdt_line(" 0x0000, // Translation Offset"); 1738 dsdt_line(" 0x%04X, // Length", 1739 bi->iolimit - bi->iobase); 1740 dsdt_line(" ,, , TypeStatic)"); 1741 1742 /* mmio window (32-bit) */ 1743 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1744 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1745 dsdt_line(" 0x00000000, // Granularity"); 1746 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1747 dsdt_line(" 0x%08X, // Range Maximum\n", 1748 bi->memlimit32 - 1); 1749 dsdt_line(" 0x00000000, // Translation Offset"); 1750 dsdt_line(" 0x%08X, // Length\n", 1751 bi->memlimit32 - bi->membase32); 1752 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1753 1754 /* mmio window (64-bit) */ 1755 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1756 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1757 dsdt_line(" 0x0000000000000000, // Granularity"); 1758 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1759 dsdt_line(" 0x%016lX, // Range Maximum\n", 1760 bi->memlimit64 - 1); 1761 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1762 dsdt_line(" 0x%016lX, // Length\n", 1763 bi->memlimit64 - bi->membase64); 1764 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1765 dsdt_line(" })"); 1766 1767 #ifdef __amd64__ 1768 if (pci_count_lintr(bus) != 0) { 1769 dsdt_indent(2); 1770 dsdt_line("Name (PPRT, Package ()"); 1771 dsdt_line("{"); 1772 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1773 dsdt_line("})"); 1774 dsdt_line("Name (APRT, Package ()"); 1775 dsdt_line("{"); 1776 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1777 dsdt_line("})"); 1778 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1779 dsdt_line("{"); 1780 dsdt_line(" If (PICM)"); 1781 dsdt_line(" {"); 1782 dsdt_line(" Return (APRT)"); 1783 dsdt_line(" }"); 1784 dsdt_line(" Else"); 1785 dsdt_line(" {"); 1786 dsdt_line(" Return (PPRT)"); 1787 dsdt_line(" }"); 1788 dsdt_line("}"); 1789 dsdt_unindent(2); 1790 } 1791 #endif 1792 1793 dsdt_indent(2); 1794 for (slot = 0; slot < MAXSLOTS; slot++) { 1795 si = &bi->slotinfo[slot]; 1796 for (func = 0; func < MAXFUNCS; func++) { 1797 pi = si->si_funcs[func].fi_devi; 1798 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1799 pi->pi_d->pe_write_dsdt(pi); 1800 } 1801 } 1802 dsdt_unindent(2); 1803 done: 1804 dsdt_line(" }"); 1805 } 1806 1807 void 1808 pci_write_dsdt(void) 1809 { 1810 int bus; 1811 1812 dsdt_indent(1); 1813 dsdt_line("Name (PICM, 0x00)"); 1814 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1815 dsdt_line("{"); 1816 dsdt_line(" Store (Arg0, PICM)"); 1817 dsdt_line("}"); 1818 dsdt_line(""); 1819 dsdt_line("Scope (_SB)"); 1820 dsdt_line("{"); 1821 for (bus = 0; bus < MAXBUSES; bus++) 1822 pci_bus_write_dsdt(bus); 1823 dsdt_line("}"); 1824 dsdt_unindent(1); 1825 } 1826 1827 int 1828 pci_bus_configured(int bus) 1829 { 1830 assert(bus >= 0 && bus < MAXBUSES); 1831 return (pci_businfo[bus] != NULL); 1832 } 1833 1834 int 1835 pci_msi_enabled(struct pci_devinst *pi) 1836 { 1837 return (pi->pi_msi.enabled); 1838 } 1839 1840 int 1841 pci_msi_maxmsgnum(struct pci_devinst *pi) 1842 { 1843 if (pi->pi_msi.enabled) 1844 return (pi->pi_msi.maxmsgnum); 1845 else 1846 return (0); 1847 } 1848 1849 int 1850 pci_msix_enabled(struct pci_devinst *pi) 1851 { 1852 1853 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1854 } 1855 1856 void 1857 pci_generate_msix(struct pci_devinst *pi, int index) 1858 { 1859 struct msix_table_entry *mte; 1860 1861 if (!pci_msix_enabled(pi)) 1862 return; 1863 1864 if (pi->pi_msix.function_mask) 1865 return; 1866 1867 if (index >= pi->pi_msix.table_count) 1868 return; 1869 1870 mte = &pi->pi_msix.table[index]; 1871 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1872 /* XXX Set PBA bit if interrupt is disabled */ 1873 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1874 } 1875 } 1876 1877 void 1878 pci_generate_msi(struct pci_devinst *pi, int index) 1879 { 1880 1881 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1882 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1883 pi->pi_msi.msg_data + index); 1884 } 1885 } 1886 1887 #ifdef __amd64__ 1888 static bool 1889 pci_lintr_permitted(struct pci_devinst *pi) 1890 { 1891 uint16_t cmd; 1892 1893 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1894 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1895 (cmd & PCIM_CMD_INTxDIS))); 1896 } 1897 1898 void 1899 pci_lintr_request(struct pci_devinst *pi) 1900 { 1901 struct businfo *bi; 1902 struct slotinfo *si; 1903 int bestpin, bestcount, pin; 1904 1905 bi = pci_businfo[pi->pi_bus]; 1906 assert(bi != NULL); 1907 1908 /* 1909 * Just allocate a pin from our slot. The pin will be 1910 * assigned IRQs later when interrupts are routed. 1911 */ 1912 si = &bi->slotinfo[pi->pi_slot]; 1913 bestpin = 0; 1914 bestcount = si->si_intpins[0].ii_count; 1915 for (pin = 1; pin < 4; pin++) { 1916 if (si->si_intpins[pin].ii_count < bestcount) { 1917 bestpin = pin; 1918 bestcount = si->si_intpins[pin].ii_count; 1919 } 1920 } 1921 1922 si->si_intpins[bestpin].ii_count++; 1923 pi->pi_lintr.pin = bestpin + 1; 1924 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1925 } 1926 1927 static void 1928 pci_lintr_route(struct pci_devinst *pi) 1929 { 1930 struct businfo *bi; 1931 struct intxinfo *ii; 1932 1933 if (pi->pi_lintr.pin == 0) 1934 return; 1935 1936 bi = pci_businfo[pi->pi_bus]; 1937 assert(bi != NULL); 1938 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1939 1940 /* 1941 * Attempt to allocate an I/O APIC pin for this intpin if one 1942 * is not yet assigned. 1943 */ 1944 if (ii->ii_ioapic_irq == 0) 1945 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1946 assert(ii->ii_ioapic_irq > 0); 1947 1948 /* 1949 * Attempt to allocate a PIRQ pin for this intpin if one is 1950 * not yet assigned. 1951 */ 1952 if (ii->ii_pirq_pin == 0) 1953 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1954 assert(ii->ii_pirq_pin > 0); 1955 1956 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1957 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1958 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1959 } 1960 1961 void 1962 pci_lintr_assert(struct pci_devinst *pi) 1963 { 1964 1965 assert(pi->pi_lintr.pin > 0); 1966 1967 pthread_mutex_lock(&pi->pi_lintr.lock); 1968 if (pi->pi_lintr.state == IDLE) { 1969 if (pci_lintr_permitted(pi)) { 1970 pi->pi_lintr.state = ASSERTED; 1971 pci_irq_assert(pi); 1972 } else 1973 pi->pi_lintr.state = PENDING; 1974 } 1975 pthread_mutex_unlock(&pi->pi_lintr.lock); 1976 } 1977 1978 void 1979 pci_lintr_deassert(struct pci_devinst *pi) 1980 { 1981 1982 assert(pi->pi_lintr.pin > 0); 1983 1984 pthread_mutex_lock(&pi->pi_lintr.lock); 1985 if (pi->pi_lintr.state == ASSERTED) { 1986 pi->pi_lintr.state = IDLE; 1987 pci_irq_deassert(pi); 1988 } else if (pi->pi_lintr.state == PENDING) 1989 pi->pi_lintr.state = IDLE; 1990 pthread_mutex_unlock(&pi->pi_lintr.lock); 1991 } 1992 1993 static void 1994 pci_lintr_update(struct pci_devinst *pi) 1995 { 1996 1997 pthread_mutex_lock(&pi->pi_lintr.lock); 1998 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1999 pci_irq_deassert(pi); 2000 pi->pi_lintr.state = PENDING; 2001 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 2002 pi->pi_lintr.state = ASSERTED; 2003 pci_irq_assert(pi); 2004 } 2005 pthread_mutex_unlock(&pi->pi_lintr.lock); 2006 } 2007 2008 int 2009 pci_count_lintr(int bus) 2010 { 2011 int count, slot, pin; 2012 struct slotinfo *slotinfo; 2013 2014 count = 0; 2015 if (pci_businfo[bus] != NULL) { 2016 for (slot = 0; slot < MAXSLOTS; slot++) { 2017 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2018 for (pin = 0; pin < 4; pin++) { 2019 if (slotinfo->si_intpins[pin].ii_count != 0) 2020 count++; 2021 } 2022 } 2023 } 2024 return (count); 2025 } 2026 2027 void 2028 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2029 { 2030 struct businfo *bi; 2031 struct slotinfo *si; 2032 struct intxinfo *ii; 2033 int slot, pin; 2034 2035 if ((bi = pci_businfo[bus]) == NULL) 2036 return; 2037 2038 for (slot = 0; slot < MAXSLOTS; slot++) { 2039 si = &bi->slotinfo[slot]; 2040 for (pin = 0; pin < 4; pin++) { 2041 ii = &si->si_intpins[pin]; 2042 if (ii->ii_count != 0) 2043 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 2044 ii->ii_ioapic_irq, arg); 2045 } 2046 } 2047 } 2048 #endif /* __amd64__ */ 2049 2050 /* 2051 * Return 1 if the emulated device in 'slot' is a multi-function device. 2052 * Return 0 otherwise. 2053 */ 2054 static int 2055 pci_emul_is_mfdev(int bus, int slot) 2056 { 2057 struct businfo *bi; 2058 struct slotinfo *si; 2059 int f, numfuncs; 2060 2061 numfuncs = 0; 2062 if ((bi = pci_businfo[bus]) != NULL) { 2063 si = &bi->slotinfo[slot]; 2064 for (f = 0; f < MAXFUNCS; f++) { 2065 if (si->si_funcs[f].fi_devi != NULL) { 2066 numfuncs++; 2067 } 2068 } 2069 } 2070 return (numfuncs > 1); 2071 } 2072 2073 /* 2074 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2075 * whether or not is a multi-function being emulated in the pci 'slot'. 2076 */ 2077 static void 2078 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2079 { 2080 int mfdev; 2081 2082 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2083 mfdev = pci_emul_is_mfdev(bus, slot); 2084 switch (bytes) { 2085 case 1: 2086 case 2: 2087 *rv &= ~PCIM_MFDEV; 2088 if (mfdev) { 2089 *rv |= PCIM_MFDEV; 2090 } 2091 break; 2092 case 4: 2093 *rv &= ~(PCIM_MFDEV << 16); 2094 if (mfdev) { 2095 *rv |= (PCIM_MFDEV << 16); 2096 } 2097 break; 2098 } 2099 } 2100 } 2101 2102 /* 2103 * Update device state in response to changes to the PCI command 2104 * register. 2105 */ 2106 void 2107 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2108 { 2109 int i; 2110 uint16_t changed, new; 2111 2112 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2113 changed = old ^ new; 2114 2115 /* 2116 * If the MMIO or I/O address space decoding has changed then 2117 * register/unregister all BARs that decode that address space. 2118 */ 2119 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2120 switch (pi->pi_bar[i].type) { 2121 case PCIBAR_NONE: 2122 case PCIBAR_MEMHI64: 2123 break; 2124 case PCIBAR_IO: 2125 /* I/O address space decoding changed? */ 2126 if (changed & PCIM_CMD_PORTEN) { 2127 if (new & PCIM_CMD_PORTEN) 2128 register_bar(pi, i); 2129 else 2130 unregister_bar(pi, i); 2131 } 2132 break; 2133 case PCIBAR_ROM: 2134 /* skip (un-)register of ROM if it disabled */ 2135 if (!romen(pi)) 2136 break; 2137 /* fallthrough */ 2138 case PCIBAR_MEM32: 2139 case PCIBAR_MEM64: 2140 /* MMIO address space decoding changed? */ 2141 if (changed & PCIM_CMD_MEMEN) { 2142 if (new & PCIM_CMD_MEMEN) 2143 register_bar(pi, i); 2144 else 2145 unregister_bar(pi, i); 2146 } 2147 break; 2148 default: 2149 assert(0); 2150 } 2151 } 2152 2153 #ifdef __amd64__ 2154 /* 2155 * If INTx has been unmasked and is pending, assert the 2156 * interrupt. 2157 */ 2158 pci_lintr_update(pi); 2159 #endif 2160 } 2161 2162 static void 2163 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2164 { 2165 int rshift; 2166 uint32_t cmd, old, readonly; 2167 2168 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2169 2170 /* 2171 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2172 * 2173 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2174 * 'write 1 to clear'. However these bits are not set to '1' by 2175 * any device emulation so it is simpler to treat them as readonly. 2176 */ 2177 rshift = (coff & 0x3) * 8; 2178 readonly = 0xFFFFF880 >> rshift; 2179 2180 old = CFGREAD(pi, coff, bytes); 2181 new &= ~readonly; 2182 new |= (old & readonly); 2183 CFGWRITE(pi, coff, new, bytes); /* update config */ 2184 2185 pci_emul_cmd_changed(pi, cmd); 2186 } 2187 2188 static void 2189 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2190 uint32_t *valp) 2191 { 2192 struct businfo *bi; 2193 struct slotinfo *si; 2194 struct pci_devinst *pi; 2195 struct pci_devemu *pe; 2196 int idx, needcfg; 2197 uint64_t addr, bar, mask; 2198 2199 if ((bi = pci_businfo[bus]) != NULL) { 2200 si = &bi->slotinfo[slot]; 2201 pi = si->si_funcs[func].fi_devi; 2202 } else 2203 pi = NULL; 2204 2205 /* 2206 * Just return if there is no device at this slot:func or if the 2207 * the guest is doing an un-aligned access. 2208 */ 2209 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2210 (coff & (bytes - 1)) != 0) { 2211 if (in) 2212 *valp = 0xffffffff; 2213 return; 2214 } 2215 2216 /* 2217 * Ignore all writes beyond the standard config space and return all 2218 * ones on reads. 2219 */ 2220 if (coff >= PCI_REGMAX + 1) { 2221 if (in) { 2222 *valp = 0xffffffff; 2223 /* 2224 * Extended capabilities begin at offset 256 in config 2225 * space. Absence of extended capabilities is signaled 2226 * with all 0s in the extended capability header at 2227 * offset 256. 2228 */ 2229 if (coff <= PCI_REGMAX + 4) 2230 *valp = 0x00000000; 2231 } 2232 return; 2233 } 2234 2235 pe = pi->pi_d; 2236 2237 /* 2238 * Config read 2239 */ 2240 if (in) { 2241 /* Let the device emulation override the default handler */ 2242 if (pe->pe_cfgread != NULL) { 2243 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); 2244 } else { 2245 needcfg = 1; 2246 } 2247 2248 if (needcfg) 2249 *valp = CFGREAD(pi, coff, bytes); 2250 2251 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp); 2252 } else { 2253 /* Let the device emulation override the default handler */ 2254 if (pe->pe_cfgwrite != NULL && 2255 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) 2256 return; 2257 2258 /* 2259 * Special handling for write to BAR and ROM registers 2260 */ 2261 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2262 /* 2263 * Ignore writes to BAR registers that are not 2264 * 4-byte aligned. 2265 */ 2266 if (bytes != 4 || (coff & 0x3) != 0) 2267 return; 2268 2269 if (is_pcir_bar(coff)) { 2270 idx = (coff - PCIR_BAR(0)) / 4; 2271 } else if (is_pcir_bios(coff)) { 2272 idx = PCI_ROM_IDX; 2273 } else { 2274 errx(4, "%s: invalid BAR offset %d", __func__, 2275 coff); 2276 } 2277 2278 mask = ~(pi->pi_bar[idx].size - 1); 2279 switch (pi->pi_bar[idx].type) { 2280 case PCIBAR_NONE: 2281 pi->pi_bar[idx].addr = bar = 0; 2282 break; 2283 case PCIBAR_IO: 2284 addr = *valp & mask; 2285 addr &= 0xffff; 2286 bar = addr | pi->pi_bar[idx].lobits; 2287 /* 2288 * Register the new BAR value for interception 2289 */ 2290 if (addr != pi->pi_bar[idx].addr) { 2291 update_bar_address(pi, addr, idx, 2292 PCIBAR_IO); 2293 } 2294 break; 2295 case PCIBAR_MEM32: 2296 addr = bar = *valp & mask; 2297 bar |= pi->pi_bar[idx].lobits; 2298 if (addr != pi->pi_bar[idx].addr) { 2299 update_bar_address(pi, addr, idx, 2300 PCIBAR_MEM32); 2301 } 2302 break; 2303 case PCIBAR_MEM64: 2304 addr = bar = *valp & mask; 2305 bar |= pi->pi_bar[idx].lobits; 2306 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2307 update_bar_address(pi, addr, idx, 2308 PCIBAR_MEM64); 2309 } 2310 break; 2311 case PCIBAR_MEMHI64: 2312 mask = ~(pi->pi_bar[idx - 1].size - 1); 2313 addr = ((uint64_t)*valp << 32) & mask; 2314 bar = addr >> 32; 2315 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2316 update_bar_address(pi, addr, idx - 1, 2317 PCIBAR_MEMHI64); 2318 } 2319 break; 2320 case PCIBAR_ROM: 2321 addr = bar = *valp & mask; 2322 if (memen(pi) && romen(pi)) { 2323 unregister_bar(pi, idx); 2324 } 2325 pi->pi_bar[idx].addr = addr; 2326 pi->pi_bar[idx].lobits = *valp & 2327 PCIM_BIOS_ENABLE; 2328 /* romen could have changed it value */ 2329 if (memen(pi) && romen(pi)) { 2330 register_bar(pi, idx); 2331 } 2332 bar |= pi->pi_bar[idx].lobits; 2333 break; 2334 default: 2335 assert(0); 2336 } 2337 pci_set_cfgdata32(pi, coff, bar); 2338 2339 } else if (pci_emul_iscap(pi, coff)) { 2340 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); 2341 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2342 pci_emul_cmdsts_write(pi, coff, *valp, bytes); 2343 } else { 2344 CFGWRITE(pi, coff, *valp, bytes); 2345 } 2346 } 2347 } 2348 2349 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2350 2351 static int 2352 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2353 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2354 { 2355 uint32_t x; 2356 2357 if (bytes != 4) { 2358 if (in) 2359 *eax = (bytes == 2) ? 0xffff : 0xff; 2360 return (0); 2361 } 2362 2363 if (in) { 2364 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2365 if (cfgenable) 2366 x |= CONF1_ENABLE; 2367 *eax = x; 2368 } else { 2369 x = *eax; 2370 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2371 cfgoff = (x & PCI_REGMAX) & ~0x03; 2372 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2373 cfgslot = (x >> 11) & PCI_SLOTMAX; 2374 cfgbus = (x >> 16) & PCI_BUSMAX; 2375 } 2376 2377 return (0); 2378 } 2379 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2380 2381 static int 2382 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2383 int bytes, uint32_t *eax, void *arg __unused) 2384 { 2385 int coff; 2386 2387 assert(bytes == 1 || bytes == 2 || bytes == 4); 2388 2389 coff = cfgoff + (port - CONF1_DATA_PORT); 2390 if (cfgenable) { 2391 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2392 } else { 2393 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2394 if (in) 2395 *eax = 0xffffffff; 2396 } 2397 return (0); 2398 } 2399 2400 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2401 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2402 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2403 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2404 2405 #ifdef BHYVE_SNAPSHOT 2406 /* 2407 * Saves/restores PCI device emulated state. Returns 0 on success. 2408 */ 2409 static int 2410 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2411 { 2412 struct pci_devinst *pi; 2413 int i; 2414 int ret; 2415 2416 pi = meta->dev_data; 2417 2418 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2419 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2420 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2421 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2422 2423 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2424 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2425 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2426 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2427 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2428 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2429 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2430 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2431 2432 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2433 meta, ret, done); 2434 2435 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2436 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2437 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2438 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2439 } 2440 2441 /* Restore MSI-X table. */ 2442 for (i = 0; i < pi->pi_msix.table_count; i++) { 2443 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2444 meta, ret, done); 2445 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2446 meta, ret, done); 2447 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2448 meta, ret, done); 2449 } 2450 2451 done: 2452 return (ret); 2453 } 2454 2455 int 2456 pci_snapshot(struct vm_snapshot_meta *meta) 2457 { 2458 struct pci_devemu *pde; 2459 struct pci_devinst *pdi; 2460 int ret; 2461 2462 assert(meta->dev_name != NULL); 2463 2464 pdi = meta->dev_data; 2465 pde = pdi->pi_d; 2466 2467 if (pde->pe_snapshot == NULL) 2468 return (ENOTSUP); 2469 2470 ret = pci_snapshot_pci_dev(meta); 2471 if (ret == 0) 2472 ret = (*pde->pe_snapshot)(meta); 2473 2474 return (ret); 2475 } 2476 2477 int 2478 pci_pause(struct pci_devinst *pdi) 2479 { 2480 struct pci_devemu *pde = pdi->pi_d; 2481 2482 if (pde->pe_pause == NULL) { 2483 /* The pause/resume functionality is optional. */ 2484 return (0); 2485 } 2486 2487 return (*pde->pe_pause)(pdi); 2488 } 2489 2490 int 2491 pci_resume(struct pci_devinst *pdi) 2492 { 2493 struct pci_devemu *pde = pdi->pi_d; 2494 2495 if (pde->pe_resume == NULL) { 2496 /* The pause/resume functionality is optional. */ 2497 return (0); 2498 } 2499 2500 return (*pde->pe_resume)(pdi); 2501 } 2502 #endif 2503 2504 #define PCI_EMUL_TEST 2505 #ifdef PCI_EMUL_TEST 2506 /* 2507 * Define a dummy test device 2508 */ 2509 #define DIOSZ 8 2510 #define DMEMSZ 4096 2511 struct pci_emul_dsoftc { 2512 uint8_t ioregs[DIOSZ]; 2513 uint8_t memregs[2][DMEMSZ]; 2514 }; 2515 2516 #define PCI_EMUL_MSI_MSGS 4 2517 #define PCI_EMUL_MSIX_MSGS 16 2518 2519 static int 2520 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2521 { 2522 int error; 2523 struct pci_emul_dsoftc *sc; 2524 2525 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2526 2527 pi->pi_arg = sc; 2528 2529 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2530 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2531 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2532 2533 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2534 assert(error == 0); 2535 2536 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2537 assert(error == 0); 2538 2539 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2540 assert(error == 0); 2541 2542 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2543 assert(error == 0); 2544 2545 return (0); 2546 } 2547 2548 static void 2549 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2550 uint64_t value) 2551 { 2552 int i; 2553 struct pci_emul_dsoftc *sc = pi->pi_arg; 2554 2555 if (baridx == 0) { 2556 if (offset + size > DIOSZ) { 2557 printf("diow: iow too large, offset %ld size %d\n", 2558 offset, size); 2559 return; 2560 } 2561 2562 if (size == 1) { 2563 sc->ioregs[offset] = value & 0xff; 2564 } else if (size == 2) { 2565 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2566 } else if (size == 4) { 2567 *(uint32_t *)&sc->ioregs[offset] = value; 2568 } else { 2569 printf("diow: iow unknown size %d\n", size); 2570 } 2571 2572 /* 2573 * Special magic value to generate an interrupt 2574 */ 2575 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2576 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2577 2578 if (value == 0xabcdef) { 2579 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2580 pci_generate_msi(pi, i); 2581 } 2582 } 2583 2584 if (baridx == 1 || baridx == 2) { 2585 if (offset + size > DMEMSZ) { 2586 printf("diow: memw too large, offset %ld size %d\n", 2587 offset, size); 2588 return; 2589 } 2590 2591 i = baridx - 1; /* 'memregs' index */ 2592 2593 if (size == 1) { 2594 sc->memregs[i][offset] = value; 2595 } else if (size == 2) { 2596 *(uint16_t *)&sc->memregs[i][offset] = value; 2597 } else if (size == 4) { 2598 *(uint32_t *)&sc->memregs[i][offset] = value; 2599 } else if (size == 8) { 2600 *(uint64_t *)&sc->memregs[i][offset] = value; 2601 } else { 2602 printf("diow: memw unknown size %d\n", size); 2603 } 2604 2605 /* 2606 * magic interrupt ?? 2607 */ 2608 } 2609 2610 if (baridx > 2 || baridx < 0) { 2611 printf("diow: unknown bar idx %d\n", baridx); 2612 } 2613 } 2614 2615 static uint64_t 2616 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2617 { 2618 struct pci_emul_dsoftc *sc = pi->pi_arg; 2619 uint32_t value; 2620 int i; 2621 2622 if (baridx == 0) { 2623 if (offset + size > DIOSZ) { 2624 printf("dior: ior too large, offset %ld size %d\n", 2625 offset, size); 2626 return (0); 2627 } 2628 2629 value = 0; 2630 if (size == 1) { 2631 value = sc->ioregs[offset]; 2632 } else if (size == 2) { 2633 value = *(uint16_t *) &sc->ioregs[offset]; 2634 } else if (size == 4) { 2635 value = *(uint32_t *) &sc->ioregs[offset]; 2636 } else { 2637 printf("dior: ior unknown size %d\n", size); 2638 } 2639 } 2640 2641 if (baridx == 1 || baridx == 2) { 2642 if (offset + size > DMEMSZ) { 2643 printf("dior: memr too large, offset %ld size %d\n", 2644 offset, size); 2645 return (0); 2646 } 2647 2648 i = baridx - 1; /* 'memregs' index */ 2649 2650 if (size == 1) { 2651 value = sc->memregs[i][offset]; 2652 } else if (size == 2) { 2653 value = *(uint16_t *) &sc->memregs[i][offset]; 2654 } else if (size == 4) { 2655 value = *(uint32_t *) &sc->memregs[i][offset]; 2656 } else if (size == 8) { 2657 value = *(uint64_t *) &sc->memregs[i][offset]; 2658 } else { 2659 printf("dior: ior unknown size %d\n", size); 2660 } 2661 } 2662 2663 2664 if (baridx > 2 || baridx < 0) { 2665 printf("dior: unknown bar idx %d\n", baridx); 2666 return (0); 2667 } 2668 2669 return (value); 2670 } 2671 2672 #ifdef BHYVE_SNAPSHOT 2673 struct pci_devinst * 2674 pci_next(const struct pci_devinst *cursor) 2675 { 2676 unsigned bus = 0, slot = 0, func = 0; 2677 struct businfo *bi; 2678 struct slotinfo *si; 2679 struct funcinfo *fi; 2680 2681 bus = cursor ? cursor->pi_bus : 0; 2682 slot = cursor ? cursor->pi_slot : 0; 2683 func = cursor ? (cursor->pi_func + 1) : 0; 2684 2685 for (; bus < MAXBUSES; bus++) { 2686 if ((bi = pci_businfo[bus]) == NULL) 2687 continue; 2688 2689 if (slot >= MAXSLOTS) 2690 slot = 0; 2691 2692 for (; slot < MAXSLOTS; slot++) { 2693 si = &bi->slotinfo[slot]; 2694 if (func >= MAXFUNCS) 2695 func = 0; 2696 for (; func < MAXFUNCS; func++) { 2697 fi = &si->si_funcs[func]; 2698 if (fi->fi_devi == NULL) 2699 continue; 2700 2701 return (fi->fi_devi); 2702 } 2703 } 2704 } 2705 2706 return (NULL); 2707 } 2708 2709 static int 2710 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2711 { 2712 return (0); 2713 } 2714 #endif 2715 2716 static const struct pci_devemu pci_dummy = { 2717 .pe_emu = "dummy", 2718 .pe_init = pci_emul_dinit, 2719 .pe_barwrite = pci_emul_diow, 2720 .pe_barread = pci_emul_dior, 2721 #ifdef BHYVE_SNAPSHOT 2722 .pe_snapshot = pci_emul_snapshot, 2723 #endif 2724 }; 2725 PCI_EMUL_SET(pci_dummy); 2726 2727 #endif /* PCI_EMUL_TEST */ 2728