1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/types.h> 31 #include <machine/vmm.h> 32 #include <machine/vmm_snapshot.h> 33 34 #include <err.h> 35 #include <stdio.h> 36 #include <stdlib.h> 37 #include <string.h> 38 39 #include <vmmapi.h> 40 41 #include "acpi.h" 42 #include "debug.h" 43 #include "bootrom.h" 44 #include "config.h" 45 #include "inout.h" 46 #include "pci_emul.h" 47 #include "pci_irq.h" 48 #include "pci_lpc.h" 49 #include "pci_passthru.h" 50 #include "pctestdev.h" 51 #include "tpm_device.h" 52 #include "uart_emul.h" 53 54 #define IO_ICU1 0x20 55 #define IO_ICU2 0xA0 56 57 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 58 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 59 60 #define ELCR_PORT 0x4d0 61 SYSRES_IO(ELCR_PORT, 2); 62 63 #define IO_TIMER1_PORT 0x40 64 65 #define NMISC_PORT 0x61 66 SYSRES_IO(NMISC_PORT, 1); 67 68 static struct pci_devinst *lpc_bridge; 69 70 #define LPC_UART_NUM 4 71 static struct lpc_uart_softc { 72 struct uart_ns16550_softc *uart_softc; 73 int iobase; 74 int irq; 75 int enabled; 76 } lpc_uart_softc[LPC_UART_NUM]; 77 78 static const char *lpc_uart_names[LPC_UART_NUM] = { 79 "com1", "com2", "com3", "com4" 80 }; 81 82 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 83 "COM1", "COM2", "COM3", "COM4" 84 }; 85 86 /* 87 * LPC device configuration is in the following form: 88 * <lpc_device_name>[,<options>] 89 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 90 */ 91 int 92 lpc_device_parse(const char *opts) 93 { 94 int unit, error; 95 char *str, *cpy, *lpcdev, *node_name; 96 const char *romfile, *varfile, *tpm_type, *tpm_path; 97 98 error = -1; 99 str = cpy = strdup(opts); 100 lpcdev = strsep(&str, ","); 101 if (lpcdev != NULL) { 102 if (strcasecmp(lpcdev, "bootrom") == 0) { 103 romfile = strsep(&str, ","); 104 if (romfile == NULL) { 105 errx(4, "invalid bootrom option \"%s\"", opts); 106 } 107 set_config_value("bootrom", romfile); 108 109 varfile = strsep(&str, ","); 110 if (varfile == NULL) { 111 error = 0; 112 goto done; 113 } 114 if (strchr(varfile, '=') == NULL) { 115 set_config_value("bootvars", varfile); 116 } else { 117 /* varfile doesn't exist, it's another config 118 * option */ 119 pci_parse_legacy_config(find_config_node("lpc"), 120 varfile); 121 } 122 123 pci_parse_legacy_config(find_config_node("lpc"), str); 124 error = 0; 125 goto done; 126 } 127 if (strcasecmp(lpcdev, "tpm") == 0) { 128 nvlist_t *nvl = create_config_node("tpm"); 129 130 tpm_type = strsep(&str, ","); 131 if (tpm_type == NULL) { 132 errx(4, "invalid tpm type \"%s\"", opts); 133 } 134 set_config_value_node(nvl, "type", tpm_type); 135 136 tpm_path = strsep(&str, ","); 137 if (tpm_path == NULL) { 138 errx(4, "invalid tpm path \"%s\"", opts); 139 } 140 set_config_value_node(nvl, "path", tpm_path); 141 142 pci_parse_legacy_config(find_config_node("tpm"), str); 143 144 set_config_value_node_if_unset(nvl, "version", "2.0"); 145 error = 0; 146 goto done; 147 } 148 for (unit = 0; unit < LPC_UART_NUM; unit++) { 149 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 150 asprintf(&node_name, "lpc.%s.path", 151 lpc_uart_names[unit]); 152 set_config_value(node_name, str); 153 free(node_name); 154 error = 0; 155 goto done; 156 } 157 } 158 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 159 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 160 set_config_bool(node_name, true); 161 free(node_name); 162 error = 0; 163 goto done; 164 } 165 } 166 167 done: 168 free(cpy); 169 170 return (error); 171 } 172 173 void 174 lpc_print_supported_devices(void) 175 { 176 size_t i; 177 178 printf("bootrom\n"); 179 for (i = 0; i < LPC_UART_NUM; i++) 180 printf("%s\n", lpc_uart_names[i]); 181 printf("tpm\n"); 182 printf("%s\n", pctestdev_getname()); 183 } 184 185 const char * 186 lpc_fwcfg(void) 187 { 188 return (get_config_value("lpc.fwcfg")); 189 } 190 191 static void 192 lpc_uart_intr_assert(void *arg) 193 { 194 struct lpc_uart_softc *sc = arg; 195 196 assert(sc->irq >= 0); 197 198 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 199 } 200 201 static void 202 lpc_uart_intr_deassert(void *arg __unused) 203 { 204 /* 205 * The COM devices on the LPC bus generate edge triggered interrupts, 206 * so nothing more to do here. 207 */ 208 } 209 210 static int 211 lpc_uart_io_handler(struct vmctx *ctx __unused, int in, 212 int port, int bytes, uint32_t *eax, void *arg) 213 { 214 int offset; 215 struct lpc_uart_softc *sc = arg; 216 217 offset = port - sc->iobase; 218 219 switch (bytes) { 220 case 1: 221 if (in) 222 *eax = uart_ns16550_read(sc->uart_softc, offset); 223 else 224 uart_ns16550_write(sc->uart_softc, offset, *eax); 225 break; 226 case 2: 227 if (in) { 228 *eax = uart_ns16550_read(sc->uart_softc, offset); 229 *eax |= 230 uart_ns16550_read(sc->uart_softc, offset + 1) << 8; 231 } else { 232 uart_ns16550_write(sc->uart_softc, offset, *eax); 233 uart_ns16550_write(sc->uart_softc, offset + 1, 234 *eax >> 8); 235 } 236 break; 237 default: 238 return (-1); 239 } 240 241 return (0); 242 } 243 244 static int 245 lpc_init(struct vmctx *ctx) 246 { 247 struct lpc_uart_softc *sc; 248 struct inout_port iop; 249 const char *backend, *name; 250 char *node_name; 251 int unit, error; 252 253 /* COM1 and COM2 */ 254 for (unit = 0; unit < LPC_UART_NUM; unit++) { 255 sc = &lpc_uart_softc[unit]; 256 name = lpc_uart_names[unit]; 257 258 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 259 EPRINTLN("Unable to allocate resources for " 260 "LPC device %s", name); 261 return (-1); 262 } 263 pci_irq_reserve(sc->irq); 264 265 sc->uart_softc = uart_ns16550_init(lpc_uart_intr_assert, 266 lpc_uart_intr_deassert, sc); 267 268 asprintf(&node_name, "lpc.%s.path", name); 269 backend = get_config_value(node_name); 270 free(node_name); 271 if (backend != NULL && 272 uart_ns16550_tty_open(sc->uart_softc, backend) != 0) { 273 EPRINTLN("Unable to initialize backend '%s' " 274 "for LPC device %s", backend, name); 275 return (-1); 276 } 277 278 bzero(&iop, sizeof(struct inout_port)); 279 iop.name = name; 280 iop.port = sc->iobase; 281 iop.size = UART_NS16550_IO_BAR_SIZE; 282 iop.flags = IOPORT_F_INOUT; 283 iop.handler = lpc_uart_io_handler; 284 iop.arg = sc; 285 286 error = register_inout(&iop); 287 assert(error == 0); 288 sc->enabled = 1; 289 } 290 291 /* pc-testdev */ 292 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 293 if (get_config_bool_default(node_name, false)) { 294 error = pctestdev_init(ctx); 295 if (error) 296 return (error); 297 } 298 free(node_name); 299 300 return (0); 301 } 302 303 static void 304 pci_lpc_write_dsdt(struct pci_devinst *pi) 305 { 306 struct lpc_dsdt **ldpp, *ldp; 307 308 dsdt_line(""); 309 dsdt_line("Device (ISA)"); 310 dsdt_line("{"); 311 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 312 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 313 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 314 dsdt_line(" {"); 315 dsdt_line(" Offset (0x60),"); 316 dsdt_line(" PIRA, 8,"); 317 dsdt_line(" PIRB, 8,"); 318 dsdt_line(" PIRC, 8,"); 319 dsdt_line(" PIRD, 8,"); 320 dsdt_line(" Offset (0x68),"); 321 dsdt_line(" PIRE, 8,"); 322 dsdt_line(" PIRF, 8,"); 323 dsdt_line(" PIRG, 8,"); 324 dsdt_line(" PIRH, 8"); 325 dsdt_line(" }"); 326 dsdt_line(""); 327 328 dsdt_indent(1); 329 SET_FOREACH(ldpp, lpc_dsdt_set) { 330 ldp = *ldpp; 331 ldp->handler(); 332 } 333 334 dsdt_line(""); 335 dsdt_line("Device (PIC)"); 336 dsdt_line("{"); 337 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 338 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 339 dsdt_line(" {"); 340 dsdt_indent(2); 341 dsdt_fixed_ioport(IO_ICU1, 2); 342 dsdt_fixed_ioport(IO_ICU2, 2); 343 dsdt_fixed_irq(2); 344 dsdt_unindent(2); 345 dsdt_line(" })"); 346 dsdt_line("}"); 347 348 dsdt_line(""); 349 dsdt_line("Device (TIMR)"); 350 dsdt_line("{"); 351 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 352 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 353 dsdt_line(" {"); 354 dsdt_indent(2); 355 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 356 dsdt_fixed_irq(0); 357 dsdt_unindent(2); 358 dsdt_line(" })"); 359 dsdt_line("}"); 360 dsdt_unindent(1); 361 362 dsdt_line("}"); 363 } 364 365 static void 366 pci_lpc_sysres_dsdt(void) 367 { 368 struct lpc_sysres **lspp, *lsp; 369 370 dsdt_line(""); 371 dsdt_line("Device (SIO)"); 372 dsdt_line("{"); 373 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 374 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 375 dsdt_line(" {"); 376 377 dsdt_indent(2); 378 SET_FOREACH(lspp, lpc_sysres_set) { 379 lsp = *lspp; 380 switch (lsp->type) { 381 case LPC_SYSRES_IO: 382 dsdt_fixed_ioport(lsp->base, lsp->length); 383 break; 384 case LPC_SYSRES_MEM: 385 dsdt_fixed_mem32(lsp->base, lsp->length); 386 break; 387 } 388 } 389 dsdt_unindent(2); 390 391 dsdt_line(" })"); 392 dsdt_line("}"); 393 } 394 LPC_DSDT(pci_lpc_sysres_dsdt); 395 396 static void 397 pci_lpc_uart_dsdt(void) 398 { 399 struct lpc_uart_softc *sc; 400 int unit; 401 402 for (unit = 0; unit < LPC_UART_NUM; unit++) { 403 sc = &lpc_uart_softc[unit]; 404 if (!sc->enabled) 405 continue; 406 dsdt_line(""); 407 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 408 dsdt_line("{"); 409 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 410 dsdt_line(" Name (_UID, %d)", unit + 1); 411 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 412 dsdt_line(" {"); 413 dsdt_indent(2); 414 dsdt_fixed_ioport(sc->iobase, UART_NS16550_IO_BAR_SIZE); 415 dsdt_fixed_irq(sc->irq); 416 dsdt_unindent(2); 417 dsdt_line(" })"); 418 dsdt_line("}"); 419 } 420 } 421 LPC_DSDT(pci_lpc_uart_dsdt); 422 423 static int 424 pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 425 { 426 int pirq_pin; 427 428 if (bytes == 1) { 429 pirq_pin = 0; 430 if (coff >= 0x60 && coff <= 0x63) 431 pirq_pin = coff - 0x60 + 1; 432 if (coff >= 0x68 && coff <= 0x6b) 433 pirq_pin = coff - 0x68 + 5; 434 if (pirq_pin != 0) { 435 pirq_write(pi->pi_vmctx, pirq_pin, val); 436 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 437 return (0); 438 } 439 } 440 return (-1); 441 } 442 443 static void 444 pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused, 445 uint64_t offset __unused, int size __unused, uint64_t value __unused) 446 { 447 } 448 449 static uint64_t 450 pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused, 451 uint64_t offset __unused, int size __unused) 452 { 453 return (0); 454 } 455 456 #define LPC_DEV 0x7000 457 #define LPC_VENDOR 0x8086 458 #define LPC_REVID 0x00 459 #define LPC_SUBVEND_0 0x0000 460 #define LPC_SUBDEV_0 0x0000 461 462 static int 463 pci_lpc_get_sel(struct pcisel *const sel) 464 { 465 assert(sel != NULL); 466 467 memset(sel, 0, sizeof(*sel)); 468 469 for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) { 470 uint8_t max_func = 0; 471 472 sel->pc_dev = slot; 473 sel->pc_func = 0; 474 475 if (pci_host_read_config(sel, PCIR_HDRTYPE, 1) & PCIM_MFDEV) 476 max_func = PCI_FUNCMAX; 477 478 for (uint8_t func = 0; func <= max_func; ++func) { 479 sel->pc_func = func; 480 481 if (pci_host_read_config(sel, PCIR_CLASS, 1) == 482 PCIC_BRIDGE && 483 pci_host_read_config(sel, PCIR_SUBCLASS, 1) == 484 PCIS_BRIDGE_ISA) { 485 return (0); 486 } 487 } 488 } 489 490 warnx("%s: Unable to find host selector of LPC bridge.", __func__); 491 492 return (-1); 493 } 494 495 static int 496 pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl) 497 { 498 struct pcisel sel = { 0 }; 499 struct pcisel *selp = NULL; 500 uint16_t device, subdevice, subvendor, vendor; 501 uint8_t revid; 502 503 /* 504 * Do not allow more than one LPC bridge to be configured. 505 */ 506 if (lpc_bridge != NULL) { 507 EPRINTLN("Only one LPC bridge is allowed."); 508 return (-1); 509 } 510 511 /* 512 * Enforce that the LPC can only be configured on bus 0. This 513 * simplifies the ACPI DSDT because it can provide a decode for 514 * all legacy i/o ports behind bus 0. 515 */ 516 if (pi->pi_bus != 0) { 517 EPRINTLN("LPC bridge can be present only on bus 0."); 518 return (-1); 519 } 520 521 if (lpc_init(pi->pi_vmctx) != 0) 522 return (-1); 523 524 if (pci_lpc_get_sel(&sel) == 0) 525 selp = &sel; 526 527 vendor = pci_config_read_reg(selp, nvl, PCIR_VENDOR, 2, LPC_VENDOR); 528 device = pci_config_read_reg(selp, nvl, PCIR_DEVICE, 2, LPC_DEV); 529 revid = pci_config_read_reg(selp, nvl, PCIR_REVID, 1, LPC_REVID); 530 subvendor = pci_config_read_reg(selp, nvl, PCIR_SUBVEND_0, 2, 531 LPC_SUBVEND_0); 532 subdevice = pci_config_read_reg(selp, nvl, PCIR_SUBDEV_0, 2, 533 LPC_SUBDEV_0); 534 535 /* initialize config space */ 536 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 537 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 538 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 539 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 540 pci_set_cfgdata8(pi, PCIR_REVID, revid); 541 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, subvendor); 542 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, subdevice); 543 544 lpc_bridge = pi; 545 546 return (0); 547 } 548 549 char * 550 lpc_pirq_name(int pin) 551 { 552 char *name; 553 554 if (lpc_bridge == NULL) 555 return (NULL); 556 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 557 return (name); 558 } 559 560 void 561 lpc_pirq_routed(void) 562 { 563 int pin; 564 565 if (lpc_bridge == NULL) 566 return; 567 568 for (pin = 0; pin < 4; pin++) 569 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 570 for (pin = 0; pin < 4; pin++) 571 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 572 } 573 574 #ifdef BHYVE_SNAPSHOT 575 static int 576 pci_lpc_snapshot(struct vm_snapshot_meta *meta) 577 { 578 int unit, ret; 579 struct uart_ns16550_softc *sc; 580 581 for (unit = 0; unit < LPC_UART_NUM; unit++) { 582 sc = lpc_uart_softc[unit].uart_softc; 583 584 ret = uart_ns16550_snapshot(sc, meta); 585 if (ret != 0) 586 goto done; 587 } 588 589 done: 590 return (ret); 591 } 592 #endif 593 594 static const struct pci_devemu pci_de_lpc = { 595 .pe_emu = "lpc", 596 .pe_init = pci_lpc_init, 597 .pe_write_dsdt = pci_lpc_write_dsdt, 598 .pe_cfgwrite = pci_lpc_cfgwrite, 599 .pe_barwrite = pci_lpc_write, 600 .pe_barread = pci_lpc_read, 601 #ifdef BHYVE_SNAPSHOT 602 .pe_snapshot = pci_lpc_snapshot, 603 #endif 604 }; 605 PCI_EMUL_SET(pci_de_lpc); 606