1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015, 2024 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef __X86_IOMMU_X86_IOMMU_H 32 #define __X86_IOMMU_X86_IOMMU_H 33 34 /* Both Intel and AMD are not too crazy to have different sizes. */ 35 typedef struct iommu_pte { 36 uint64_t pte; 37 } iommu_pte_t; 38 39 #define IOMMU_PAGE_SIZE PAGE_SIZE 40 #define IOMMU_PAGE_MASK (IOMMU_PAGE_SIZE - 1) 41 #define IOMMU_PAGE_SHIFT PAGE_SHIFT 42 #define IOMMU_NPTEPG (IOMMU_PAGE_SIZE / sizeof(iommu_pte_t)) 43 #define IOMMU_NPTEPGSHIFT 9 44 #define IOMMU_PTEMASK (IOMMU_NPTEPG - 1) 45 46 struct sf_buf; 47 struct vm_object; 48 49 struct vm_page *iommu_pgalloc(struct vm_object *obj, vm_pindex_t idx, 50 int flags); 51 void iommu_pgfree(struct vm_object *obj, vm_pindex_t idx, int flags); 52 void *iommu_map_pgtbl(struct vm_object *obj, vm_pindex_t idx, int flags, 53 struct sf_buf **sf); 54 void iommu_unmap_pgtbl(struct sf_buf *sf); 55 56 extern iommu_haddr_t iommu_high; 57 extern int iommu_tbl_pagecnt; 58 59 SYSCTL_DECL(_hw_iommu); 60 SYSCTL_DECL(_hw_iommu_dmar); 61 62 struct x86_unit_common; 63 64 struct x86_iommu { 65 struct x86_unit_common *(*get_x86_common)(struct 66 iommu_unit *iommu); 67 void (*qi_ensure)(struct iommu_unit *unit, int descr_count); 68 void (*qi_emit_wait_descr)(struct iommu_unit *unit, uint32_t seq, 69 bool, bool, bool); 70 void (*qi_advance_tail)(struct iommu_unit *unit); 71 void (*qi_invalidate_emit)(struct iommu_domain *idomain, 72 iommu_gaddr_t base, iommu_gaddr_t size, struct iommu_qi_genseq * 73 pseq, bool emit_wait); 74 void (*domain_unload_entry)(struct iommu_map_entry *entry, bool free, 75 bool cansleep); 76 void (*domain_unload)(struct iommu_domain *iodom, 77 struct iommu_map_entries_tailq *entries, bool cansleep); 78 struct iommu_ctx *(*get_ctx)(struct iommu_unit *iommu, 79 device_t dev, uint16_t rid, bool id_mapped, bool rmrr_init); 80 void (*free_ctx_locked)(struct iommu_unit *iommu, 81 struct iommu_ctx *context); 82 void (*free_ctx)(struct iommu_ctx *context); 83 struct iommu_unit *(*find)(device_t dev, bool verbose); 84 int (*alloc_msi_intr)(device_t src, u_int *cookies, u_int count); 85 int (*map_msi_intr)(device_t src, u_int cpu, u_int vector, 86 u_int cookie, uint64_t *addr, uint32_t *data); 87 int (*unmap_msi_intr)(device_t src, u_int cookie); 88 int (*map_ioapic_intr)(u_int ioapic_id, u_int cpu, u_int vector, 89 bool edge, bool activehi, int irq, u_int *cookie, uint32_t *hi, 90 uint32_t *lo); 91 int (*unmap_ioapic_intr)(u_int ioapic_id, u_int *cookie); 92 }; 93 void set_x86_iommu(struct x86_iommu *); 94 struct x86_iommu *get_x86_iommu(void); 95 96 struct iommu_msi_data { 97 int irq; 98 int irq_rid; 99 struct resource *irq_res; 100 void *intr_handle; 101 int (*handler)(void *); 102 int msi_data_reg; 103 int msi_addr_reg; 104 int msi_uaddr_reg; 105 uint64_t msi_addr; 106 uint32_t msi_data; 107 void (*enable_intr)(struct iommu_unit *); 108 void (*disable_intr)(struct iommu_unit *); 109 const char *name; 110 }; 111 112 #define IOMMU_MAX_MSI 3 113 114 struct x86_unit_common { 115 uint32_t qi_buf_maxsz; 116 uint32_t qi_cmd_sz; 117 118 char *inv_queue; 119 vm_size_t inv_queue_size; 120 uint32_t inv_queue_avail; 121 uint32_t inv_queue_tail; 122 123 /* 124 * Hw writes there on completion of wait descriptor 125 * processing. Intel writes 4 bytes, while AMD does the 126 * 8-bytes write. Due to little-endian, and use of 4-byte 127 * sequence numbers, the difference does not matter for us. 128 */ 129 volatile uint64_t inv_waitd_seq_hw; 130 131 uint64_t inv_waitd_seq_hw_phys; 132 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 133 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 134 u_int inv_seq_waiters; /* count of waiters for seq */ 135 u_int inv_queue_full; /* informational counter */ 136 137 /* 138 * Delayed freeing of map entries queue processing: 139 * 140 * tlb_flush_head and tlb_flush_tail are used to implement a FIFO 141 * queue that supports concurrent dequeues and enqueues. However, 142 * there can only be a single dequeuer (accessing tlb_flush_head) and 143 * a single enqueuer (accessing tlb_flush_tail) at a time. Since the 144 * unit's qi_task is the only dequeuer, it can access tlb_flush_head 145 * without any locking. In contrast, there may be multiple enqueuers, 146 * so the enqueuers acquire the iommu unit lock to serialize their 147 * accesses to tlb_flush_tail. 148 * 149 * In this FIFO queue implementation, the key to enabling concurrent 150 * dequeues and enqueues is that the dequeuer never needs to access 151 * tlb_flush_tail and the enqueuer never needs to access 152 * tlb_flush_head. In particular, tlb_flush_head and tlb_flush_tail 153 * are never NULL, so neither a dequeuer nor an enqueuer ever needs to 154 * update both. Instead, tlb_flush_head always points to a "zombie" 155 * struct, which previously held the last dequeued item. Thus, the 156 * zombie's next field actually points to the struct holding the first 157 * item in the queue. When an item is dequeued, the current zombie is 158 * finally freed, and the struct that held the just dequeued item 159 * becomes the new zombie. When the queue is empty, tlb_flush_tail 160 * also points to the zombie. 161 */ 162 struct iommu_map_entry *tlb_flush_head; 163 struct iommu_map_entry *tlb_flush_tail; 164 struct task qi_task; 165 struct taskqueue *qi_taskqueue; 166 167 struct iommu_msi_data intrs[IOMMU_MAX_MSI]; 168 }; 169 170 void iommu_domain_free_entry(struct iommu_map_entry *entry, bool free); 171 172 void iommu_qi_emit_wait_seq(struct iommu_unit *unit, struct iommu_qi_genseq * 173 pseq, bool emit_wait); 174 void iommu_qi_wait_for_seq(struct iommu_unit *unit, const struct 175 iommu_qi_genseq *gseq, bool nowait); 176 void iommu_qi_drain_tlb_flush(struct iommu_unit *unit); 177 void iommu_qi_invalidate_locked(struct iommu_domain *domain, 178 struct iommu_map_entry *entry, bool emit_wait); 179 void iommu_qi_invalidate_sync(struct iommu_domain *domain, iommu_gaddr_t base, 180 iommu_gaddr_t size, bool cansleep); 181 void iommu_qi_common_init(struct iommu_unit *unit, task_fn_t taskfunc); 182 void iommu_qi_common_fini(struct iommu_unit *unit, void (*disable_qi)( 183 struct iommu_unit *)); 184 185 int iommu_alloc_irq(struct iommu_unit *unit, int idx); 186 void iommu_release_intr(struct iommu_unit *unit, int idx); 187 188 void iommu_device_tag_init(struct iommu_ctx *ctx, device_t dev); 189 190 int pglvl_pgtbl_pte_off(int pglvl, iommu_gaddr_t base, int lvl); 191 vm_pindex_t pglvl_pgtbl_get_pindex(int pglvl, iommu_gaddr_t base, int lvl); 192 vm_pindex_t pglvl_max_pages(int pglvl); 193 iommu_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 194 195 #endif 196