1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _X86_APICVAR_H_ 31 #define _X86_APICVAR_H_ 32 33 /* 34 * Local && I/O APIC variable definitions. 35 */ 36 37 /* 38 * Layout of local APIC interrupt vectors: 39 * 40 * 0xff (255) +-------------+ 41 * | | 15 (Spurious / IPIs / Local Interrupts) 42 * 0xf0 (240) +-------------+ 43 * | | 14 (I/O Interrupts / Timer) 44 * 0xe0 (224) +-------------+ 45 * | | 13 (I/O Interrupts) 46 * 0xd0 (208) +-------------+ 47 * | | 12 (I/O Interrupts) 48 * 0xc0 (192) +-------------+ 49 * | | 11 (I/O Interrupts) 50 * 0xb0 (176) +-------------+ 51 * | | 10 (I/O Interrupts) 52 * 0xa0 (160) +-------------+ 53 * | | 9 (I/O Interrupts) 54 * 0x90 (144) +-------------+ 55 * | | 8 (I/O Interrupts / System Calls) 56 * 0x80 (128) +-------------+ 57 * | | 7 (I/O Interrupts) 58 * 0x70 (112) +-------------+ 59 * | | 6 (I/O Interrupts) 60 * 0x60 (96) +-------------+ 61 * | | 5 (I/O Interrupts) 62 * 0x50 (80) +-------------+ 63 * | | 4 (I/O Interrupts) 64 * 0x40 (64) +-------------+ 65 * | | 3 (I/O Interrupts) 66 * 0x30 (48) +-------------+ 67 * | | 2 (ATPIC Interrupts) 68 * 0x20 (32) +-------------+ 69 * | | 1 (Exceptions, traps, faults, etc.) 70 * 0x10 (16) +-------------+ 71 * | | 0 (Exceptions, traps, faults, etc.) 72 * 0x00 (0) +-------------+ 73 * 74 * Note: 0x80 needs to be handled specially and not allocated to an 75 * I/O device! 76 */ 77 78 #define xAPIC_MAX_APIC_ID 0xfe 79 #define xAPIC_ID_ALL 0xff 80 #define MAX_APIC_ID 0x200 81 #define APIC_ID_ALL 0xffffffff 82 83 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 84 85 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 86 #define APIC_IO_INTS (IDT_IO_INTS + 16) 87 #define APIC_NUM_IOINTS 191 88 89 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 90 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 91 92 /* 93 ********************* !!! WARNING !!! ****************************** 94 * Each local apic has an interrupt receive fifo that is two entries deep 95 * for each interrupt priority class (higher 4 bits of interrupt vector). 96 * Once the fifo is full the APIC can no longer receive interrupts for this 97 * class and sending IPIs from other CPUs will be blocked. 98 * To avoid deadlocks there should be no more than two IPI interrupts 99 * pending at the same time. 100 * Currently this is guaranteed by dividing the IPIs in two groups that have 101 * each at most one IPI interrupt pending. The first group is protected by the 102 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 103 * at a time) The second group uses a single interrupt and a bitmap to avoid 104 * redundant IPI interrupts. 105 */ 106 107 /* Interrupts for local APIC LVT entries other than the timer. */ 108 #define APIC_LOCAL_INTS 240 109 #define APIC_ERROR_INT APIC_LOCAL_INTS 110 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 111 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 112 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 113 114 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 115 #define IPI_INVLOP (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, amd64 */ 116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, i386 */ 117 #define IPI_INVLPG (APIC_IPI_INTS + 2) 118 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 119 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 120 /* Vector to handle bitmap based IPIs */ 121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 122 123 /* IPIs handled by IPI_BITMAP_VECTOR */ 124 #define IPI_AST 0 /* Generate software trap. */ 125 #define IPI_PREEMPT 1 126 #define IPI_HARDCLOCK 2 127 #define IPI_TRACE 3 /* Collect stack trace. */ 128 #define IPI_BITMAP_LAST IPI_TRACE 129 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 130 131 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 132 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 133 #define IPI_SWI (APIC_IPI_INTS + 8) /* Run clk_intr_event. */ 134 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 135 #define IPI_DYN_LAST (254) /* IPIs allocated at runtime */ 136 137 /* 138 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 139 * it is delivered using an NMI anyways. 140 */ 141 #define IPI_NMI_FIRST 255 142 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 143 144 /* 145 * The spurious interrupt can share the priority class with the IPIs since 146 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 147 */ 148 #define APIC_SPURIOUS_INT 255 149 150 #ifndef LOCORE 151 152 #define APIC_IPI_DEST_SELF -1 153 #define APIC_IPI_DEST_ALL -2 154 #define APIC_IPI_DEST_OTHERS -3 155 156 #define APIC_BUS_UNKNOWN -1 157 #define APIC_BUS_ISA 0 158 #define APIC_BUS_EISA 1 159 #define APIC_BUS_PCI 2 160 #define APIC_BUS_MAX APIC_BUS_PCI 161 162 #define IRQ_EXTINT -1 163 #define IRQ_NMI -2 164 #define IRQ_SMI -3 165 #define IRQ_DISABLED -4 166 167 /* 168 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including 169 * CPU's and I/O APIC's. 170 */ 171 struct apic_enumerator { 172 const char *apic_name; 173 int (*apic_probe)(void); 174 int (*apic_probe_cpus)(void); 175 int (*apic_setup_local)(void); 176 int (*apic_setup_io)(void); 177 SLIST_ENTRY(apic_enumerator) apic_next; 178 }; 179 180 inthand_t 181 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 182 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 183 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 184 IDTVEC(spuriousint), IDTVEC(timerint), 185 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti), 186 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti), 187 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti), 188 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti); 189 190 extern vm_paddr_t lapic_paddr; 191 extern int *apic_cpuids; 192 193 void apic_register_enumerator(struct apic_enumerator *enumerator); 194 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 195 int ioapic_disable_pin(void *cookie, u_int pin); 196 int ioapic_get_vector(void *cookie, u_int pin); 197 void ioapic_register(void *cookie); 198 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 199 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 200 int ioapic_set_extint(void *cookie, u_int pin); 201 int ioapic_set_nmi(void *cookie, u_int pin); 202 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 203 int ioapic_set_triggermode(void *cookie, u_int pin, 204 enum intr_trigger trigger); 205 int ioapic_set_smi(void *cookie, u_int pin); 206 207 /* 208 * Struct containing pointers to APIC functions whose 209 * implementation is run time selectable. 210 */ 211 struct apic_ops { 212 void (*create)(u_int, int); 213 void (*init)(vm_paddr_t); 214 void (*xapic_mode)(void); 215 bool (*is_x2apic)(void); 216 void (*setup)(int); 217 void (*dump)(const char *); 218 void (*disable)(void); 219 void (*eoi)(void); 220 int (*id)(void); 221 int (*intr_pending)(u_int); 222 void (*set_logical_id)(u_int, u_int, u_int); 223 u_int (*cpuid)(u_int); 224 225 /* Vectors */ 226 u_int (*alloc_vector)(u_int, u_int); 227 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 228 void (*enable_vector)(u_int, u_int); 229 void (*disable_vector)(u_int, u_int); 230 void (*free_vector)(u_int, u_int, u_int); 231 232 /* Timer */ 233 void (*calibrate_timer)(void); 234 235 /* PMC */ 236 int (*enable_pmc)(void); 237 void (*disable_pmc)(void); 238 void (*reenable_pmc)(void); 239 240 /* CMC */ 241 void (*enable_cmc)(void); 242 243 /* AMD ELVT */ 244 int (*enable_mca_elvt)(void); 245 246 /* IPI */ 247 void (*ipi_raw)(register_t, u_int); 248 void (*ipi_vectored)(u_int, int); 249 int (*ipi_wait)(int); 250 int (*ipi_alloc)(inthand_t *ipifunc); 251 void (*ipi_free)(int vector); 252 253 /* LVT */ 254 int (*set_lvt_mask)(u_int, u_int, u_char); 255 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 256 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 257 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 258 }; 259 260 extern struct apic_ops apic_ops; 261 262 static inline void 263 lapic_create(u_int apic_id, int boot_cpu) 264 { 265 266 apic_ops.create(apic_id, boot_cpu); 267 } 268 269 static inline void 270 lapic_init(vm_paddr_t addr) 271 { 272 273 apic_ops.init(addr); 274 } 275 276 static inline void 277 lapic_xapic_mode(void) 278 { 279 280 apic_ops.xapic_mode(); 281 } 282 283 static inline bool 284 lapic_is_x2apic(void) 285 { 286 287 return (apic_ops.is_x2apic()); 288 } 289 290 static inline void 291 lapic_setup(int boot) 292 { 293 294 apic_ops.setup(boot); 295 } 296 297 static inline void 298 lapic_dump(const char *str) 299 { 300 301 apic_ops.dump(str); 302 } 303 304 static inline void 305 lapic_disable(void) 306 { 307 308 apic_ops.disable(); 309 } 310 311 static inline void 312 lapic_eoi(void) 313 { 314 315 apic_ops.eoi(); 316 } 317 318 static inline int 319 lapic_id(void) 320 { 321 322 return (apic_ops.id()); 323 } 324 325 static inline int 326 lapic_intr_pending(u_int vector) 327 { 328 329 return (apic_ops.intr_pending(vector)); 330 } 331 332 /* XXX: UNUSED */ 333 static inline void 334 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 335 { 336 337 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 338 } 339 340 static inline u_int 341 apic_cpuid(u_int apic_id) 342 { 343 344 return (apic_ops.cpuid(apic_id)); 345 } 346 347 static inline u_int 348 apic_alloc_vector(u_int apic_id, u_int irq) 349 { 350 351 return (apic_ops.alloc_vector(apic_id, irq)); 352 } 353 354 static inline u_int 355 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 356 { 357 358 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 359 } 360 361 static inline void 362 apic_enable_vector(u_int apic_id, u_int vector) 363 { 364 365 apic_ops.enable_vector(apic_id, vector); 366 } 367 368 static inline void 369 apic_disable_vector(u_int apic_id, u_int vector) 370 { 371 372 apic_ops.disable_vector(apic_id, vector); 373 } 374 375 static inline void 376 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 377 { 378 379 apic_ops.free_vector(apic_id, vector, irq); 380 } 381 382 static inline void 383 lapic_calibrate_timer(void) 384 { 385 386 apic_ops.calibrate_timer(); 387 } 388 389 static inline int 390 lapic_enable_pmc(void) 391 { 392 393 return (apic_ops.enable_pmc()); 394 } 395 396 static inline void 397 lapic_disable_pmc(void) 398 { 399 400 apic_ops.disable_pmc(); 401 } 402 403 static inline void 404 lapic_reenable_pmc(void) 405 { 406 407 apic_ops.reenable_pmc(); 408 } 409 410 static inline void 411 lapic_enable_cmc(void) 412 { 413 414 apic_ops.enable_cmc(); 415 } 416 417 static inline int 418 lapic_enable_mca_elvt(void) 419 { 420 421 return (apic_ops.enable_mca_elvt()); 422 } 423 424 static inline void 425 lapic_ipi_raw(register_t icrlo, u_int dest) 426 { 427 428 apic_ops.ipi_raw(icrlo, dest); 429 } 430 431 static inline void 432 lapic_ipi_vectored(u_int vector, int dest) 433 { 434 435 apic_ops.ipi_vectored(vector, dest); 436 } 437 438 static inline int 439 lapic_ipi_wait(int delay) 440 { 441 442 return (apic_ops.ipi_wait(delay)); 443 } 444 445 static inline int 446 lapic_ipi_alloc(inthand_t *ipifunc) 447 { 448 449 return (apic_ops.ipi_alloc(ipifunc)); 450 } 451 452 static inline void 453 lapic_ipi_free(int vector) 454 { 455 456 return (apic_ops.ipi_free(vector)); 457 } 458 459 static inline int 460 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 461 { 462 463 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 464 } 465 466 static inline int 467 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 468 { 469 470 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 471 } 472 473 static inline int 474 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 475 { 476 477 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 478 } 479 480 static inline int 481 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 482 { 483 484 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 485 } 486 487 void lapic_handle_cmc(void); 488 void lapic_handle_error(void); 489 void lapic_handle_intr(int vector, struct trapframe *frame); 490 void lapic_handle_timer(struct trapframe *frame); 491 492 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 493 494 extern int x2apic_mode; 495 extern int lapic_eoi_suppression; 496 497 #ifdef _SYS_SYSCTL_H_ 498 SYSCTL_DECL(_hw_apic); 499 #endif 500 501 #endif /* !LOCORE */ 502 #endif /* _X86_APICVAR_H_ */ 503