1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _MACHINE_RISCVREG_H_ 36 #define _MACHINE_RISCVREG_H_ 37 38 #define SCAUSE_INTR (1ul << 63) 39 #define SCAUSE_CODE (~SCAUSE_INTR) 40 #define SCAUSE_INST_MISALIGNED 0 41 #define SCAUSE_INST_ACCESS_FAULT 1 42 #define SCAUSE_ILLEGAL_INSTRUCTION 2 43 #define SCAUSE_BREAKPOINT 3 44 #define SCAUSE_LOAD_MISALIGNED 4 45 #define SCAUSE_LOAD_ACCESS_FAULT 5 46 #define SCAUSE_STORE_MISALIGNED 6 47 #define SCAUSE_STORE_ACCESS_FAULT 7 48 #define SCAUSE_ECALL_USER 8 49 #define SCAUSE_ECALL_SUPERVISOR 9 50 #define SCAUSE_INST_PAGE_FAULT 12 51 #define SCAUSE_LOAD_PAGE_FAULT 13 52 #define SCAUSE_STORE_PAGE_FAULT 15 53 54 #define SSTATUS_UIE (1 << 0) 55 #define SSTATUS_SIE (1 << 1) 56 #define SSTATUS_UPIE (1 << 4) 57 #define SSTATUS_SPIE (1 << 5) 58 #define SSTATUS_SPIE_SHIFT 5 59 #define SSTATUS_SPP (1 << 8) 60 #define SSTATUS_SPP_SHIFT 8 61 #define SSTATUS_FS_SHIFT 13 62 #define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT) 63 #define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT) 64 #define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT) 65 #define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT) 66 #define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT) 67 #define SSTATUS_XS_SHIFT 15 68 #define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT) 69 #define SSTATUS_SUM (1 << 18) 70 #if __riscv_xlen == 64 71 #define SSTATUS_SD (1ul << 63) 72 #else 73 #define SSTATUS_SD (1 << 31) 74 #endif 75 76 #define MSTATUS_UIE (1 << 0) 77 #define MSTATUS_SIE (1 << 1) 78 #define MSTATUS_HIE (1 << 2) 79 #define MSTATUS_MIE (1 << 3) 80 #define MSTATUS_UPIE (1 << 4) 81 #define MSTATUS_SPIE (1 << 5) 82 #define MSTATUS_SPIE_SHIFT 5 83 #define MSTATUS_HPIE (1 << 6) 84 #define MSTATUS_MPIE (1 << 7) 85 #define MSTATUS_MPIE_SHIFT 7 86 #define MSTATUS_SPP (1 << 8) 87 #define MSTATUS_SPP_SHIFT 8 88 #define MSTATUS_HPP_MASK 0x3 89 #define MSTATUS_HPP_SHIFT 9 90 #define MSTATUS_MPP_MASK 0x3 91 #define MSTATUS_MPP_SHIFT 11 92 #define MSTATUS_FS_MASK 0x3 93 #define MSTATUS_FS_SHIFT 13 94 #define MSTATUS_XS_MASK 0x3 95 #define MSTATUS_XS_SHIFT 15 96 #define MSTATUS_MPRV (1 << 17) 97 #define MSTATUS_PUM (1 << 18) 98 #define MSTATUS_VM_MASK 0x1f 99 #define MSTATUS_VM_SHIFT 24 100 #define MSTATUS_VM_MBARE 0 101 #define MSTATUS_VM_MBB 1 102 #define MSTATUS_VM_MBBID 2 103 #define MSTATUS_VM_SV32 8 104 #define MSTATUS_VM_SV39 9 105 #define MSTATUS_VM_SV48 10 106 #define MSTATUS_VM_SV57 11 107 #define MSTATUS_VM_SV64 12 108 #if __riscv_xlen == 64 109 #define MSTATUS_SD (1ul << 63) 110 #else 111 #define MSTATUS_SD (1 << 31) 112 #endif 113 114 #define MSTATUS_PRV_U 0 /* user */ 115 #define MSTATUS_PRV_S 1 /* supervisor */ 116 #define MSTATUS_PRV_H 2 /* hypervisor */ 117 #define MSTATUS_PRV_M 3 /* machine */ 118 119 #define MIE_USIE (1 << 0) 120 #define MIE_SSIE (1 << 1) 121 #define MIE_HSIE (1 << 2) 122 #define MIE_MSIE (1 << 3) 123 #define MIE_UTIE (1 << 4) 124 #define MIE_STIE (1 << 5) 125 #define MIE_HTIE (1 << 6) 126 #define MIE_MTIE (1 << 7) 127 128 #define MIP_USIP (1 << 0) 129 #define MIP_SSIP (1 << 1) 130 #define MIP_HSIP (1 << 2) 131 #define MIP_MSIP (1 << 3) 132 #define MIP_UTIP (1 << 4) 133 #define MIP_STIP (1 << 5) 134 #define MIP_HTIP (1 << 6) 135 #define MIP_MTIP (1 << 7) 136 137 #define SIE_USIE (1 << 0) 138 #define SIE_SSIE (1 << 1) 139 #define SIE_UTIE (1 << 4) 140 #define SIE_STIE (1 << 5) 141 #define SIE_UEIE (1 << 8) 142 #define SIE_SEIE (1 << 9) 143 144 #define MIP_SEIP (1 << 9) 145 146 /* Note: sip register has no SIP_STIP bit in Spike simulator */ 147 #define SIP_SSIP (1 << 1) 148 #define SIP_STIP (1 << 5) 149 150 #define SATP_PPN_S 0 151 #define SATP_PPN_M (0xfffffffffffUL << SATP_PPN_S) 152 #define SATP_ASID_S 44 153 #define SATP_ASID_M (0xffffUL << SATP_ASID_S) 154 #define SATP_MODE_S 60 155 #define SATP_MODE_M (0xfUL << SATP_MODE_S) 156 #define SATP_MODE_SV39 (8ULL << SATP_MODE_S) 157 #define SATP_MODE_SV48 (9ULL << SATP_MODE_S) 158 159 #define XLEN __riscv_xlen 160 #define XLEN_BYTES (XLEN / 8) 161 #define INSN_SIZE 4 162 #define INSN_C_SIZE 2 163 164 #define X_RA 1 165 #define X_SP 2 166 #define X_GP 3 167 #define X_TP 4 168 #define X_T0 5 169 #define X_T1 6 170 #define X_T2 7 171 #define X_T3 28 172 173 #define RD_SHIFT 7 174 #define RD_MASK (0x1f << RD_SHIFT) 175 #define RS1_SHIFT 15 176 #define RS1_MASK (0x1f << RS1_SHIFT) 177 #define RS1_SP (X_SP << RS1_SHIFT) 178 #define RS2_SHIFT 20 179 #define RS2_MASK (0x1f << RS2_SHIFT) 180 #define RS2_RA (X_RA << RS2_SHIFT) 181 #define IMM_SHIFT 20 182 #define IMM_MASK (0xfff << IMM_SHIFT) 183 184 #define RS2_C_SHIFT 2 185 #define RS2_C_MASK (0x1f << RS2_C_SHIFT) 186 #define RS2_C_RA (X_RA << RS2_C_SHIFT) 187 188 #define CSR_ZIMM(val) \ 189 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 190 191 #define csr_swap(csr, val) \ 192 ({ if (CSR_ZIMM(val)) \ 193 __asm __volatile("csrrwi %0, " #csr ", %1" \ 194 : "=r" (val) : "i" (val)); \ 195 else \ 196 __asm __volatile("csrrw %0, " #csr ", %1" \ 197 : "=r" (val) : "r" (val)); \ 198 val; \ 199 }) 200 201 #define csr_write(csr, val) \ 202 ({ if (CSR_ZIMM(val)) \ 203 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 204 else \ 205 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 206 }) 207 208 #define csr_set(csr, val) \ 209 ({ if (CSR_ZIMM(val)) \ 210 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 211 else \ 212 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 213 }) 214 215 #define csr_clear(csr, val) \ 216 ({ if (CSR_ZIMM(val)) \ 217 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 218 else \ 219 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 220 }) 221 222 #define csr_read(csr) \ 223 ({ u_long val; \ 224 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 225 val; \ 226 }) 227 228 #if __riscv_xlen == 32 229 #define csr_read64(csr) \ 230 ({ uint64_t val; \ 231 uint32_t high, low; \ 232 __asm __volatile("1: " \ 233 "csrr t0, " #csr "h\n" \ 234 "csrr %0, " #csr "\n" \ 235 "csrr %1, " #csr "h\n" \ 236 "bne t0, %1, 1b" \ 237 : "=r" (low), "=r" (high) \ 238 : \ 239 : "t0"); \ 240 val = (low | ((uint64_t)high << 32)); \ 241 val; \ 242 }) 243 #else 244 #define csr_read64(csr) ((uint64_t)csr_read(csr)) 245 #endif 246 247 #endif /* !_MACHINE_RISCVREG_H_ */ 248