1 /*- 2 * Copyright (c) 2015-2016 Nathan Whitehorn 3 * Copyright (c) 2017-2018 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/pciio.h> 37 #include <sys/endian.h> 38 #include <sys/rman.h> 39 #include <sys/vmem.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_pci.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #include <dev/ofw/ofwpci.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr_machdep.h> 52 #include <machine/md_var.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include "pcib_if.h" 58 #include "pic_if.h" 59 #include "iommu_if.h" 60 #include "opal.h" 61 62 #define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL) 63 #define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL) 64 #define OPAL_PCI_TCE_R (1UL << 0) 65 #define OPAL_PCI_TCE_W (1UL << 1) 66 #define PHB3_TCE_KILL_INVAL_ALL (1UL << 63) 67 68 /* 69 * Device interface. 70 */ 71 static int opalpci_probe(device_t); 72 static int opalpci_attach(device_t); 73 74 /* 75 * pcib interface. 76 */ 77 static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int, 78 u_int, int); 79 static void opalpci_write_config(device_t, u_int, u_int, u_int, 80 u_int, u_int32_t, int); 81 static int opalpci_alloc_msi(device_t dev, device_t child, 82 int count, int maxcount, int *irqs); 83 static int opalpci_release_msi(device_t dev, device_t child, 84 int count, int *irqs); 85 static int opalpci_alloc_msix(device_t dev, device_t child, 86 int *irq); 87 static int opalpci_release_msix(device_t dev, device_t child, 88 int irq); 89 static int opalpci_map_msi(device_t dev, device_t child, 90 int irq, uint64_t *addr, uint32_t *data); 91 static int opalpci_route_interrupt(device_t bus, device_t dev, int pin); 92 93 /* 94 * MSI PIC interface. 95 */ 96 static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector); 97 static void opalpic_pic_eoi(device_t dev, u_int irq); 98 static void opalpic_pic_mask(device_t dev, u_int irq); 99 static void opalpic_pic_unmask(device_t dev, u_int irq); 100 101 /* 102 * Commands 103 */ 104 #define OPAL_M32_WINDOW_TYPE 1 105 #define OPAL_M64_WINDOW_TYPE 2 106 #define OPAL_IO_WINDOW_TYPE 3 107 108 #define OPAL_RESET_PHB_COMPLETE 1 109 #define OPAL_RESET_PCI_IODA_TABLE 6 110 111 #define OPAL_DISABLE_M64 0 112 #define OPAL_ENABLE_M64_SPLIT 1 113 #define OPAL_ENABLE_M64_NON_SPLIT 2 114 115 #define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1 116 #define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2 117 #define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3 118 119 /* 120 * Constants 121 */ 122 #define OPAL_PCI_DEFAULT_PE 1 123 124 /* 125 * Driver methods. 126 */ 127 static device_method_t opalpci_methods[] = { 128 /* Device interface */ 129 DEVMETHOD(device_probe, opalpci_probe), 130 DEVMETHOD(device_attach, opalpci_attach), 131 132 /* pcib interface */ 133 DEVMETHOD(pcib_read_config, opalpci_read_config), 134 DEVMETHOD(pcib_write_config, opalpci_write_config), 135 136 DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi), 137 DEVMETHOD(pcib_release_msi, opalpci_release_msi), 138 DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix), 139 DEVMETHOD(pcib_release_msix, opalpci_release_msix), 140 DEVMETHOD(pcib_map_msi, opalpci_map_msi), 141 DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt), 142 143 /* PIC interface for MSIs */ 144 DEVMETHOD(pic_enable, opalpic_pic_enable), 145 DEVMETHOD(pic_eoi, opalpic_pic_eoi), 146 DEVMETHOD(pic_mask, opalpic_pic_mask), 147 DEVMETHOD(pic_unmask, opalpic_pic_unmask), 148 149 DEVMETHOD_END 150 }; 151 152 struct opalpci_softc { 153 struct ofw_pci_softc ofw_sc; 154 uint64_t phb_id; 155 vmem_t *msi_vmem; 156 int msi_base; /* Base XIVE number */ 157 int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */ 158 uint64_t *tce; /* TCE table for 1:1 mapping */ 159 struct resource *r_reg; 160 }; 161 162 static devclass_t opalpci_devclass; 163 DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods, 164 sizeof(struct opalpci_softc), ofw_pci_driver); 165 EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, opalpci_devclass, 0, 0, 166 BUS_PASS_BUS); 167 168 static int 169 opalpci_probe(device_t dev) 170 { 171 const char *type; 172 173 if (opal_check() != 0) 174 return (ENXIO); 175 176 type = ofw_bus_get_type(dev); 177 178 if (type == NULL || (strcmp(type, "pci") != 0 && 179 strcmp(type, "pciex") != 0)) 180 return (ENXIO); 181 182 if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid")) 183 return (ENXIO); 184 185 device_set_desc(dev, "OPAL Host-PCI bridge"); 186 return (BUS_PROBE_GENERIC); 187 } 188 189 static void 190 pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc) 191 { 192 193 mb(); 194 bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL); 195 mb(); 196 } 197 198 /* Simple function to round to a power of 2 */ 199 static uint64_t 200 round_pow2(uint64_t val) 201 { 202 203 return (1 << (flsl(val + (val - 1)) - 1)); 204 } 205 206 /* 207 * Starting with skiboot 5.10 PCIe nodes have a new property, 208 * "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us 209 * to avoid hard-coding the maximum TCE size allowed, and instead provide a sane 210 * default (however, the "sane" default, which works for all targets, is 64k, 211 * limiting us to 64GB if we have 1M entries. 212 */ 213 static uint64_t 214 max_tce_size(device_t dev) 215 { 216 phandle_t node; 217 cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */ 218 int count; 219 220 node = ofw_bus_get_node(dev); 221 222 count = OF_getencprop(node, "ibm,supported-tce-sizes", 223 sizes, sizeof(sizes)); 224 if (count < (int) sizeof(cell_t)) 225 return OPAL_PCI_TCE_DEFAULT_SEG_SIZE; 226 227 count /= sizeof(cell_t); 228 229 return (1ULL << sizes[count - 1]); 230 } 231 232 static int 233 opalpci_attach(device_t dev) 234 { 235 struct opalpci_softc *sc; 236 cell_t id[2], m64ranges[2], m64window[6], npe; 237 phandle_t node; 238 int i, err; 239 uint64_t maxmem; 240 uint64_t entries; 241 uint64_t tce_size; 242 uint64_t tce_tbl_size; 243 int m64bar; 244 int rid; 245 246 sc = device_get_softc(dev); 247 node = ofw_bus_get_node(dev); 248 249 switch (OF_getproplen(node, "ibm,opal-phbid")) { 250 case 8: 251 OF_getencprop(node, "ibm,opal-phbid", id, 8); 252 sc->phb_id = ((uint64_t)id[0] << 32) | id[1]; 253 break; 254 case 4: 255 OF_getencprop(node, "ibm,opal-phbid", id, 4); 256 sc->phb_id = id[0]; 257 break; 258 default: 259 device_printf(dev, "PHB ID property had wrong length (%zd)\n", 260 OF_getproplen(node, "ibm,opal-phbid")); 261 return (ENXIO); 262 } 263 264 if (bootverbose) 265 device_printf(dev, "OPAL ID %#lx\n", sc->phb_id); 266 267 rid = 0; 268 sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 269 &rid, RF_ACTIVE | RF_SHAREABLE); 270 if (sc->r_reg == NULL) { 271 device_printf(dev, "Failed to allocate PHB[%jd] registers\n", 272 (uintmax_t)sc->phb_id); 273 return (ENXIO); 274 } 275 276 #if 0 277 /* 278 * Reset PCI IODA table 279 */ 280 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE, 281 1); 282 if (err != 0) { 283 device_printf(dev, "IODA table reset failed: %d\n", err); 284 return (ENXIO); 285 } 286 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 287 1); 288 if (err < 0) { 289 device_printf(dev, "PHB reset failed: %d\n", err); 290 return (ENXIO); 291 } 292 if (err > 0) { 293 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 294 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 295 } 296 } 297 if (err < 0) { 298 device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err); 299 } 300 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 301 0); 302 if (err < 0) { 303 device_printf(dev, "PHB reset failed: %d\n", err); 304 return (ENXIO); 305 } 306 if (err > 0) { 307 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 308 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 309 } 310 } 311 #endif 312 313 /* 314 * Map all devices on the bus to partitionable endpoint one until 315 * such time as we start wanting to do things like bhyve. 316 */ 317 err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, 318 0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER, 319 OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE); 320 if (err != 0) { 321 device_printf(dev, "PE mapping failed: %d\n", err); 322 return (ENXIO); 323 } 324 325 /* 326 * Turn on MMIO, mapped to PE 1 327 */ 328 if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4) 329 npe = 1; 330 for (i = 0; i < npe; i++) { 331 err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 332 OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i); 333 if (err != 0) 334 device_printf(dev, "MMIO %d map failed: %d\n", i, err); 335 } 336 337 if (OF_getencprop(node, "ibm,opal-available-m64-ranges", 338 m64ranges, sizeof(m64ranges)) == sizeof(m64ranges)) 339 m64bar = m64ranges[0]; 340 else 341 m64bar = 0; 342 343 /* XXX: multiple M64 windows? */ 344 if (OF_getencprop(node, "ibm,opal-m64-window", 345 m64window, sizeof(m64window)) == sizeof(m64window)) { 346 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 347 OPAL_M64_WINDOW_TYPE, m64bar, 0); 348 opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id, 349 OPAL_M64_WINDOW_TYPE, m64bar /* index */, 350 ((uint64_t)m64window[2] << 32) | m64window[3], 0, 351 ((uint64_t)m64window[4] << 32) | m64window[5]); 352 opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 353 OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE, 354 m64bar /* index */, 0); 355 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 356 OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT); 357 } 358 359 /* 360 * Enable IOMMU for PE1 - map everything 1:1 using 361 * segments of max_tce_size size 362 */ 363 tce_size = max_tce_size(dev); 364 maxmem = roundup2(powerpc_ptob(Maxmem), tce_size); 365 entries = round_pow2(maxmem / tce_size); 366 tce_tbl_size = max(entries * sizeof(uint64_t), 4096); 367 if (entries > OPAL_PCI_TCE_MAX_ENTRIES) 368 panic("POWERNV supports only %jdGB of memory space\n", 369 (uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30)); 370 if (bootverbose) 371 device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem); 372 sc->tce = contigmalloc(tce_tbl_size, 373 M_DEVBUF, M_NOWAIT | M_ZERO, 0, 374 BUS_SPACE_MAXADDR, tce_size, 0); 375 if (sc->tce == NULL) 376 panic("Failed to allocate TCE memory for PHB %jd\n", 377 (uintmax_t)sc->phb_id); 378 379 for (i = 0; i < entries; i++) 380 sc->tce[i] = (i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W; 381 382 /* Map TCE for every PE. It seems necessary for Power8 */ 383 for (i = 0; i < npe; i++) { 384 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id, 385 i, (i << 1), 386 1, pmap_kextract((uint64_t)&sc->tce[0]), 387 tce_tbl_size, tce_size); 388 if (err != 0) { 389 device_printf(dev, "DMA IOMMU mapping failed: %d\n", err); 390 return (ENXIO); 391 } 392 393 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id, 394 i, (i << 1) + 1, 395 (1UL << 59), maxmem); 396 if (err != 0) { 397 device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err); 398 return (ENXIO); 399 } 400 } 401 402 /* 403 * Invalidate all previous TCE entries. 404 * 405 * TODO: add support for other PHBs than PHB3 406 */ 407 pci_phb3_tce_invalidate_entire(sc); 408 409 /* 410 * Get MSI properties 411 */ 412 sc->msi_vmem = NULL; 413 if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) { 414 cell_t msi_ranges[2]; 415 OF_getencprop(node, "ibm,opal-msi-ranges", 416 msi_ranges, sizeof(msi_ranges)); 417 sc->msi_base = msi_ranges[0]; 418 419 sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0], 420 msi_ranges[1], 1, 16, M_BESTFIT | M_WAITOK); 421 422 sc->base_msi_irq = powerpc_register_pic(dev, 423 OF_xref_from_node(node), 424 msi_ranges[0] + msi_ranges[1], 0, FALSE); 425 426 if (bootverbose) 427 device_printf(dev, "Supports %d MSIs starting at %d\n", 428 msi_ranges[1], msi_ranges[0]); 429 } 430 431 /* 432 * General OFW PCI attach 433 */ 434 err = ofw_pci_init(dev); 435 if (err != 0) 436 return (err); 437 438 /* 439 * Unfreeze non-config-space PCI operations. Let this fail silently 440 * if e.g. there is no current freeze. 441 */ 442 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE, 443 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 444 445 /* 446 * OPAL stores 64-bit BARs in a special property rather than "ranges" 447 */ 448 if (OF_getencprop(node, "ibm,opal-m64-window", 449 m64window, sizeof(m64window)) == sizeof(m64window)) { 450 struct ofw_pci_range *rp; 451 452 sc->ofw_sc.sc_nrange++; 453 sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range, 454 sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]), 455 M_DEVBUF, M_WAITOK); 456 rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1]; 457 rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 | 458 OFW_PCI_PHYS_HI_PREFETCHABLE; 459 rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1]; 460 rp->host = ((uint64_t)m64window[2] << 32) | m64window[3]; 461 rp->size = ((uint64_t)m64window[4] << 32) | m64window[5]; 462 rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci, 463 rp->pci + rp->size - 1); 464 } 465 466 return (ofw_pci_attach(dev)); 467 } 468 469 static uint32_t 470 opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 471 int width) 472 { 473 struct opalpci_softc *sc; 474 uint64_t config_addr; 475 uint8_t byte; 476 uint16_t half; 477 uint32_t word; 478 int error; 479 480 sc = device_get_softc(dev); 481 482 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 483 484 switch (width) { 485 case 1: 486 error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id, 487 config_addr, reg, vtophys(&byte)); 488 word = byte; 489 break; 490 case 2: 491 error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id, 492 config_addr, reg, vtophys(&half)); 493 word = half; 494 break; 495 case 4: 496 error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id, 497 config_addr, reg, vtophys(&word)); 498 break; 499 default: 500 error = OPAL_SUCCESS; 501 word = 0xffffffff; 502 } 503 504 /* 505 * Poking config state for non-existant devices can make 506 * the host bridge hang up. Clear any errors. 507 * 508 * XXX: Make this conditional on the existence of a freeze 509 */ 510 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE, 511 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 512 513 if (error != OPAL_SUCCESS) 514 word = 0xffffffff; 515 516 return (word); 517 } 518 519 static void 520 opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 521 u_int reg, uint32_t val, int width) 522 { 523 struct opalpci_softc *sc; 524 uint64_t config_addr; 525 int error = OPAL_SUCCESS; 526 527 sc = device_get_softc(dev); 528 529 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 530 531 switch (width) { 532 case 1: 533 error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id, 534 config_addr, reg, val); 535 break; 536 case 2: 537 error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id, 538 config_addr, reg, val); 539 break; 540 case 4: 541 error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id, 542 config_addr, reg, val); 543 break; 544 } 545 546 if (error != OPAL_SUCCESS) { 547 /* 548 * Poking config state for non-existant devices can make 549 * the host bridge hang up. Clear any errors. 550 */ 551 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, 552 OPAL_PCI_DEFAULT_PE, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 553 } 554 } 555 556 static int 557 opalpci_route_interrupt(device_t bus, device_t dev, int pin) 558 { 559 560 return (pin); 561 } 562 563 static int 564 opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount, 565 int *irqs) 566 { 567 struct opalpci_softc *sc; 568 vmem_addr_t start; 569 phandle_t xref; 570 int err, i; 571 572 sc = device_get_softc(dev); 573 if (sc->msi_vmem == NULL) 574 return (ENODEV); 575 576 err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0, 577 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 578 579 if (err) 580 return (err); 581 582 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 583 for (i = 0; i < count; i++) 584 irqs[i] = MAP_IRQ(xref, start + i); 585 586 return (0); 587 } 588 589 static int 590 opalpci_release_msi(device_t dev, device_t child, int count, int *irqs) 591 { 592 struct opalpci_softc *sc; 593 594 sc = device_get_softc(dev); 595 if (sc->msi_vmem == NULL) 596 return (ENODEV); 597 598 vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count); 599 return (0); 600 } 601 602 static int 603 opalpci_alloc_msix(device_t dev, device_t child, int *irq) 604 { 605 return (opalpci_alloc_msi(dev, child, 1, 1, irq)); 606 } 607 608 static int 609 opalpci_release_msix(device_t dev, device_t child, int irq) 610 { 611 return (opalpci_release_msi(dev, child, 1, &irq)); 612 } 613 614 static int 615 opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 616 uint32_t *data) 617 { 618 struct opalpci_softc *sc; 619 struct pci_devinfo *dinfo; 620 int err, xive; 621 622 sc = device_get_softc(dev); 623 if (sc->msi_vmem == NULL) 624 return (ENODEV); 625 626 xive = irq - sc->base_msi_irq - sc->msi_base; 627 opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive); 628 629 dinfo = device_get_ivars(child); 630 if (dinfo->cfg.msi.msi_alloc > 0 && 631 (dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) { 632 uint32_t msi32; 633 err = opal_call(OPAL_GET_MSI_32, sc->phb_id, 634 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32), 635 vtophys(data)); 636 *addr = be32toh(msi32); 637 } else { 638 err = opal_call(OPAL_GET_MSI_64, sc->phb_id, 639 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data)); 640 *addr = be64toh(*addr); 641 } 642 *data = be32toh(*data); 643 644 if (bootverbose && err != 0) 645 device_printf(child, "OPAL MSI mapping error: %d\n", err); 646 647 return ((err == 0) ? 0 : ENXIO); 648 } 649 650 static void 651 opalpic_pic_enable(device_t dev, u_int irq, u_int vector) 652 { 653 PIC_ENABLE(root_pic, irq, vector); 654 } 655 656 static void opalpic_pic_eoi(device_t dev, u_int irq) 657 { 658 struct opalpci_softc *sc; 659 660 sc = device_get_softc(dev); 661 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq); 662 663 PIC_EOI(root_pic, irq); 664 } 665 666 static void opalpic_pic_mask(device_t dev, u_int irq) 667 { 668 PIC_MASK(root_pic, irq); 669 } 670 671 static void opalpic_pic_unmask(device_t dev, u_int irq) 672 { 673 struct opalpci_softc *sc; 674 675 sc = device_get_softc(dev); 676 677 PIC_UNMASK(root_pic, irq); 678 679 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq); 680 } 681 682 683