1 /*- 2 * Copyright 2004 by Peter Grehan. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * Mac 'Kauai' PCI ATA controller 33 */ 34 #include "opt_ata.h" 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/malloc.h> 41 #include <sys/sema.h> 42 #include <sys/taskqueue.h> 43 #include <vm/uma.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <sys/ata.h> 49 #include <dev/ata/ata-all.h> 50 #include <ata_if.h> 51 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <machine/intr_machdep.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 59 #include "ata_dbdma.h" 60 61 #define ATA_KAUAI_REGOFFSET 0x2000 62 #define ATA_KAUAI_DBDMAOFFSET 0x1000 63 64 /* 65 * Offset to alt-control register from base 66 */ 67 #define ATA_KAUAI_ALTOFFSET (ATA_KAUAI_REGOFFSET + 0x160) 68 69 /* 70 * Define the gap between registers 71 */ 72 #define ATA_KAUAI_REGGAP 16 73 74 /* 75 * PIO and DMA access registers 76 */ 77 #define PIO_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x200) 78 #define UDMA_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x210) 79 #define DMA_IRQ_REG (ATA_KAUAI_REGOFFSET + 0x300) 80 81 #define USE_DBDMA_IRQ 0 82 83 /* 84 * Define the kauai pci bus attachment. 85 */ 86 static int ata_kauai_probe(device_t dev); 87 static int ata_kauai_attach(device_t dev); 88 static int ata_kauai_setmode(device_t dev, int target, int mode); 89 static int ata_kauai_begin_transaction(struct ata_request *request); 90 91 static device_method_t ata_kauai_methods[] = { 92 /* Device interface */ 93 DEVMETHOD(device_probe, ata_kauai_probe), 94 DEVMETHOD(device_attach, ata_kauai_attach), 95 DEVMETHOD(device_detach, bus_generic_detach), 96 DEVMETHOD(device_shutdown, bus_generic_shutdown), 97 DEVMETHOD(device_suspend, bus_generic_suspend), 98 DEVMETHOD(device_resume, bus_generic_resume), 99 100 /* ATA interface */ 101 DEVMETHOD(ata_setmode, ata_kauai_setmode), 102 { 0, 0 } 103 }; 104 105 struct ata_kauai_softc { 106 struct ata_dbdma_channel sc_ch; 107 108 struct resource *sc_memr; 109 110 int shasta; 111 112 uint32_t udmaconf[2]; 113 uint32_t wdmaconf[2]; 114 uint32_t pioconf[2]; 115 }; 116 117 static driver_t ata_kauai_driver = { 118 "ata", 119 ata_kauai_methods, 120 sizeof(struct ata_kauai_softc), 121 }; 122 123 DRIVER_MODULE(ata, pci, ata_kauai_driver, ata_devclass, 0, 0); 124 MODULE_DEPEND(ata, ata, 1, 1, 1); 125 126 /* 127 * PCI ID search table 128 */ 129 static struct kauai_pci_dev { 130 u_int32_t kpd_devid; 131 char *kpd_desc; 132 } kauai_pci_devlist[] = { 133 { 0x0033106b, "Uninorth2 Kauai ATA Controller" }, 134 { 0x003b106b, "Intrepid Kauai ATA Controller" }, 135 { 0x0043106b, "K2 Kauai ATA Controller" }, 136 { 0x0050106b, "Shasta Kauai ATA Controller" }, 137 { 0x0069106b, "Intrepid-2 Kauai ATA Controller" }, 138 { 0, NULL } 139 }; 140 141 /* 142 * IDE transfer timings 143 */ 144 #define KAUAI_PIO_MASK 0xff000fff 145 #define KAUAI_DMA_MASK 0x00fff000 146 #define KAUAI_UDMA_MASK 0x0000ffff 147 148 static const u_int pio_timing_kauai[] = { 149 0x08000a92, /* PIO0 */ 150 0x0800060f, /* PIO1 */ 151 0x0800038b, /* PIO2 */ 152 0x05000249, /* PIO3 */ 153 0x04000148 /* PIO4 */ 154 }; 155 static const u_int pio_timing_shasta[] = { 156 0x0a000c97, /* PIO0 */ 157 0x07000712, /* PIO1 */ 158 0x040003cd, /* PIO2 */ 159 0x0400028b, /* PIO3 */ 160 0x0400010a /* PIO4 */ 161 }; 162 163 static const u_int dma_timing_kauai[] = { 164 0x00618000, /* WDMA0 */ 165 0x00209000, /* WDMA1 */ 166 0x00148000 /* WDMA2 */ 167 }; 168 static const u_int dma_timing_shasta[] = { 169 0x00820800, /* WDMA0 */ 170 0x0028b000, /* WDMA1 */ 171 0x001ca000 /* WDMA2 */ 172 }; 173 174 static const u_int udma_timing_kauai[] = { 175 0x000070c1, /* UDMA0 */ 176 0x00005d81, /* UDMA1 */ 177 0x00004a61, /* UDMA2 */ 178 0x00003a51, /* UDMA3 */ 179 0x00002a31, /* UDMA4 */ 180 0x00002921 /* UDMA5 */ 181 }; 182 static const u_int udma_timing_shasta[] = { 183 0x00035901, /* UDMA0 */ 184 0x000348b1, /* UDMA1 */ 185 0x00033881, /* UDMA2 */ 186 0x00033861, /* UDMA3 */ 187 0x00033841, /* UDMA4 */ 188 0x00033031, /* UDMA5 */ 189 0x00033021 /* UDMA6 */ 190 }; 191 192 static int 193 ata_kauai_probe(device_t dev) 194 { 195 struct ata_channel *ch; 196 struct ata_kauai_softc *sc; 197 u_int32_t devid; 198 phandle_t node; 199 const char *compatstring = NULL; 200 int i, found, rid; 201 202 found = 0; 203 devid = pci_get_devid(dev); 204 for (i = 0; kauai_pci_devlist[i].kpd_desc != NULL; i++) { 205 if (devid == kauai_pci_devlist[i].kpd_devid) { 206 found = 1; 207 device_set_desc(dev, kauai_pci_devlist[i].kpd_desc); 208 } 209 } 210 211 if (!found) 212 return (ENXIO); 213 214 node = ofw_bus_get_node(dev); 215 sc = device_get_softc(dev); 216 bzero(sc, sizeof(struct ata_kauai_softc)); 217 ch = &sc->sc_ch.sc_ch; 218 219 compatstring = ofw_bus_get_compat(dev); 220 if (compatstring != NULL && strcmp(compatstring,"shasta-ata") == 0) 221 sc->shasta = 1; 222 223 /* Regular Kauai controllers apparently need this hack */ 224 if (!sc->shasta) 225 bus_set_resource(dev, SYS_RES_IRQ, 0, 39, 1); 226 227 rid = PCIR_BARS; 228 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 229 RF_ACTIVE); 230 if (sc->sc_memr == NULL) { 231 device_printf(dev, "could not allocate memory\n"); 232 return (ENXIO); 233 } 234 235 /* 236 * Set up the resource vectors 237 */ 238 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 239 ch->r_io[i].res = sc->sc_memr; 240 ch->r_io[i].offset = i*ATA_KAUAI_REGGAP + ATA_KAUAI_REGOFFSET; 241 } 242 ch->r_io[ATA_CONTROL].res = sc->sc_memr; 243 ch->r_io[ATA_CONTROL].offset = ATA_KAUAI_ALTOFFSET; 244 ata_default_registers(dev); 245 246 ch->unit = 0; 247 ch->flags |= ATA_USE_16BIT; 248 ata_generic_hw(dev); 249 250 return (ata_probe(dev)); 251 } 252 253 #if USE_DBDMA_IRQ 254 static int 255 ata_kauai_dma_interrupt(struct ata_kauai_softc *sc) 256 { 257 /* Clear the DMA interrupt bits */ 258 259 bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000); 260 261 return ata_interrupt(sc); 262 } 263 #endif 264 265 static int 266 ata_kauai_attach(device_t dev) 267 { 268 struct ata_kauai_softc *sc = device_get_softc(dev); 269 #if USE_DBDMA_IRQ 270 int dbdma_irq_rid = 1; 271 struct resource *dbdma_irq; 272 void *cookie; 273 #endif 274 275 pci_enable_busmaster(dev); 276 277 /* Init DMA engine */ 278 279 sc->sc_ch.dbdma_rid = 1; 280 sc->sc_ch.dbdma_regs = sc->sc_memr; 281 sc->sc_ch.dbdma_offset = ATA_KAUAI_DBDMAOFFSET; 282 283 ata_dbdma_dmainit(dev); 284 285 #if USE_DBDMA_IRQ 286 /* Bind to DBDMA interrupt as well */ 287 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 288 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) { 289 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL, 290 (driver_intr_t *)ata_kauai_dma_interrupt, sc,&cookie); 291 } 292 #endif 293 294 /* Set up initial mode */ 295 sc->pioconf[0] = sc->pioconf[1] = 296 bus_read_4(sc->sc_memr, PIO_CONFIG_REG) & 0x0f000fff; 297 298 sc->udmaconf[0] = sc->udmaconf[1] = 0; 299 sc->wdmaconf[0] = sc->wdmaconf[1] = 0; 300 301 /* Magic FCR value from Apple */ 302 bus_write_4(sc->sc_memr, 0, 0x00000007); 303 304 /* Set begin_transaction */ 305 sc->sc_ch.sc_ch.hw.begin_transaction = ata_kauai_begin_transaction; 306 307 return ata_attach(dev); 308 } 309 310 static int 311 ata_kauai_setmode(device_t dev, int target, int mode) 312 { 313 struct ata_kauai_softc *sc = device_get_softc(dev); 314 315 mode = min(mode,sc->shasta ? ATA_UDMA6 : ATA_UDMA5); 316 317 if (sc->shasta) { 318 switch (mode & ATA_DMA_MASK) { 319 case ATA_UDMA0: 320 sc->udmaconf[target] 321 = udma_timing_shasta[mode & ATA_MODE_MASK]; 322 break; 323 case ATA_WDMA0: 324 sc->udmaconf[target] = 0; 325 sc->wdmaconf[target] 326 = dma_timing_shasta[mode & ATA_MODE_MASK]; 327 break; 328 default: 329 sc->pioconf[target] 330 = pio_timing_shasta[(mode & ATA_MODE_MASK) - 331 ATA_PIO0]; 332 break; 333 } 334 } else { 335 switch (mode & ATA_DMA_MASK) { 336 case ATA_UDMA0: 337 sc->udmaconf[target] 338 = udma_timing_kauai[mode & ATA_MODE_MASK]; 339 break; 340 case ATA_WDMA0: 341 sc->udmaconf[target] = 0; 342 sc->wdmaconf[target] 343 = dma_timing_kauai[mode & ATA_MODE_MASK]; 344 break; 345 default: 346 sc->pioconf[target] 347 = pio_timing_kauai[(mode & ATA_MODE_MASK) 348 - ATA_PIO0]; 349 break; 350 } 351 } 352 353 return (mode); 354 } 355 356 static int 357 ata_kauai_begin_transaction(struct ata_request *request) 358 { 359 struct ata_kauai_softc *sc = device_get_softc(request->parent); 360 361 bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]); 362 bus_write_4(sc->sc_memr, PIO_CONFIG_REG, 363 sc->wdmaconf[request->unit] | sc->pioconf[request->unit]); 364 365 return ata_begin_transaction(request); 366 } 367 368