xref: /freebsd/sys/powerpc/powermac/ata_dbdma.c (revision 71e3c3083b47ad0f04322c5a1173377433c05a6e)
1b7382e09SNathan Whitehorn /*-
2*71e3c308SPedro F. Giffuni  * SPDX-License-Identifier: BSD-3-Clause
3*71e3c308SPedro F. Giffuni  *
4b7382e09SNathan Whitehorn  * Copyright 2008 by Nathan Whitehorn. All rights reserved.
5b7382e09SNathan Whitehorn  *
6b7382e09SNathan Whitehorn  * Redistribution and use in source and binary forms, with or without
7b7382e09SNathan Whitehorn  * modification, are permitted provided that the following conditions
8b7382e09SNathan Whitehorn  * are met:
9b7382e09SNathan Whitehorn  * 1. Redistributions of source code must retain the above copyright
10b7382e09SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer.
11b7382e09SNathan Whitehorn  * 2. Redistributions in binary form must reproduce the above copyright
12b7382e09SNathan Whitehorn  *    notice, this list of conditions and the following disclaimer in the
13b7382e09SNathan Whitehorn  *    documentation and/or other materials provided with the distribution.
14b7382e09SNathan Whitehorn  * 3. The name of the author may not be used to endorse or promote products
15b7382e09SNathan Whitehorn  *    derived from this software without specific prior written permission.
16b7382e09SNathan Whitehorn  *
17b7382e09SNathan Whitehorn  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18b7382e09SNathan Whitehorn  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19b7382e09SNathan Whitehorn  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20b7382e09SNathan Whitehorn  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21b7382e09SNathan Whitehorn  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22b7382e09SNathan Whitehorn  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23b7382e09SNathan Whitehorn  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24b7382e09SNathan Whitehorn  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25b7382e09SNathan Whitehorn  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26b7382e09SNathan Whitehorn  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27b7382e09SNathan Whitehorn  * SUCH DAMAGE.
28b7382e09SNathan Whitehorn  */
29b7382e09SNathan Whitehorn 
30d2ce15bdSMarius Strobl #include <sys/cdefs.h>
31d2ce15bdSMarius Strobl __FBSDID("* $FreeBSD$");
32d2ce15bdSMarius Strobl 
33b7382e09SNathan Whitehorn /*
34b7382e09SNathan Whitehorn  * Common routines for the DMA engine on both the Apple Kauai and MacIO
35b7382e09SNathan Whitehorn  * ATA controllers.
36b7382e09SNathan Whitehorn  */
37b7382e09SNathan Whitehorn 
38b7382e09SNathan Whitehorn #include <sys/param.h>
39b7382e09SNathan Whitehorn #include <sys/systm.h>
40b7382e09SNathan Whitehorn #include <sys/kernel.h>
41b7382e09SNathan Whitehorn #include <sys/module.h>
42b7382e09SNathan Whitehorn #include <sys/bus.h>
43b7382e09SNathan Whitehorn #include <sys/malloc.h>
44b7382e09SNathan Whitehorn #include <sys/sema.h>
45b7382e09SNathan Whitehorn #include <sys/taskqueue.h>
46b7382e09SNathan Whitehorn #include <vm/uma.h>
47b7382e09SNathan Whitehorn #include <machine/stdarg.h>
48b7382e09SNathan Whitehorn #include <machine/resource.h>
49b7382e09SNathan Whitehorn #include <machine/bus.h>
50b7382e09SNathan Whitehorn #include <sys/rman.h>
51b7382e09SNathan Whitehorn #include <sys/ata.h>
52b7382e09SNathan Whitehorn #include <dev/ata/ata-all.h>
53b7382e09SNathan Whitehorn #include <dev/ata/ata-pci.h>
54b7382e09SNathan Whitehorn #include <ata_if.h>
55b7382e09SNathan Whitehorn 
56b7382e09SNathan Whitehorn #include "ata_dbdma.h"
57b7382e09SNathan Whitehorn 
58b7382e09SNathan Whitehorn struct ata_dbdma_dmaload_args {
59b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc;
60b7382e09SNathan Whitehorn 
61b7382e09SNathan Whitehorn 	int write;
62b7382e09SNathan Whitehorn 	int nsegs;
63b7382e09SNathan Whitehorn };
64b7382e09SNathan Whitehorn 
65b7382e09SNathan Whitehorn static void
66b7382e09SNathan Whitehorn ata_dbdma_setprd(void *xarg, bus_dma_segment_t *segs, int nsegs, int error)
67b7382e09SNathan Whitehorn {
68b7382e09SNathan Whitehorn 	struct ata_dbdma_dmaload_args *arg = xarg;
69b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = arg->sc;
70b7382e09SNathan Whitehorn 	int branch_type, command;
71b7382e09SNathan Whitehorn 	int prev_stop;
72b7382e09SNathan Whitehorn 	int i;
73b7382e09SNathan Whitehorn 
74b7382e09SNathan Whitehorn 	mtx_lock(&sc->dbdma_mtx);
75b7382e09SNathan Whitehorn 
76b7382e09SNathan Whitehorn 	prev_stop = sc->next_dma_slot-1;
77b7382e09SNathan Whitehorn 	if (prev_stop < 0)
78b7382e09SNathan Whitehorn 		prev_stop = 0xff;
79b7382e09SNathan Whitehorn 
80b7382e09SNathan Whitehorn 	for (i = 0; i < nsegs; i++) {
81b7382e09SNathan Whitehorn 		/* Loop back to the beginning if this is our last slot */
82b7382e09SNathan Whitehorn 		if (sc->next_dma_slot == 0xff)
83b7382e09SNathan Whitehorn 			branch_type = DBDMA_ALWAYS;
84b7382e09SNathan Whitehorn 		else
85b7382e09SNathan Whitehorn 			branch_type = DBDMA_NEVER;
86b7382e09SNathan Whitehorn 
87b7382e09SNathan Whitehorn 		if (arg->write) {
88b7382e09SNathan Whitehorn 			command = (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE :
89b7382e09SNathan Whitehorn 			    DBDMA_OUTPUT_LAST;
90b7382e09SNathan Whitehorn 		} else {
91b7382e09SNathan Whitehorn 			command = (i + 1 < nsegs) ? DBDMA_INPUT_MORE :
92b7382e09SNathan Whitehorn 			    DBDMA_INPUT_LAST;
93b7382e09SNathan Whitehorn 		}
94b7382e09SNathan Whitehorn 
95b7382e09SNathan Whitehorn 		dbdma_insert_command(sc->dbdma, sc->next_dma_slot++,
96b7382e09SNathan Whitehorn 		    command, 0, segs[i].ds_addr, segs[i].ds_len,
97b7382e09SNathan Whitehorn 		    DBDMA_NEVER, branch_type, DBDMA_NEVER, 0);
98b7382e09SNathan Whitehorn 
99b7382e09SNathan Whitehorn 		if (branch_type == DBDMA_ALWAYS)
100b7382e09SNathan Whitehorn 			sc->next_dma_slot = 0;
101b7382e09SNathan Whitehorn 	}
102b7382e09SNathan Whitehorn 
103b7382e09SNathan Whitehorn 	/* We have a corner case where the STOP command is the last slot,
104b7382e09SNathan Whitehorn 	 * but you can't branch in STOP commands. So add a NOP branch here
105b7382e09SNathan Whitehorn 	 * and the STOP in slot 0. */
106b7382e09SNathan Whitehorn 
107b7382e09SNathan Whitehorn 	if (sc->next_dma_slot == 0xff) {
108b7382e09SNathan Whitehorn 		dbdma_insert_branch(sc->dbdma, sc->next_dma_slot, 0);
109b7382e09SNathan Whitehorn 		sc->next_dma_slot = 0;
110b7382e09SNathan Whitehorn 	}
111b7382e09SNathan Whitehorn 
112b7382e09SNathan Whitehorn #if 0
113b7382e09SNathan Whitehorn 	dbdma_insert_command(sc->dbdma, sc->next_dma_slot++,
114b7382e09SNathan Whitehorn 	    DBDMA_NOP, 0, 0, 0, DBDMA_ALWAYS, DBDMA_NEVER, DBDMA_NEVER, 0);
115b7382e09SNathan Whitehorn #endif
116b7382e09SNathan Whitehorn 	dbdma_insert_stop(sc->dbdma, sc->next_dma_slot++);
117b7382e09SNathan Whitehorn 	dbdma_insert_nop(sc->dbdma, prev_stop);
118b7382e09SNathan Whitehorn 
119b7382e09SNathan Whitehorn 	dbdma_sync_commands(sc->dbdma, BUS_DMASYNC_PREWRITE);
120b7382e09SNathan Whitehorn 
121b7382e09SNathan Whitehorn 	mtx_unlock(&sc->dbdma_mtx);
122b7382e09SNathan Whitehorn 
123b7382e09SNathan Whitehorn 	arg->nsegs = nsegs;
124b7382e09SNathan Whitehorn }
125b7382e09SNathan Whitehorn 
126b7382e09SNathan Whitehorn static int
127b7382e09SNathan Whitehorn ata_dbdma_status(device_t dev)
128b7382e09SNathan Whitehorn {
129b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = device_get_softc(dev);
130b7382e09SNathan Whitehorn 	struct ata_channel *ch = device_get_softc(dev);
131b7382e09SNathan Whitehorn 
132b7382e09SNathan Whitehorn 	if (sc->sc_ch.dma.flags & ATA_DMA_ACTIVE) {
133b7382e09SNathan Whitehorn 		return (!(dbdma_get_chan_status(sc->dbdma) &
134b7382e09SNathan Whitehorn 		    DBDMA_STATUS_ACTIVE));
135b7382e09SNathan Whitehorn 	}
136b7382e09SNathan Whitehorn 
137b7382e09SNathan Whitehorn 	if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
138b7382e09SNathan Whitehorn 		DELAY(100);
139b7382e09SNathan Whitehorn 		if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
140b7382e09SNathan Whitehorn 			return 0;
141b7382e09SNathan Whitehorn 	}
142b7382e09SNathan Whitehorn 	return 1;
143b7382e09SNathan Whitehorn }
144b7382e09SNathan Whitehorn 
145b7382e09SNathan Whitehorn static int
146b7382e09SNathan Whitehorn ata_dbdma_start(struct ata_request *request)
147b7382e09SNathan Whitehorn {
148b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = device_get_softc(request->parent);
149b7382e09SNathan Whitehorn 
150b7382e09SNathan Whitehorn 	sc->sc_ch.dma.flags |= ATA_DMA_ACTIVE;
151b7382e09SNathan Whitehorn 	dbdma_wake(sc->dbdma);
152b7382e09SNathan Whitehorn 	return 0;
153b7382e09SNathan Whitehorn }
154b7382e09SNathan Whitehorn 
155b7382e09SNathan Whitehorn static void
156b7382e09SNathan Whitehorn ata_dbdma_reset(device_t dev)
157b7382e09SNathan Whitehorn {
158b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = device_get_softc(dev);
159b7382e09SNathan Whitehorn 
160b7382e09SNathan Whitehorn 	mtx_lock(&sc->dbdma_mtx);
161b7382e09SNathan Whitehorn 
162b7382e09SNathan Whitehorn 	dbdma_stop(sc->dbdma);
163b7382e09SNathan Whitehorn 	dbdma_insert_stop(sc->dbdma, 0);
164b7382e09SNathan Whitehorn 	sc->next_dma_slot=1;
165b7382e09SNathan Whitehorn 	dbdma_set_current_cmd(sc->dbdma, 0);
166b7382e09SNathan Whitehorn 
167b7382e09SNathan Whitehorn 	sc->sc_ch.dma.flags &= ~ATA_DMA_ACTIVE;
168b7382e09SNathan Whitehorn 
169b7382e09SNathan Whitehorn 	mtx_unlock(&sc->dbdma_mtx);
170b7382e09SNathan Whitehorn }
171b7382e09SNathan Whitehorn 
172b7382e09SNathan Whitehorn static int
173b7382e09SNathan Whitehorn ata_dbdma_stop(struct ata_request *request)
174b7382e09SNathan Whitehorn {
175b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = device_get_softc(request->parent);
176b7382e09SNathan Whitehorn 
177b7382e09SNathan Whitehorn 	uint16_t status;
178b7382e09SNathan Whitehorn 
179b7382e09SNathan Whitehorn 	status = dbdma_get_chan_status(sc->dbdma);
180b7382e09SNathan Whitehorn 
181b7382e09SNathan Whitehorn 	dbdma_pause(sc->dbdma);
182b7382e09SNathan Whitehorn 	sc->sc_ch.dma.flags &= ~ATA_DMA_ACTIVE;
183b7382e09SNathan Whitehorn 
184b7382e09SNathan Whitehorn 	if (status & DBDMA_STATUS_DEAD) {
185b7382e09SNathan Whitehorn 		device_printf(request->parent,"DBDMA dead, resetting "
186b7382e09SNathan Whitehorn 		    "channel...\n");
187b7382e09SNathan Whitehorn 		ata_dbdma_reset(request->parent);
188b7382e09SNathan Whitehorn 		return ATA_S_ERROR;
189b7382e09SNathan Whitehorn 	}
190b7382e09SNathan Whitehorn 
191b7382e09SNathan Whitehorn 	if (!(status & DBDMA_STATUS_RUN)) {
192b7382e09SNathan Whitehorn 		device_printf(request->parent,"DBDMA confused, stop called "
193b7382e09SNathan Whitehorn 		    "when channel is not running!\n");
194b7382e09SNathan Whitehorn 		return ATA_S_ERROR;
195b7382e09SNathan Whitehorn 	}
196b7382e09SNathan Whitehorn 
197b7382e09SNathan Whitehorn 	if (status & DBDMA_STATUS_ACTIVE) {
198b7382e09SNathan Whitehorn 		device_printf(request->parent,"DBDMA channel stopped "
199b7382e09SNathan Whitehorn 		    "prematurely\n");
200b7382e09SNathan Whitehorn 		return ATA_S_ERROR;
201b7382e09SNathan Whitehorn 	}
202b7382e09SNathan Whitehorn 	return 0;
203b7382e09SNathan Whitehorn }
204b7382e09SNathan Whitehorn 
205b7382e09SNathan Whitehorn static int
206b7382e09SNathan Whitehorn ata_dbdma_load(struct ata_request *request, void *addr, int *entries)
207b7382e09SNathan Whitehorn {
208b7382e09SNathan Whitehorn 	struct ata_channel *ch = device_get_softc(request->parent);
209b7382e09SNathan Whitehorn 	struct ata_dbdma_dmaload_args args;
210b7382e09SNathan Whitehorn 
211b7382e09SNathan Whitehorn 	int error;
212b7382e09SNathan Whitehorn 
213b7382e09SNathan Whitehorn 	args.sc = device_get_softc(request->parent);
214b7382e09SNathan Whitehorn 	args.write = !(request->flags & ATA_R_READ);
215b7382e09SNathan Whitehorn 
216b7382e09SNathan Whitehorn 	if (!request->bytecount) {
217b7382e09SNathan Whitehorn 		device_printf(request->dev,
218b7382e09SNathan Whitehorn 		    "FAILURE - zero length DMA transfer attempted\n");
219b7382e09SNathan Whitehorn 		return EIO;
220b7382e09SNathan Whitehorn 	}
221b7382e09SNathan Whitehorn 	if (((uintptr_t)(request->data) & (ch->dma.alignment - 1)) ||
222b7382e09SNathan Whitehorn 	    (request->bytecount & (ch->dma.alignment - 1))) {
223b7382e09SNathan Whitehorn 		device_printf(request->dev,
224b7382e09SNathan Whitehorn 		    "FAILURE - non aligned DMA transfer attempted\n");
225b7382e09SNathan Whitehorn 		return EIO;
226b7382e09SNathan Whitehorn 	}
227b7382e09SNathan Whitehorn 	if (request->bytecount > ch->dma.max_iosize) {
228b7382e09SNathan Whitehorn 		device_printf(request->dev,
229b7382e09SNathan Whitehorn 		    "FAILURE - oversized DMA transfer attempt %d > %d\n",
230b7382e09SNathan Whitehorn 		    request->bytecount, ch->dma.max_iosize);
231b7382e09SNathan Whitehorn 		return EIO;
232b7382e09SNathan Whitehorn 	}
233b7382e09SNathan Whitehorn 
234066f913aSAlexander Motin 	request->dma = &ch->dma.slot[0];
235b7382e09SNathan Whitehorn 
236b7382e09SNathan Whitehorn 	if ((error = bus_dmamap_load(request->dma->data_tag,
237b7382e09SNathan Whitehorn 	    request->dma->data_map, request->data, request->bytecount,
238b7382e09SNathan Whitehorn 	    &ata_dbdma_setprd, &args, BUS_DMA_NOWAIT))) {
239b7382e09SNathan Whitehorn 		device_printf(request->dev, "FAILURE - load data\n");
240b7382e09SNathan Whitehorn 		goto error;
241b7382e09SNathan Whitehorn 	}
242b7382e09SNathan Whitehorn 
243b7382e09SNathan Whitehorn 	if (entries)
244b7382e09SNathan Whitehorn 		*entries = args.nsegs;
245b7382e09SNathan Whitehorn 
246b7382e09SNathan Whitehorn 	bus_dmamap_sync(request->dma->sg_tag, request->dma->sg_map,
247b7382e09SNathan Whitehorn 	    BUS_DMASYNC_PREWRITE);
248b7382e09SNathan Whitehorn 	bus_dmamap_sync(request->dma->data_tag, request->dma->data_map,
249b7382e09SNathan Whitehorn 	    (request->flags & ATA_R_READ) ?
250b7382e09SNathan Whitehorn 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
251b7382e09SNathan Whitehorn 
252b7382e09SNathan Whitehorn 	return 0;
253b7382e09SNathan Whitehorn 
254b7382e09SNathan Whitehorn error:
255b7382e09SNathan Whitehorn 	ch->dma.unload(request);
256b7382e09SNathan Whitehorn 	return EIO;
257b7382e09SNathan Whitehorn }
258b7382e09SNathan Whitehorn 
259b7382e09SNathan Whitehorn void
260b7382e09SNathan Whitehorn ata_dbdma_dmainit(device_t dev)
261b7382e09SNathan Whitehorn {
262b7382e09SNathan Whitehorn 	struct ata_dbdma_channel *sc = device_get_softc(dev);
263b7382e09SNathan Whitehorn 	int error;
264b7382e09SNathan Whitehorn 
265b7382e09SNathan Whitehorn 	error = dbdma_allocate_channel(sc->dbdma_regs, sc->dbdma_offset,
266b7382e09SNathan Whitehorn 	    bus_get_dma_tag(dev), 256, &sc->dbdma);
267b7382e09SNathan Whitehorn 
268b7382e09SNathan Whitehorn 	dbdma_set_wait_selector(sc->dbdma,1 << 7, 1 << 7);
269b7382e09SNathan Whitehorn 
270b7382e09SNathan Whitehorn 	dbdma_insert_stop(sc->dbdma,0);
271b7382e09SNathan Whitehorn 	sc->next_dma_slot=1;
272b7382e09SNathan Whitehorn 
273b7382e09SNathan Whitehorn 	sc->sc_ch.dma.start = ata_dbdma_start;
274b7382e09SNathan Whitehorn 	sc->sc_ch.dma.stop = ata_dbdma_stop;
275b7382e09SNathan Whitehorn 	sc->sc_ch.dma.load = ata_dbdma_load;
276b7382e09SNathan Whitehorn 	sc->sc_ch.dma.reset = ata_dbdma_reset;
277b7382e09SNathan Whitehorn 
278360bf678SNathan Whitehorn 	/*
279360bf678SNathan Whitehorn 	 * DBDMA's field for transfer size is 16 bits. This will overflow
280360bf678SNathan Whitehorn 	 * if we try to do a 64K transfer, so stop short of 64K.
281360bf678SNathan Whitehorn 	 */
282360bf678SNathan Whitehorn 	sc->sc_ch.dma.segsize = 126 * DEV_BSIZE;
283b56b04b8SMarius Strobl 	ata_dmainit(dev);
284360bf678SNathan Whitehorn 
285b7382e09SNathan Whitehorn 	sc->sc_ch.hw.status = ata_dbdma_status;
286b7382e09SNathan Whitehorn 
287b7382e09SNathan Whitehorn 	mtx_init(&sc->dbdma_mtx, "ATA DBDMA", NULL, MTX_DEF);
288b7382e09SNathan Whitehorn }
289