1 /*- 2 * Copyright (c) 2017 Justin Hibbits 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/cpu.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/smp.h> 34 35 #include <dev/ofw/ofw_bus.h> 36 #include <dev/ofw/ofw_bus_subr.h> 37 38 #include <machine/cpu.h> 39 40 #include <powerpc/mpc85xx/mpc85xx.h> 41 42 #include "cpufreq_if.h" 43 44 /* No worries about uint32_t math overflow in here, because the highest 45 * multiplier supported is 4, and the highest speed part is still well below 46 * 2GHz. 47 */ 48 49 #define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000) 50 #define GUTS_PMJCR (CCSRBAR_VA + 0xe007c) 51 #define PMJCR_RATIO_M 0x3f 52 #define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8))) 53 #define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f) 54 #define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080) 55 #define POWMGTCSR_JOG 0x00200000 56 #define POWMGTCSR_INT_MASK 0x00000f00 57 58 #define MHZ 1000000 59 60 struct mpc85xx_jog_softc { 61 device_t dev; 62 int cpu; 63 int low; 64 int high; 65 int min_freq; 66 }; 67 68 static struct ofw_compat_data *mpc85xx_jog_devcompat(void); 69 static void mpc85xx_jog_identify(driver_t *driver, device_t parent); 70 static int mpc85xx_jog_probe(device_t dev); 71 static int mpc85xx_jog_attach(device_t dev); 72 static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count); 73 static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set); 74 static int mpc85xx_jog_get(device_t dev, struct cf_setting *set); 75 static int mpc85xx_jog_type(device_t dev, int *type); 76 77 static device_method_t mpc85xx_jog_methods[] = { 78 /* Device interface */ 79 DEVMETHOD(device_identify, mpc85xx_jog_identify), 80 DEVMETHOD(device_probe, mpc85xx_jog_probe), 81 DEVMETHOD(device_attach, mpc85xx_jog_attach), 82 83 /* cpufreq interface */ 84 DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set), 85 DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get), 86 DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type), 87 DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings), 88 {0, 0} 89 }; 90 91 static driver_t mpc85xx_jog_driver = { 92 "jog", 93 mpc85xx_jog_methods, 94 sizeof(struct mpc85xx_jog_softc) 95 }; 96 97 DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, 0, 0); 98 99 struct mpc85xx_constraints { 100 int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */ 101 int min_mult; /* Minimum PLL multiplier. */ 102 }; 103 104 static struct mpc85xx_constraints mpc8536_constraints = { 105 800, 106 3 107 }; 108 109 static struct mpc85xx_constraints p1022_constraints = { 110 500, 111 2 112 }; 113 114 static struct ofw_compat_data jog_compat[] = { 115 {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints}, 116 {"fsl,p1022-guts", (uintptr_t)&p1022_constraints}, 117 {NULL, 0} 118 }; 119 120 static struct ofw_compat_data * 121 mpc85xx_jog_devcompat(void) 122 { 123 phandle_t node; 124 int i; 125 126 node = OF_finddevice("/soc"); 127 if (node == -1) 128 return (NULL); 129 130 for (i = 0; jog_compat[i].ocd_str != NULL; i++) 131 if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0) 132 break; 133 134 if (jog_compat[i].ocd_str == NULL) 135 return (NULL); 136 137 return (&jog_compat[i]); 138 } 139 140 static void 141 mpc85xx_jog_identify(driver_t *driver, device_t parent) 142 { 143 struct ofw_compat_data *compat; 144 145 /* Make sure we're not being doubly invoked. */ 146 if (device_find_child(parent, "mpc85xx_jog", -1) != NULL) 147 return; 148 149 compat = mpc85xx_jog_devcompat(); 150 if (compat == NULL) 151 return; 152 153 /* 154 * We attach a child for every CPU since settings need to 155 * be performed on every CPU in the SMP case. 156 */ 157 if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL) 158 device_printf(parent, "add jog child failed\n"); 159 } 160 161 static int 162 mpc85xx_jog_probe(device_t dev) 163 { 164 struct ofw_compat_data *compat; 165 166 compat = mpc85xx_jog_devcompat(); 167 if (compat == NULL || compat->ocd_str == NULL) 168 return (ENXIO); 169 170 device_set_desc(dev, "Freescale CPU Jogger"); 171 return (0); 172 } 173 174 static int 175 mpc85xx_jog_attach(device_t dev) 176 { 177 struct ofw_compat_data *compat; 178 struct mpc85xx_jog_softc *sc; 179 struct mpc85xx_constraints *constraints; 180 phandle_t cpu; 181 uint32_t reg; 182 183 sc = device_get_softc(dev); 184 sc->dev = dev; 185 186 compat = mpc85xx_jog_devcompat(); 187 constraints = (struct mpc85xx_constraints *)compat->ocd_data; 188 cpu = ofw_bus_get_node(device_get_parent(dev)); 189 190 if (cpu <= 0) { 191 device_printf(dev,"No CPU device tree node!\n"); 192 return (ENXIO); 193 } 194 195 OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu)); 196 197 reg = ccsr_read4(GUTS_PORPLLSR); 198 199 /* 200 * Assume power-on PLL is the highest PLL config supported on the 201 * board. 202 */ 203 sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu); 204 sc->min_freq = constraints->threshold; 205 sc->low = constraints->min_mult; 206 207 cpufreq_register(dev); 208 return (0); 209 } 210 211 static int 212 mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count) 213 { 214 struct mpc85xx_jog_softc *sc; 215 uint32_t sysclk; 216 int i; 217 218 sc = device_get_softc(dev); 219 if (sets == NULL || count == NULL) 220 return (EINVAL); 221 if (*count < sc->high - 1) 222 return (E2BIG); 223 224 sysclk = mpc85xx_get_system_clock(); 225 /* Return a list of valid settings for this driver. */ 226 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high); 227 228 for (i = sc->high; i >= sc->low; --i) { 229 sets[sc->high - i].freq = sysclk * i / MHZ; 230 sets[sc->high - i].dev = dev; 231 sets[sc->high - i].spec[0] = i; 232 } 233 *count = sc->high - sc->low + 1; 234 235 return (0); 236 } 237 238 struct jog_rv_args { 239 int cpu; 240 int mult; 241 int slow; 242 volatile int inprogress; 243 }; 244 245 static void 246 mpc85xx_jog_set_int(void *arg) 247 { 248 struct jog_rv_args *args = arg; 249 uint32_t reg; 250 251 if (PCPU_GET(cpuid) == args->cpu) { 252 reg = ccsr_read4(GUTS_PMJCR); 253 reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu); 254 reg |= PMJCR_CORE_MULT(args->mult, args->cpu); 255 if (args->slow) 256 reg &= ~(1 << (12 + args->cpu)); 257 else 258 reg |= (1 << (12 + args->cpu)); 259 260 ccsr_write4(GUTS_PMJCR, reg); 261 262 reg = ccsr_read4(GUTS_POWMGTCSR); 263 reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK; 264 ccsr_write4(GUTS_POWMGTCSR, reg); 265 266 /* Wait for completion */ 267 do { 268 DELAY(100); 269 reg = ccsr_read4(GUTS_POWMGTCSR); 270 } while (reg & POWMGTCSR_JOG); 271 272 reg = ccsr_read4(GUTS_POWMGTCSR); 273 ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK); 274 ccsr_read4(GUTS_POWMGTCSR); 275 276 args->inprogress = 0; 277 } else { 278 while (args->inprogress) 279 cpu_spinwait(); 280 } 281 } 282 283 static int 284 mpc85xx_jog_set(device_t dev, const struct cf_setting *set) 285 { 286 struct mpc85xx_jog_softc *sc; 287 struct jog_rv_args args; 288 289 if (set == NULL) 290 return (EINVAL); 291 292 sc = device_get_softc(dev); 293 294 args.slow = (set->freq <= sc->min_freq); 295 args.mult = set->spec[0]; 296 args.cpu = PCPU_GET(cpuid); 297 args.inprogress = 1; 298 smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int, 299 smp_no_rendezvous_barrier, &args); 300 301 return (0); 302 } 303 304 static int 305 mpc85xx_jog_get(device_t dev, struct cf_setting *set) 306 { 307 struct mpc85xx_jog_softc *sc; 308 uint32_t pmjcr; 309 uint32_t freq; 310 311 if (set == NULL) 312 return (EINVAL); 313 314 sc = device_get_softc(dev); 315 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 316 317 pmjcr = ccsr_read4(GUTS_PORPLLSR); 318 freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu); 319 freq *= mpc85xx_get_system_clock(); 320 freq /= MHZ; 321 322 set->freq = freq; 323 set->dev = dev; 324 325 return (0); 326 } 327 328 static int 329 mpc85xx_jog_type(device_t dev, int *type) 330 { 331 332 if (type == NULL) 333 return (EINVAL); 334 335 *type = CPUFREQ_TYPE_ABSOLUTE; 336 return (0); 337 } 338